2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/driconf.h"
48 #include "util/u_memory.h"
50 #include "common/gen_defines.h"
52 static const __DRIconfigOptionsExtension brw_config_options
= {
53 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
56 DRI_CONF_SECTION_PERFORMANCE
57 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
58 * DRI_CONF_BO_REUSE_ALL
60 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
61 DRI_CONF_DESC_BEGIN("Buffer object reuse")
62 DRI_CONF_ENUM(0, "Disable buffer object reuse")
63 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
66 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_MESA_GLTHREAD("false")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_PRECISE_TRIG("false")
73 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
74 DRI_CONF_DESC("Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
81 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
82 DRI_CONF_DISABLE_THROTTLING("false")
83 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
84 DRI_CONF_FORCE_GLSL_VERSION(0)
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
88 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
90 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
91 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
92 DRI_CONF_FORCE_COMPAT_PROFILE("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
94 DRI_CONF_FORCE_GL_VENDOR()
96 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
97 DRI_CONF_DESC("Perform code generation at shader link time.")
101 DRI_CONF_SECTION_MISCELLANEOUS
102 DRI_CONF_GLSL_ZERO_INIT("false")
103 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
104 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
105 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
106 DRI_CONF_ALLOW_FP16_CONFIGS("false")
111 #include "intel_batchbuffer.h"
112 #include "intel_buffers.h"
113 #include "brw_bufmgr.h"
114 #include "intel_fbo.h"
115 #include "intel_mipmap_tree.h"
116 #include "intel_screen.h"
117 #include "intel_tex.h"
118 #include "intel_image.h"
120 #include "brw_context.h"
122 #include "drm-uapi/i915_drm.h"
125 * For debugging purposes, this returns a time in seconds.
132 clock_gettime(CLOCK_MONOTONIC
, &tp
);
134 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
137 static const __DRItexBufferExtension intelTexBufferExtension
= {
138 .base
= { __DRI_TEX_BUFFER
, 3 },
140 .setTexBuffer
= intelSetTexBuffer
,
141 .setTexBuffer2
= intelSetTexBuffer2
,
142 .releaseTexBuffer
= intelReleaseTexBuffer
,
146 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
147 __DRIdrawable
*dPriv
,
149 enum __DRI2throttleReason reason
)
151 struct brw_context
*brw
= cPriv
->driverPrivate
;
156 struct gl_context
*ctx
= &brw
->ctx
;
158 _mesa_glthread_finish(ctx
);
160 FLUSH_VERTICES(ctx
, 0);
162 if (flags
& __DRI2_FLUSH_DRAWABLE
)
163 intel_resolve_for_dri2_flush(brw
, dPriv
);
165 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
166 brw
->need_swap_throttle
= true;
167 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
168 brw
->need_flush_throttle
= true;
170 intel_batchbuffer_flush(brw
);
174 * Provides compatibility with loaders that only support the older (version
175 * 1-3) flush interface.
177 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
180 intel_dri2_flush(__DRIdrawable
*drawable
)
182 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
183 __DRI2_FLUSH_DRAWABLE
,
184 __DRI2_THROTTLE_SWAPBUFFER
);
187 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
188 .base
= { __DRI2_FLUSH
, 4 },
190 .flush
= intel_dri2_flush
,
191 .invalidate
= dri2InvalidateDrawable
,
192 .flush_with_flags
= intel_dri2_flush_with_flags
,
195 static const struct intel_image_format intel_image_formats
[] = {
196 { DRM_FORMAT_ABGR16161616F
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F
, 8 } } },
199 { DRM_FORMAT_XBGR16161616F
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F
, 8 } } },
202 { DRM_FORMAT_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
205 { DRM_FORMAT_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
208 { DRM_FORMAT_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
211 { DRM_FORMAT_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
214 { DRM_FORMAT_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
217 { DRM_FORMAT_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
220 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
223 { __DRI_IMAGE_FOURCC_SXRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8
, 4 } } },
226 { DRM_FORMAT_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
229 { DRM_FORMAT_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
232 { DRM_FORMAT_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
235 { DRM_FORMAT_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
238 { DRM_FORMAT_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
239 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
241 { DRM_FORMAT_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
244 { DRM_FORMAT_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
247 { DRM_FORMAT_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
250 { DRM_FORMAT_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { DRM_FORMAT_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
260 { DRM_FORMAT_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
265 { DRM_FORMAT_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
270 { DRM_FORMAT_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
275 { DRM_FORMAT_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
276 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
280 { DRM_FORMAT_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
281 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
285 { DRM_FORMAT_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
286 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
287 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
290 { DRM_FORMAT_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
292 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
293 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
295 { DRM_FORMAT_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
296 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
297 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
298 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
300 { DRM_FORMAT_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
301 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
302 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
304 { DRM_FORMAT_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
305 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
306 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
308 { DRM_FORMAT_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
309 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
310 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
312 { DRM_FORMAT_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
313 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
314 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
316 { DRM_FORMAT_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
317 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
318 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
320 { DRM_FORMAT_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
321 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
323 { DRM_FORMAT_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
324 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
326 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
327 * and treat them as planar buffers in the compositors.
328 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
329 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
330 * clusters and places pairs and places U into the G component and
331 * V into A. This lets the texture sampler interpolate the Y
332 * components correctly when sampling from plane 0, and interpolate
333 * U and V correctly when sampling from plane 1. */
334 { DRM_FORMAT_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
335 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
336 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
337 { DRM_FORMAT_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
338 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
339 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
342 static const struct {
345 } supported_modifiers
[] = {
346 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
347 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
348 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
349 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
353 modifier_is_supported(const struct gen_device_info
*devinfo
,
354 const struct intel_image_format
*fmt
, int dri_format
,
357 const struct isl_drm_modifier_info
*modinfo
=
358 isl_drm_modifier_get_info(modifier
);
361 /* ISL had better know about the modifier */
365 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
366 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
367 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
370 /* CCS_E is not supported for planar images */
371 if (fmt
&& fmt
->nplanes
> 1)
375 assert(dri_format
== 0);
376 dri_format
= fmt
->planes
[0].dri_format
;
379 mesa_format format
= driImageFormatToGLFormat(dri_format
);
380 /* Whether or not we support compression is based on the RGBA non-sRGB
381 * version of the format.
383 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
384 format
= _mesa_get_srgb_format_linear(format
);
385 if (!isl_format_supports_ccs_e(devinfo
,
386 brw_isl_format_for_mesa_format(format
)))
390 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
391 if (supported_modifiers
[i
].modifier
!= modifier
)
394 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
401 tiling_to_modifier(uint32_t tiling
)
403 static const uint64_t map
[] = {
404 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
405 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
406 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
409 assert(tiling
< ARRAY_SIZE(map
));
415 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
417 uint32_t tiling
, swizzle
;
418 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
420 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
421 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
422 func
, image
->offset
);
426 static const struct intel_image_format
*
427 intel_image_format_lookup(int fourcc
)
429 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
430 if (intel_image_formats
[i
].fourcc
== fourcc
)
431 return &intel_image_formats
[i
];
438 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
440 if (image
->planar_format
) {
441 *fourcc
= image
->planar_format
->fourcc
;
445 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
446 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
447 *fourcc
= intel_image_formats
[i
].fourcc
;
455 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
460 image
= calloc(1, sizeof *image
);
464 image
->screen
= screen
;
465 image
->dri_format
= dri_format
;
468 image
->format
= driImageFormatToGLFormat(dri_format
);
469 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
470 image
->format
== MESA_FORMAT_NONE
) {
475 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
476 image
->data
= loaderPrivate
;
482 * Sets up a DRIImage structure to point to a slice out of a miptree.
485 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
486 struct intel_mipmap_tree
*mt
, GLuint level
,
489 intel_miptree_make_shareable(brw
, mt
);
491 intel_miptree_check_level_layer(mt
, level
, zoffset
);
493 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
494 level
- mt
->first_level
);
495 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
496 level
- mt
->first_level
);
497 image
->pitch
= mt
->surf
.row_pitch_B
;
499 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
503 brw_bo_unreference(image
->bo
);
505 brw_bo_reference(mt
->bo
);
509 intel_create_image_from_name(__DRIscreen
*dri_screen
,
510 int width
, int height
, int format
,
511 int name
, int pitch
, void *loaderPrivate
)
513 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
517 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
521 if (image
->format
== MESA_FORMAT_NONE
)
524 cpp
= _mesa_get_format_bytes(image
->format
);
526 image
->width
= width
;
527 image
->height
= height
;
528 image
->pitch
= pitch
* cpp
;
529 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
535 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
541 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
542 int renderbuffer
, void *loaderPrivate
)
545 struct brw_context
*brw
= context
->driverPrivate
;
546 struct gl_context
*ctx
= &brw
->ctx
;
547 struct gl_renderbuffer
*rb
;
548 struct intel_renderbuffer
*irb
;
550 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
552 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
556 irb
= intel_renderbuffer(rb
);
557 intel_miptree_make_shareable(brw
, irb
->mt
);
558 image
= calloc(1, sizeof *image
);
562 image
->internal_format
= rb
->InternalFormat
;
563 image
->format
= rb
->Format
;
564 image
->modifier
= tiling_to_modifier(
565 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
567 image
->data
= loaderPrivate
;
568 brw_bo_unreference(image
->bo
);
569 image
->bo
= irb
->mt
->bo
;
570 brw_bo_reference(irb
->mt
->bo
);
571 image
->width
= rb
->Width
;
572 image
->height
= rb
->Height
;
573 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
574 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
575 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
577 rb
->NeedsFinishRenderTexture
= true;
582 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
583 unsigned texture
, int zoffset
,
589 struct brw_context
*brw
= context
->driverPrivate
;
590 struct gl_texture_object
*obj
;
591 struct intel_texture_object
*iobj
;
594 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
595 if (!obj
|| obj
->Target
!= target
) {
596 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
600 if (target
== GL_TEXTURE_CUBE_MAP
)
603 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
604 iobj
= intel_texture_object(obj
);
605 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
606 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
610 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
611 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
615 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
616 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
619 image
= calloc(1, sizeof *image
);
621 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
625 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
626 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
627 image
->modifier
= tiling_to_modifier(
628 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
629 image
->data
= loaderPrivate
;
630 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
631 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
632 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
633 image
->planar_format
= iobj
->planar_format
;
634 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
635 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
640 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
645 intel_destroy_image(__DRIimage
*image
)
647 brw_bo_unreference(image
->bo
);
651 enum modifier_priority
{
652 MODIFIER_PRIORITY_INVALID
= 0,
653 MODIFIER_PRIORITY_LINEAR
,
656 MODIFIER_PRIORITY_Y_CCS
,
659 const uint64_t priority_to_modifier
[] = {
660 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
661 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
662 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
663 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
664 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
668 select_best_modifier(struct gen_device_info
*devinfo
,
670 const uint64_t *modifiers
,
671 const unsigned count
)
673 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
675 for (int i
= 0; i
< count
; i
++) {
676 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
679 switch (modifiers
[i
]) {
680 case I915_FORMAT_MOD_Y_TILED_CCS
:
681 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
683 case I915_FORMAT_MOD_Y_TILED
:
684 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
686 case I915_FORMAT_MOD_X_TILED
:
687 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
689 case DRM_FORMAT_MOD_LINEAR
:
690 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
692 case DRM_FORMAT_MOD_INVALID
:
698 return priority_to_modifier
[prio
];
702 intel_create_image_common(__DRIscreen
*dri_screen
,
703 int width
, int height
, int format
,
705 const uint64_t *modifiers
,
710 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
711 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
714 /* Callers of this may specify a modifier, or a dri usage, but not both. The
715 * newer modifier interface deprecates the older usage flags.
717 assert(!(use
&& count
));
719 if (use
& __DRI_IMAGE_USE_CURSOR
) {
720 if (width
!= 64 || height
!= 64)
722 modifier
= DRM_FORMAT_MOD_LINEAR
;
725 if (use
& __DRI_IMAGE_USE_LINEAR
)
726 modifier
= DRM_FORMAT_MOD_LINEAR
;
728 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
730 /* User requested specific modifiers */
731 modifier
= select_best_modifier(&screen
->devinfo
, format
,
733 if (modifier
== DRM_FORMAT_MOD_INVALID
)
736 /* Historically, X-tiled was the default, and so lack of modifier means
739 modifier
= I915_FORMAT_MOD_X_TILED
;
743 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
747 const struct isl_drm_modifier_info
*mod_info
=
748 isl_drm_modifier_get_info(modifier
);
750 struct isl_surf surf
;
751 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
752 .dim
= ISL_SURF_DIM_2D
,
753 .format
= brw_isl_format_for_mesa_format(image
->format
),
760 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
761 ISL_SURF_USAGE_TEXTURE_BIT
|
762 ISL_SURF_USAGE_STORAGE_BIT
|
763 ((use
& __DRI_IMAGE_USE_SCANOUT
) ?
764 ISL_SURF_USAGE_DISPLAY_BIT
: 0),
765 .tiling_flags
= (1 << mod_info
->tiling
));
772 struct isl_surf aux_surf
= {0,};
773 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
774 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
, 0);
780 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
784 /* We request that the bufmgr zero the buffer for us for two reasons:
786 * 1) If a buffer gets re-used from the pool, we don't want to leak random
787 * garbage from our process to some other.
789 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
790 * a valid state. A CCS value of 0 indicates that the given block is
791 * in the pass-through state which is what we want.
793 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
794 surf
.size_B
+ aux_surf
.size_B
,
796 isl_tiling_to_i915_tiling(mod_info
->tiling
),
797 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
798 if (image
->bo
== NULL
) {
802 image
->width
= width
;
803 image
->height
= height
;
804 image
->pitch
= surf
.row_pitch_B
;
805 image
->modifier
= modifier
;
807 if (aux_surf
.size_B
) {
808 image
->aux_offset
= surf
.size_B
;
809 image
->aux_pitch
= aux_surf
.row_pitch_B
;
810 image
->aux_size
= aux_surf
.size_B
;
817 intel_create_image(__DRIscreen
*dri_screen
,
818 int width
, int height
, int format
,
822 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
827 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
828 int x0
, int y0
, int width
, int height
,
829 unsigned int flags
, int *stride
, void **map_info
)
831 struct brw_context
*brw
= NULL
;
832 struct brw_bo
*bo
= NULL
;
833 void *raw_data
= NULL
;
838 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
841 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
844 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
847 if (flags
& MAP_INTERNAL_MASK
)
850 brw
= context
->driverPrivate
;
856 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
857 raw_data
= brw_bo_map(brw
, bo
, flags
);
861 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
862 pix_bytes
= _mesa_get_format_bytes(image
->format
);
866 assert(pix_bytes
> 0);
868 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
870 brw_bo_reference(bo
);
872 *stride
= image
->pitch
;
879 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
881 struct brw_bo
*bo
= map_info
;
884 brw_bo_unreference(bo
);
888 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
889 int width
, int height
, int format
,
890 const uint64_t *modifiers
,
891 const unsigned count
,
894 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
895 modifiers
, count
, loaderPrivate
);
899 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
902 case __DRI_IMAGE_ATTRIB_STRIDE
:
903 *value
= image
->pitch
;
905 case __DRI_IMAGE_ATTRIB_HANDLE
: {
906 __DRIscreen
*dri_screen
= image
->screen
->driScrnPriv
;
908 if (brw_bo_export_gem_handle_for_device(image
->bo
,
915 case __DRI_IMAGE_ATTRIB_NAME
:
916 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
917 case __DRI_IMAGE_ATTRIB_FORMAT
:
918 *value
= image
->dri_format
;
920 case __DRI_IMAGE_ATTRIB_WIDTH
:
921 *value
= image
->width
;
923 case __DRI_IMAGE_ATTRIB_HEIGHT
:
924 *value
= image
->height
;
926 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
927 if (image
->planar_format
== NULL
)
929 *value
= image
->planar_format
->components
;
931 case __DRI_IMAGE_ATTRIB_FD
:
932 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
933 case __DRI_IMAGE_ATTRIB_FOURCC
:
934 return intel_image_get_fourcc(image
, value
);
935 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
936 if (isl_drm_modifier_has_aux(image
->modifier
)) {
937 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
939 } else if (image
->planar_format
) {
940 *value
= image
->planar_format
->nplanes
;
945 case __DRI_IMAGE_ATTRIB_OFFSET
:
946 *value
= image
->offset
;
948 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
949 *value
= (image
->modifier
& 0xffffffff);
951 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
952 *value
= ((image
->modifier
>> 32) & 0xffffffff);
961 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
962 uint32_t fourcc
, uint64_t modifier
,
963 int attrib
, uint64_t *value
)
965 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
966 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
968 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
972 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
973 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
982 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
986 image
= calloc(1, sizeof *image
);
990 brw_bo_reference(orig_image
->bo
);
991 image
->screen
= orig_image
->screen
;
992 image
->bo
= orig_image
->bo
;
993 image
->internal_format
= orig_image
->internal_format
;
994 image
->planar_format
= orig_image
->planar_format
;
995 image
->dri_format
= orig_image
->dri_format
;
996 image
->format
= orig_image
->format
;
997 image
->modifier
= orig_image
->modifier
;
998 image
->offset
= orig_image
->offset
;
999 image
->width
= orig_image
->width
;
1000 image
->height
= orig_image
->height
;
1001 image
->pitch
= orig_image
->pitch
;
1002 image
->tile_x
= orig_image
->tile_x
;
1003 image
->tile_y
= orig_image
->tile_y
;
1004 image
->has_depthstencil
= orig_image
->has_depthstencil
;
1005 image
->data
= loaderPrivate
;
1006 image
->aux_offset
= orig_image
->aux_offset
;
1007 image
->aux_pitch
= orig_image
->aux_pitch
;
1009 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
1010 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
1016 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
1018 if (use
& __DRI_IMAGE_USE_CURSOR
) {
1019 if (image
->width
!= 64 || image
->height
!= 64)
1027 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1028 int width
, int height
, int fourcc
,
1029 int *names
, int num_names
,
1030 int *strides
, int *offsets
,
1031 void *loaderPrivate
)
1033 const struct intel_image_format
*f
= NULL
;
1037 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1040 f
= intel_image_format_lookup(fourcc
);
1044 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1045 __DRI_IMAGE_FORMAT_NONE
,
1046 names
[0], strides
[0],
1052 image
->planar_format
= f
;
1053 for (i
= 0; i
< f
->nplanes
; i
++) {
1054 index
= f
->planes
[i
].buffer_index
;
1055 image
->offsets
[index
] = offsets
[index
];
1056 image
->strides
[index
] = strides
[index
];
1063 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1064 int width
, int height
, int fourcc
,
1065 uint64_t modifier
, int *fds
, int num_fds
,
1066 int *strides
, int *offsets
,
1067 void *loaderPrivate
)
1069 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1070 const struct intel_image_format
*f
;
1075 if (fds
== NULL
|| num_fds
< 1)
1078 f
= intel_image_format_lookup(fourcc
);
1082 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1083 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1086 if (f
->nplanes
== 1)
1087 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1090 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1096 image
->width
= width
;
1097 image
->height
= height
;
1098 image
->pitch
= strides
[0];
1100 image
->planar_format
= f
;
1102 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1103 const struct isl_drm_modifier_info
*mod_info
=
1104 isl_drm_modifier_get_info(modifier
);
1105 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1106 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1107 tiling
, strides
[0]);
1109 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1112 if (image
->bo
== NULL
) {
1117 /* We only support all planes from the same bo.
1118 * brw_bo_gem_create_from_prime() should return the same pointer for all
1119 * fds received here */
1120 for (i
= 1; i
< num_fds
; i
++) {
1121 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1122 brw_bo_unreference(aux
);
1123 if (aux
!= image
->bo
) {
1124 brw_bo_unreference(image
->bo
);
1130 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1131 image
->modifier
= modifier
;
1133 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1135 const struct isl_drm_modifier_info
*mod_info
=
1136 isl_drm_modifier_get_info(image
->modifier
);
1139 struct isl_surf surf
;
1140 for (i
= 0; i
< f
->nplanes
; i
++) {
1141 index
= f
->planes
[i
].buffer_index
;
1142 image
->offsets
[index
] = offsets
[index
];
1143 image
->strides
[index
] = strides
[index
];
1145 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1146 /* The images we will create are actually based on the RGBA non-sRGB
1147 * version of the format.
1149 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1150 format
= _mesa_get_srgb_format_linear(format
);
1152 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1153 .dim
= ISL_SURF_DIM_2D
,
1154 .format
= brw_isl_format_for_mesa_format(format
),
1155 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1156 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1161 .row_pitch_B
= strides
[index
],
1162 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1163 ISL_SURF_USAGE_TEXTURE_BIT
|
1164 ISL_SURF_USAGE_STORAGE_BIT
,
1165 .tiling_flags
= (1 << mod_info
->tiling
));
1167 brw_bo_unreference(image
->bo
);
1172 const int end
= offsets
[index
] + surf
.size_B
;
1177 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1178 /* Even though we initialize surf in the loop above, we know that
1179 * anything with CCS_E will have exactly one plane so surf is properly
1180 * initialized when we get here.
1182 assert(f
->nplanes
== 1);
1184 image
->aux_offset
= offsets
[1];
1185 image
->aux_pitch
= strides
[1];
1187 /* Scanout hardware requires that the CCS be placed after the main
1188 * surface in memory. We consider any CCS that is placed any earlier in
1189 * memory to be invalid and reject it.
1191 * At some point in the future, this restriction may be relaxed if the
1192 * hardware becomes less strict but we may need a new modifier for that.
1195 if (image
->aux_offset
< size
) {
1196 brw_bo_unreference(image
->bo
);
1201 struct isl_surf aux_surf
= {0,};
1202 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
,
1205 brw_bo_unreference(image
->bo
);
1210 image
->aux_size
= aux_surf
.size_B
;
1212 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1216 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1219 /* Check that the requested image actually fits within the BO. 'size'
1220 * is already relative to the offsets, so we don't need to add that. */
1221 if (image
->bo
->size
== 0) {
1222 image
->bo
->size
= size
;
1223 } else if (size
> image
->bo
->size
) {
1224 brw_bo_unreference(image
->bo
);
1229 if (f
->nplanes
== 1) {
1230 image
->offset
= image
->offsets
[0];
1231 intel_image_warn_if_unaligned(image
, __func__
);
1238 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1239 int width
, int height
, int fourcc
,
1240 int *fds
, int num_fds
, int *strides
, int *offsets
,
1241 void *loaderPrivate
)
1243 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1244 DRM_FORMAT_MOD_INVALID
,
1245 fds
, num_fds
, strides
, offsets
,
1250 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1251 int width
, int height
,
1252 int fourcc
, uint64_t modifier
,
1253 int *fds
, int num_fds
,
1254 int *strides
, int *offsets
,
1255 enum __DRIYUVColorSpace yuv_color_space
,
1256 enum __DRISampleRange sample_range
,
1257 enum __DRIChromaSiting horizontal_siting
,
1258 enum __DRIChromaSiting vertical_siting
,
1260 void *loaderPrivate
)
1263 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1266 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1270 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1272 fds
, num_fds
, strides
, offsets
,
1276 * Invalid parameters and any inconsistencies between are assumed to be
1277 * checked by the caller. Therefore besides unsupported formats one can fail
1278 * only in allocation.
1281 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1285 image
->yuv_color_space
= yuv_color_space
;
1286 image
->sample_range
= sample_range
;
1287 image
->horizontal_siting
= horizontal_siting
;
1288 image
->vertical_siting
= vertical_siting
;
1289 image
->imported_dmabuf
= true;
1291 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1296 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1297 int width
, int height
, int fourcc
,
1298 int *fds
, int num_fds
,
1299 int *strides
, int *offsets
,
1300 enum __DRIYUVColorSpace yuv_color_space
,
1301 enum __DRISampleRange sample_range
,
1302 enum __DRIChromaSiting horizontal_siting
,
1303 enum __DRIChromaSiting vertical_siting
,
1305 void *loaderPrivate
)
1307 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1308 fourcc
, DRM_FORMAT_MOD_INVALID
,
1309 fds
, num_fds
, strides
, offsets
,
1319 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1320 const struct intel_image_format
*fmt
)
1322 /* Currently, all formats with an intel_image_format are available on all
1323 * platforms so there's really nothing to check there.
1327 if (fmt
->nplanes
== 1) {
1328 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1329 /* The images we will create are actually based on the RGBA non-sRGB
1330 * version of the format.
1332 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1333 format
= _mesa_get_srgb_format_linear(format
);
1334 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1335 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1343 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1344 int *formats
, int *count
)
1346 struct intel_screen
*screen
= _screen
->driverPrivate
;
1347 int num_formats
= 0, i
;
1349 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1350 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1351 * in the Linux kernel. We don't want to accidentally advertise them
1352 * them through the EGL layer.
1354 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1355 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
||
1356 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SXRGB8888
)
1359 if (!intel_image_format_is_supported(&screen
->devinfo
,
1360 &intel_image_formats
[i
]))
1367 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1368 if (num_formats
>= max
)
1372 *count
= num_formats
;
1377 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1378 uint64_t *modifiers
,
1379 unsigned int *external_only
,
1382 struct intel_screen
*screen
= _screen
->driverPrivate
;
1383 const struct intel_image_format
*f
;
1384 int num_mods
= 0, i
;
1386 f
= intel_image_format_lookup(fourcc
);
1390 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1393 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1394 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1395 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1402 modifiers
[num_mods
- 1] = modifier
;
1403 if (num_mods
>= max
)
1407 if (external_only
!= NULL
) {
1408 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1409 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1410 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1411 f
->components
== __DRI_IMAGE_COMPONENTS_AYUV
||
1412 f
->components
== __DRI_IMAGE_COMPONENTS_XYUV
||
1413 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1414 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1415 external_only
[i
] = GL_TRUE
;
1418 external_only
[i
] = GL_FALSE
;
1428 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1430 int width
, height
, offset
, stride
, size
, dri_format
;
1436 width
= parent
->width
;
1437 height
= parent
->height
;
1439 const struct intel_image_format
*f
= parent
->planar_format
;
1441 if (f
&& plane
< f
->nplanes
) {
1442 /* Use the planar format definition. */
1443 width
>>= f
->planes
[plane
].width_shift
;
1444 height
>>= f
->planes
[plane
].height_shift
;
1445 dri_format
= f
->planes
[plane
].dri_format
;
1446 int index
= f
->planes
[plane
].buffer_index
;
1447 offset
= parent
->offsets
[index
];
1448 stride
= parent
->strides
[index
];
1449 size
= height
* stride
;
1450 } else if (plane
== 0) {
1451 /* The only plane of a non-planar image: copy the parent definition
1453 dri_format
= parent
->dri_format
;
1454 offset
= parent
->offset
;
1455 stride
= parent
->pitch
;
1456 size
= height
* stride
;
1457 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1458 isl_drm_modifier_has_aux(parent
->modifier
)) {
1459 /* Auxiliary plane */
1460 dri_format
= parent
->dri_format
;
1461 offset
= parent
->aux_offset
;
1462 stride
= parent
->aux_pitch
;
1463 size
= parent
->aux_size
;
1468 if (offset
+ size
> parent
->bo
->size
) {
1469 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1473 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1477 image
->bo
= parent
->bo
;
1478 brw_bo_reference(parent
->bo
);
1479 image
->modifier
= parent
->modifier
;
1481 image
->width
= width
;
1482 image
->height
= height
;
1483 image
->pitch
= stride
;
1484 image
->offset
= offset
;
1486 intel_image_warn_if_unaligned(image
, __func__
);
1491 static const __DRIimageExtension intelImageExtension
= {
1492 .base
= { __DRI_IMAGE
, 16 },
1494 .createImageFromName
= intel_create_image_from_name
,
1495 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1496 .destroyImage
= intel_destroy_image
,
1497 .createImage
= intel_create_image
,
1498 .queryImage
= intel_query_image
,
1499 .dupImage
= intel_dup_image
,
1500 .validateUsage
= intel_validate_usage
,
1501 .createImageFromNames
= intel_create_image_from_names
,
1502 .fromPlanar
= intel_from_planar
,
1503 .createImageFromTexture
= intel_create_image_from_texture
,
1504 .createImageFromFds
= intel_create_image_from_fds
,
1505 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1507 .getCapabilities
= NULL
,
1508 .mapImage
= intel_map_image
,
1509 .unmapImage
= intel_unmap_image
,
1510 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1511 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1512 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1513 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1514 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1518 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1519 int param
, unsigned int *value
)
1521 const struct intel_screen
*const screen
=
1522 (struct intel_screen
*) dri_screen
->driverPrivate
;
1525 case __DRI2_RENDERER_VENDOR_ID
:
1528 case __DRI2_RENDERER_DEVICE_ID
:
1529 value
[0] = screen
->deviceID
;
1531 case __DRI2_RENDERER_ACCELERATED
:
1534 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1535 /* Once a batch uses more than 75% of the maximum mappable size, we
1536 * assume that there's some fragmentation, and we start doing extra
1537 * flushing, etc. That's the big cliff apps will care about.
1539 const unsigned gpu_mappable_megabytes
=
1540 screen
->aperture_threshold
/ (1024 * 1024);
1542 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1543 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1545 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1548 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1549 * (uint64_t) system_page_size
;
1551 const unsigned system_memory_megabytes
=
1552 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1554 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1557 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1560 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1563 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1565 if (brw_hw_context_set_priority(screen
->bufmgr
,
1566 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1567 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1568 if (brw_hw_context_set_priority(screen
->bufmgr
,
1569 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1570 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1571 /* reset to default last, just in case */
1572 if (brw_hw_context_set_priority(screen
->bufmgr
,
1573 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1574 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1576 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1580 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1587 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1588 int param
, const char **value
)
1590 const struct intel_screen
*screen
=
1591 (struct intel_screen
*) dri_screen
->driverPrivate
;
1594 case __DRI2_RENDERER_VENDOR_ID
:
1595 value
[0] = brw_vendor_string
;
1597 case __DRI2_RENDERER_DEVICE_ID
:
1598 value
[0] = brw_get_renderer_string(screen
);
1608 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1609 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1611 const struct intel_screen
*const screen
=
1612 (struct intel_screen
*) dri_screen
->driverPrivate
;
1614 if (!screen
->disk_cache
)
1617 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1620 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1621 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1623 .queryInteger
= brw_query_renderer_integer
,
1624 .queryString
= brw_query_renderer_string
1627 static const __DRIrobustnessExtension dri2Robustness
= {
1628 .base
= { __DRI2_ROBUSTNESS
, 1 }
1631 static const __DRI2blobExtension intelBlobExtension
= {
1632 .base
= { __DRI2_BLOB
, 1 },
1633 .set_cache_funcs
= brw_set_cache_funcs
1636 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1637 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1640 static const __DRIextension
*screenExtensions
[] = {
1641 &intelTexBufferExtension
.base
,
1642 &intelFenceExtension
.base
,
1643 &intelFlushExtension
.base
,
1644 &intelImageExtension
.base
,
1645 &intelRendererQueryExtension
.base
,
1646 &intelMutableRenderBufferExtension
.base
,
1647 &dri2ConfigQueryExtension
.base
,
1648 &dri2NoErrorExtension
.base
,
1649 &intelBlobExtension
.base
,
1653 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1654 &intelTexBufferExtension
.base
,
1655 &intelFenceExtension
.base
,
1656 &intelFlushExtension
.base
,
1657 &intelImageExtension
.base
,
1658 &intelRendererQueryExtension
.base
,
1659 &intelMutableRenderBufferExtension
.base
,
1660 &dri2ConfigQueryExtension
.base
,
1661 &dri2Robustness
.base
,
1662 &dri2NoErrorExtension
.base
,
1663 &intelBlobExtension
.base
,
1668 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1671 struct drm_i915_getparam gp
;
1673 memset(&gp
, 0, sizeof(gp
));
1677 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1680 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1687 intel_get_boolean(struct intel_screen
*screen
, int param
)
1690 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1694 intel_get_integer(struct intel_screen
*screen
, int param
)
1698 if (intel_get_param(screen
, param
, &value
) == 0)
1705 intelDestroyScreen(__DRIscreen
* sPriv
)
1707 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1709 brw_bufmgr_unref(screen
->bufmgr
);
1710 driDestroyOptionInfo(&screen
->optionCache
);
1712 disk_cache_destroy(screen
->disk_cache
);
1714 ralloc_free(screen
);
1715 sPriv
->driverPrivate
= NULL
;
1720 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1722 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1723 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1724 * this does not allocate GPU memory.
1727 intelCreateBuffer(__DRIscreen
*dri_screen
,
1728 __DRIdrawable
* driDrawPriv
,
1729 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1731 struct intel_renderbuffer
*rb
;
1732 struct intel_screen
*screen
= (struct intel_screen
*)
1733 dri_screen
->driverPrivate
;
1734 mesa_format rgbFormat
;
1735 unsigned num_samples
=
1736 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1741 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1745 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1747 if (screen
->winsys_msaa_samples_override
!= -1) {
1748 num_samples
= screen
->winsys_msaa_samples_override
;
1749 fb
->Visual
.samples
= num_samples
;
1752 if (mesaVis
->redBits
== 16 && mesaVis
->alphaBits
> 0 && mesaVis
->floatMode
) {
1753 rgbFormat
= MESA_FORMAT_RGBA_FLOAT16
;
1754 } else if (mesaVis
->redBits
== 16 && mesaVis
->floatMode
) {
1755 rgbFormat
= MESA_FORMAT_RGBX_FLOAT16
;
1756 } else if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1757 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1758 : MESA_FORMAT_R10G10B10A2_UNORM
;
1759 } else if (mesaVis
->redBits
== 10) {
1760 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1761 : MESA_FORMAT_R10G10B10X2_UNORM
;
1762 } else if (mesaVis
->redBits
== 5) {
1763 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1764 : MESA_FORMAT_B5G6R5_UNORM
;
1765 } else if (mesaVis
->alphaBits
== 0) {
1766 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1767 : MESA_FORMAT_B8G8R8X8_SRGB
;
1768 fb
->Visual
.sRGBCapable
= true;
1769 } else if (mesaVis
->sRGBCapable
) {
1770 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1771 : MESA_FORMAT_B8G8R8A8_SRGB
;
1772 fb
->Visual
.sRGBCapable
= true;
1774 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1775 : MESA_FORMAT_B8G8R8A8_SRGB
;
1776 fb
->Visual
.sRGBCapable
= true;
1779 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1780 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1782 /* setup the hardware-based renderbuffers */
1783 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1784 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1785 rb
->need_srgb
= srgb_cap_set
;
1787 if (mesaVis
->doubleBufferMode
) {
1788 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1789 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1790 rb
->need_srgb
= srgb_cap_set
;
1794 * Assert here that the gl_config has an expected depth/stencil bit
1795 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1796 * which constructs the advertised configs.)
1798 if (mesaVis
->depthBits
== 24) {
1799 assert(mesaVis
->stencilBits
== 8);
1801 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1802 rb
= intel_create_private_renderbuffer(screen
,
1803 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1805 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1806 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1808 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1811 * Use combined depth/stencil. Note that the renderbuffer is
1812 * attached to two attachment points.
1814 rb
= intel_create_private_renderbuffer(screen
,
1815 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1817 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1818 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1821 else if (mesaVis
->depthBits
== 16) {
1822 assert(mesaVis
->stencilBits
== 0);
1823 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1825 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1828 assert(mesaVis
->depthBits
== 0);
1829 assert(mesaVis
->stencilBits
== 0);
1832 /* now add any/all software-based renderbuffers we may need */
1833 _swrast_add_soft_renderbuffers(fb
,
1834 false, /* never sw color */
1835 false, /* never sw depth */
1836 false, /* never sw stencil */
1837 mesaVis
->accumRedBits
> 0,
1838 false, /* never sw alpha */
1839 false /* never sw aux */ );
1840 driDrawPriv
->driverPrivate
= fb
;
1846 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1848 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1850 _mesa_reference_framebuffer(&fb
, NULL
);
1854 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1856 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1857 * gen10, PCI-id is enough to figure it out.
1859 assert(screen
->devinfo
.gen
>= 10);
1863 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1867 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1871 screen
->devinfo
.timestamp_frequency
= freq
;
1875 intel_detect_sseu(struct intel_screen
*screen
)
1877 assert(screen
->devinfo
.gen
>= 8);
1880 screen
->subslice_total
= -1;
1881 screen
->eu_total
= -1;
1883 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1884 &screen
->subslice_total
);
1885 if (ret
< 0 && ret
!= -EINVAL
)
1888 ret
= intel_get_param(screen
,
1889 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1890 if (ret
< 0 && ret
!= -EINVAL
)
1893 /* Without this information, we cannot get the right Braswell brandstrings,
1894 * and we have to use conservative numbers for GPGPU on many platforms, but
1895 * otherwise, things will just work.
1897 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1899 "Kernel 4.1 required to properly query GPU properties.\n");
1904 screen
->subslice_total
= -1;
1905 screen
->eu_total
= -1;
1906 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1910 intel_init_bufmgr(struct intel_screen
*screen
)
1912 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1914 if (getenv("INTEL_NO_HW") != NULL
)
1915 screen
->no_hw
= true;
1917 bool bo_reuse
= false;
1918 int bo_reuse_mode
= driQueryOptioni(&screen
->optionCache
, "bo_reuse");
1919 switch (bo_reuse_mode
) {
1920 case DRI_CONF_BO_REUSE_DISABLED
:
1922 case DRI_CONF_BO_REUSE_ALL
:
1927 screen
->bufmgr
= brw_bufmgr_get_for_fd(&screen
->devinfo
, dri_screen
->fd
, bo_reuse
);
1928 if (screen
->bufmgr
== NULL
) {
1929 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1930 __func__
, __LINE__
);
1933 screen
->fd
= brw_bufmgr_get_fd(screen
->bufmgr
);
1935 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1936 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1944 intel_detect_swizzling(struct intel_screen
*screen
)
1946 /* Broadwell PRM says:
1948 * "Before Gen8, there was a historical configuration control field to
1949 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1950 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1951 * DISP_ARB_CTL[14:13].
1953 * For Gen8 and subsequent generations, the swizzle fields are all
1954 * reserved, and the CPU's memory controller performs all address
1955 * swizzling modifications."
1957 if (screen
->devinfo
.gen
>= 8)
1960 uint32_t tiling
= I915_TILING_X
;
1961 uint32_t swizzle_mode
= 0;
1962 struct brw_bo
*buffer
=
1963 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1964 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1968 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1969 brw_bo_unreference(buffer
);
1971 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1975 intel_detect_timestamp(struct intel_screen
*screen
)
1977 uint64_t dummy
= 0, last
= 0;
1978 int upper
, lower
, loops
;
1980 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1981 * TIMESTAMP register being shifted and the low 32bits always zero.
1983 * More recent kernels offer an interface to read the full 36bits
1986 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1989 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1990 * upper 32bits for a rapidly changing timestamp.
1992 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1996 for (loops
= 0; loops
< 10; loops
++) {
1997 /* The TIMESTAMP should change every 80ns, so several round trips
1998 * through the kernel should be enough to advance it.
2000 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
2003 upper
+= (dummy
>> 32) != (last
>> 32);
2004 if (upper
> 1) /* beware 32bit counter overflow */
2005 return 2; /* upper dword holds the low 32bits of the timestamp */
2007 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
2009 return 1; /* timestamp is unshifted */
2014 /* No advancement? No timestamp! */
2019 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2021 * Some combinations of hardware and kernel versions allow this feature,
2022 * while others don't. Instead of trying to enumerate every case, just
2023 * try and write a register and see if works.
2026 intel_detect_pipelined_register(struct intel_screen
*screen
,
2027 int reg
, uint32_t expected_value
, bool reset
)
2032 struct brw_bo
*results
, *bo
;
2034 uint32_t offset
= 0;
2036 bool success
= false;
2038 /* Create a zero'ed temporary buffer for reading our results */
2039 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2040 if (results
== NULL
)
2043 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2047 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2053 /* Write the register. */
2054 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2056 *batch
++ = expected_value
;
2058 /* Save the register's value back to the buffer. */
2059 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2061 struct drm_i915_gem_relocation_entry reloc
= {
2062 .offset
= (char *) batch
- (char *) map
,
2063 .delta
= offset
* sizeof(uint32_t),
2064 .target_handle
= results
->gem_handle
,
2065 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2066 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2068 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2070 /* And afterwards clear the register */
2072 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2077 *batch
++ = MI_BATCH_BUFFER_END
;
2079 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2081 .handle
= results
->gem_handle
,
2084 .handle
= bo
->gem_handle
,
2085 .relocation_count
= 1,
2086 .relocs_ptr
= (uintptr_t) &reloc
,
2090 struct drm_i915_gem_execbuffer2 execbuf
= {
2091 .buffers_ptr
= (uintptr_t) exec_objects
,
2093 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2094 .flags
= I915_EXEC_RENDER
,
2097 /* Don't bother with error checking - if the execbuf fails, the
2098 * value won't be written and we'll just report that there's no access.
2100 drmIoctl(screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2102 /* Check whether the value got written. */
2103 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2105 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2106 brw_bo_unmap(results
);
2110 brw_bo_unreference(bo
);
2112 brw_bo_unreference(results
);
2118 intel_detect_pipelined_so(struct intel_screen
*screen
)
2120 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2122 /* Supposedly, Broadwell just works. */
2123 if (devinfo
->gen
>= 8)
2126 if (devinfo
->gen
<= 6)
2129 /* See the big explanation about command parser versions below */
2130 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2133 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2134 * statistics registers), and we already reset it to zero before using it.
2136 return intel_detect_pipelined_register(screen
,
2137 GEN7_SO_WRITE_OFFSET(0),
2143 * Return array of MSAA modes supported by the hardware. The array is
2144 * zero-terminated and sorted in decreasing order.
2147 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2149 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2150 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2151 static const int gen7_modes
[] = {8, 4, 0, -1};
2152 static const int gen6_modes
[] = {4, 0, -1};
2153 static const int gen4_modes
[] = {0, -1};
2155 if (screen
->devinfo
.gen
>= 9) {
2157 } else if (screen
->devinfo
.gen
>= 8) {
2159 } else if (screen
->devinfo
.gen
>= 7) {
2161 } else if (screen
->devinfo
.gen
== 6) {
2169 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2171 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2172 dri_screen
->dri2
.loader
->getCapability
)
2173 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2175 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2176 dri_screen
->image
.loader
->getCapability
)
2177 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2183 intel_allowed_format(__DRIscreen
*dri_screen
, mesa_format format
)
2185 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2187 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2188 bool allow_rgba_ordering
= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
);
2189 if (!allow_rgba_ordering
&&
2190 (format
== MESA_FORMAT_R8G8B8A8_UNORM
||
2191 format
== MESA_FORMAT_R8G8B8X8_UNORM
||
2192 format
== MESA_FORMAT_R8G8B8A8_SRGB
))
2195 /* Shall we expose 10 bpc formats? */
2196 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2197 "allow_rgb10_configs");
2198 if (!allow_rgb10_configs
&&
2199 (format
== MESA_FORMAT_B10G10R10A2_UNORM
||
2200 format
== MESA_FORMAT_B10G10R10X2_UNORM
))
2203 /* Shall we expose 565 formats? */
2204 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2205 "allow_rgb565_configs");
2206 if (!allow_rgb565_configs
&& format
== MESA_FORMAT_B5G6R5_UNORM
)
2209 /* Shall we expose fp16 formats? */
2210 bool allow_fp16_configs
= driQueryOptionb(&screen
->optionCache
,
2211 "allow_fp16_configs");
2212 allow_fp16_configs
&= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_FP16
);
2213 if (!allow_fp16_configs
&&
2214 (format
== MESA_FORMAT_RGBA_FLOAT16
||
2215 format
== MESA_FORMAT_RGBX_FLOAT16
))
2221 static __DRIconfig
**
2222 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2224 static const mesa_format formats
[] = {
2225 MESA_FORMAT_B5G6R5_UNORM
,
2226 MESA_FORMAT_B8G8R8A8_UNORM
,
2227 MESA_FORMAT_B8G8R8X8_UNORM
,
2229 MESA_FORMAT_B8G8R8A8_SRGB
,
2230 MESA_FORMAT_B8G8R8X8_SRGB
,
2232 /* For 10 bpc, 30 bit depth framebuffers. */
2233 MESA_FORMAT_B10G10R10A2_UNORM
,
2234 MESA_FORMAT_B10G10R10X2_UNORM
,
2236 MESA_FORMAT_RGBA_FLOAT16
,
2237 MESA_FORMAT_RGBX_FLOAT16
,
2239 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2240 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2241 * server may disagree on which format the GLXFBConfig represents,
2242 * resulting in swapped color channels.
2244 * The problem, as of 2017-05-30:
2245 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2246 * order and chooses the first __DRIconfig with the expected channel
2247 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2248 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2250 * EGL does not suffer from this problem. It correctly compares the
2251 * channel masks when matching EGLConfig to __DRIconfig.
2254 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2255 MESA_FORMAT_R8G8B8A8_UNORM
,
2257 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2258 MESA_FORMAT_R8G8B8X8_UNORM
,
2260 MESA_FORMAT_R8G8B8A8_SRGB
,
2263 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2264 static const GLenum back_buffer_modes
[] = {
2265 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2268 static const uint8_t singlesample_samples
[1] = {0};
2270 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2271 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2272 uint8_t depth_bits
[4], stencil_bits
[4];
2273 __DRIconfig
**configs
= NULL
;
2275 unsigned num_formats
= ARRAY_SIZE(formats
);
2277 /* Generate singlesample configs, each without accumulation buffer
2278 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2280 for (unsigned i
= 0; i
< num_formats
; i
++) {
2281 __DRIconfig
**new_configs
;
2282 int num_depth_stencil_bits
= 1;
2284 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2287 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2288 * buffer that has a different number of bits per pixel than the color
2289 * buffer, gen >= 6 supports this.
2292 stencil_bits
[0] = 0;
2294 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2295 if (devinfo
->gen
>= 8) {
2296 depth_bits
[num_depth_stencil_bits
] = 16;
2297 stencil_bits
[num_depth_stencil_bits
] = 0;
2298 num_depth_stencil_bits
++;
2300 if (devinfo
->gen
>= 6) {
2301 depth_bits
[num_depth_stencil_bits
] = 24;
2302 stencil_bits
[num_depth_stencil_bits
] = 8;
2303 num_depth_stencil_bits
++;
2306 depth_bits
[num_depth_stencil_bits
] = 24;
2307 stencil_bits
[num_depth_stencil_bits
] = 8;
2308 num_depth_stencil_bits
++;
2311 new_configs
= driCreateConfigs(formats
[i
],
2314 num_depth_stencil_bits
,
2315 back_buffer_modes
, 2,
2316 singlesample_samples
, 1,
2318 /*mutable_render_buffer*/ true);
2319 configs
= driConcatConfigs(configs
, new_configs
);
2322 /* Generate the minimum possible set of configs that include an
2323 * accumulation buffer.
2325 for (unsigned i
= 0; i
< num_formats
; i
++) {
2326 __DRIconfig
**new_configs
;
2328 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2331 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2332 if (devinfo
->gen
>= 8) {
2334 stencil_bits
[0] = 0;
2335 } else if (devinfo
->gen
>= 6) {
2337 stencil_bits
[0] = 8;
2340 stencil_bits
[0] = 0;
2344 stencil_bits
[0] = 8;
2347 new_configs
= driCreateConfigs(formats
[i
],
2348 depth_bits
, stencil_bits
, 1,
2349 back_buffer_modes
, 1,
2350 singlesample_samples
, 1,
2351 true, false, false);
2352 configs
= driConcatConfigs(configs
, new_configs
);
2355 /* Generate multisample configs.
2357 * This loop breaks early, and hence is a no-op, on gen < 6.
2359 * Multisample configs must follow the singlesample configs in order to
2360 * work around an X server bug present in 1.12. The X server chooses to
2361 * associate the first listed RGBA888-Z24S8 config, regardless of its
2362 * sample count, with the 32-bit depth visual used for compositing.
2364 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2365 * supported. Singlebuffer configs are not supported because no one wants
2368 for (unsigned i
= 0; i
< num_formats
; i
++) {
2369 if (devinfo
->gen
< 6)
2372 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2375 __DRIconfig
**new_configs
;
2376 const int num_depth_stencil_bits
= 2;
2377 int num_msaa_modes
= 0;
2378 const uint8_t *multisample_samples
= NULL
;
2381 stencil_bits
[0] = 0;
2383 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
&& devinfo
->gen
>= 8) {
2385 stencil_bits
[1] = 0;
2388 stencil_bits
[1] = 8;
2391 if (devinfo
->gen
>= 9) {
2392 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2393 multisample_samples
= multisample_samples_gen9
;
2394 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2395 } else if (devinfo
->gen
== 8) {
2396 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2397 multisample_samples
= multisample_samples_gen8
;
2398 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2399 } else if (devinfo
->gen
== 7) {
2400 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2401 multisample_samples
= multisample_samples_gen7
;
2402 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2403 } else if (devinfo
->gen
== 6) {
2404 static const uint8_t multisample_samples_gen6
[] = {4};
2405 multisample_samples
= multisample_samples_gen6
;
2406 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2409 new_configs
= driCreateConfigs(formats
[i
],
2412 num_depth_stencil_bits
,
2413 back_buffer_modes
, 1,
2414 multisample_samples
,
2416 false, false, false);
2417 configs
= driConcatConfigs(configs
, new_configs
);
2420 if (configs
== NULL
) {
2421 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2430 set_max_gl_versions(struct intel_screen
*screen
)
2432 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2433 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2435 switch (screen
->devinfo
.gen
) {
2440 dri_screen
->max_gl_core_version
= 46;
2441 dri_screen
->max_gl_compat_version
= 30;
2442 dri_screen
->max_gl_es1_version
= 11;
2443 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2446 dri_screen
->max_gl_core_version
= 33;
2447 if (can_do_pipelined_register_writes(screen
)) {
2448 dri_screen
->max_gl_core_version
= 42;
2449 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2450 dri_screen
->max_gl_core_version
= 43;
2451 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2452 dri_screen
->max_gl_core_version
= 45;
2454 dri_screen
->max_gl_compat_version
= 30;
2455 dri_screen
->max_gl_es1_version
= 11;
2456 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2459 dri_screen
->max_gl_core_version
= 33;
2460 dri_screen
->max_gl_compat_version
= 30;
2461 dri_screen
->max_gl_es1_version
= 11;
2462 dri_screen
->max_gl_es2_version
= 30;
2466 dri_screen
->max_gl_core_version
= 0;
2467 dri_screen
->max_gl_compat_version
= 21;
2468 dri_screen
->max_gl_es1_version
= 11;
2469 dri_screen
->max_gl_es2_version
= 20;
2472 unreachable("unrecognized intel_screen::gen");
2477 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2479 struct brw_context
*brw
= (struct brw_context
*)data
;
2482 va_start(args
, fmt
);
2484 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2485 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2486 MESA_DEBUG_TYPE_OTHER
,
2487 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2492 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2494 struct brw_context
*brw
= (struct brw_context
*)data
;
2497 va_start(args
, fmt
);
2499 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2501 va_copy(args_copy
, args
);
2502 vfprintf(stderr
, fmt
, args_copy
);
2506 if (brw
->perf_debug
) {
2508 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2509 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2510 MESA_DEBUG_TYPE_PERFORMANCE
,
2511 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2517 * This is the driver specific part of the createNewScreen entry point.
2518 * Called when using DRI2.
2520 * \return the struct gl_config supported by this driver
2523 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2525 struct intel_screen
*screen
;
2527 if (dri_screen
->image
.loader
) {
2528 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2529 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2531 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2532 "support required\n");
2536 /* Allocate the private area */
2537 screen
= rzalloc(NULL
, struct intel_screen
);
2539 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2542 /* parse information in __driConfigOptions */
2543 driOptionCache options
;
2544 memset(&options
, 0, sizeof(options
));
2546 driParseOptionInfo(&options
, brw_config_options
.xml
);
2547 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2548 "i965", NULL
, NULL
, 0, NULL
, 0);
2549 driDestroyOptionCache(&options
);
2551 screen
->driScrnPriv
= dri_screen
;
2552 dri_screen
->driverPrivate
= (void *) screen
;
2554 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2557 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2558 screen
->deviceID
= devinfo
->chipset_id
;
2559 screen
->no_hw
= devinfo
->no_hw
;
2561 if (devinfo
->gen
>= 12) {
2562 fprintf(stderr
, "gen12 and newer are not supported on i965\n");
2566 if (!intel_init_bufmgr(screen
))
2569 brw_process_intel_debug_variable();
2571 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2573 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2574 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2577 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2578 /* Theorectically unlimited! At least for individual objects...
2580 * Currently the entire (global) address space for all GTT maps is
2581 * limited to 64bits. That is all objects on the system that are
2582 * setup for GTT mmapping must fit within 64bits. An attempt to use
2583 * one that exceeds the limit with fail in brw_bo_map_gtt().
2585 * Long before we hit that limit, we will be practically limited by
2586 * that any single object must fit in physical memory (RAM). The upper
2587 * limit on the CPU's address space is currently 48bits (Skylake), of
2588 * which only 39bits can be physical memory. (The GPU itself also has
2589 * a 48bit addressable virtual space.) We can fit over 32 million
2590 * objects of the current maximum allocable size before running out
2593 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2595 /* Estimate the size of the mappable aperture into the GTT. There's an
2596 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2597 * It turns out it's basically always 256MB, though some ancient hardware
2600 uint32_t gtt_size
= 256 * 1024 * 1024;
2602 /* We don't want to map two objects such that a memcpy between them would
2603 * just fault one mapping in and then the other over and over forever. So
2604 * we would need to divide the GTT size by 2. Additionally, some GTT is
2605 * taken up by things like the framebuffer and the ringbuffer and such, so
2606 * be more conservative.
2608 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2611 screen
->aperture_threshold
= devinfo
->aperture_bytes
* 3 / 4;
2613 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2614 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2616 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2617 screen
->hw_has_swizzling
);
2619 if (devinfo
->gen
>= 10)
2620 intel_cs_timestamp_frequency(screen
);
2622 /* GENs prior to 8 do not support EU/Subslice info */
2623 if (devinfo
->gen
>= 8) {
2624 intel_detect_sseu(screen
);
2625 } else if (devinfo
->gen
== 7) {
2626 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2629 /* Gen7-7.5 kernel requirements / command parser saga:
2632 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2634 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2635 * all batches secure, allowing them to use any feature with no checking.
2636 * This is effectively equivalent to a command parser version of
2637 * \infinity - everything is possible.
2639 * The command parser does not exist, and querying the version will
2643 * The kernel enables the command parser by default, for systems with
2644 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2645 * hardware checker is still enabled, so Haswell and Baytrail cannot
2648 * Ivybridge goes from "everything is possible" to "only what the
2649 * command parser allows" (if the user boots with i915.cmd_parser=0,
2650 * then everything is possible again). We can only safely use features
2651 * allowed by the supported command parser version.
2653 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2654 * implemented by the kernel, even if it's turned off. So, checking
2655 * for version > 0 does not mean that you can write registers. We have
2656 * to try it and see. The version does, however, indicate the age of
2659 * Instead of matching the hardware checker's behavior of converting
2660 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2661 * -EINVAL, making it dangerous to try and use privileged features.
2663 * Effective command parser versions:
2664 * - Haswell: 0 (reporting 1, writes don't work)
2665 * - Baytrail: 0 (reporting 1, writes don't work)
2666 * - Ivybridge: 1 (enabled) or infinite (disabled)
2669 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2670 * effectively version 1 (enabled) or infinite (disabled).
2672 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2673 * Command parser v2 supports predicate writes.
2675 * - Haswell: 0 (reporting 1, writes don't work)
2676 * - Baytrail: 2 (enabled) or infinite (disabled)
2677 * - Ivybridge: 2 (enabled) or infinite (disabled)
2679 * So version >= 2 is enough to know that Ivybridge and Baytrail
2680 * will work. Haswell still can't do anything.
2682 * - v4.0: Version 3 happened. Largely not relevant.
2684 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2685 * L3 config registers are properly saved and restored as part
2686 * of the hardware context. We can approximately detect this point
2687 * in time by checking if I915_PARAM_REVISION is recognized - it
2688 * landed in a later commit, but in the same release cycle.
2690 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2691 * Command parser finally gains secure batch promotion. On Haswell,
2692 * the hardware checker gets disabled, which finally allows it to do
2693 * privileged commands.
2695 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2696 * - Haswell: 3 (enabled) or 0 (disabled)
2697 * - Baytrail: 3 (enabled) or infinite (disabled)
2698 * - Ivybridge: 3 (enabled) or infinite (disabled)
2700 * Unfortunately, detecting this point in time is tricky, because
2701 * no version bump happened when this important change occurred.
2702 * On Haswell, if we can write any register, then the kernel is at
2703 * least this new, and we can start trusting the version number.
2705 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2706 * Command parser reaches version 4, allowing access to Haswell
2707 * atomic scratch and chicken3 registers. If version >= 4, we know
2708 * the kernel is new enough to support privileged features on all
2709 * hardware. However, the user might have disabled it...and the
2710 * kernel will still report version 4. So we still have to guess
2713 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2714 * Command parser v5 whitelists indirect compute shader dispatch
2715 * registers, needed for OpenGL 4.3 and later.
2718 * Command parser v7 lets us use MI_MATH on Haswell.
2720 * Additionally, the kernel begins reporting version 0 when
2721 * the command parser is disabled, allowing us to skip the
2722 * guess-and-check step on Haswell. Unfortunately, this also
2723 * means that we can no longer use it as an indicator of the
2724 * age of the kernel.
2726 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2727 &screen
->cmd_parser_version
) < 0) {
2728 /* Command parser does not exist - getparam is unrecognized */
2729 screen
->cmd_parser_version
= 0;
2732 /* Kernel 4.13 retuired for exec object capture */
2733 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2734 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2737 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2738 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2741 if (!intel_detect_pipelined_so(screen
)) {
2742 /* We can't do anything, so the effective version is 0. */
2743 screen
->cmd_parser_version
= 0;
2745 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2748 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2749 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2751 /* Haswell requires command parser version 4 in order to have L3
2752 * atomic scratch1 and chicken3 bits
2754 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2755 screen
->kernel_features
|=
2756 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2759 /* Haswell requires command parser version 6 in order to write to the
2760 * MI_MATH GPR registers, and version 7 in order to use
2761 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2763 if (devinfo
->gen
>= 8 ||
2764 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2765 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2768 /* Gen7 needs at least command parser version 5 to support compute */
2769 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2770 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2772 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2773 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2775 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2777 screen
->winsys_msaa_samples_override
=
2778 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2779 printf("Forcing winsys sample count to %d\n",
2780 screen
->winsys_msaa_samples_override
);
2782 screen
->winsys_msaa_samples_override
= -1;
2785 set_max_gl_versions(screen
);
2787 /* Notification of GPU resets requires hardware contexts and a kernel new
2788 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2789 * supported, calling it with a context of 0 will either generate EPERM or
2790 * no error. If the ioctl is not supported, it always generate EINVAL.
2791 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2792 * extension to the loader.
2794 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2796 if (devinfo
->gen
>= 6) {
2797 struct drm_i915_reset_stats stats
;
2798 memset(&stats
, 0, sizeof(stats
));
2800 const int ret
= drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2802 screen
->has_context_reset_notification
=
2803 (ret
!= -1 || errno
!= EINVAL
);
2806 dri_screen
->extensions
= !screen
->has_context_reset_notification
2807 ? screenExtensions
: intelRobustScreenExtensions
;
2809 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2810 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2811 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2813 /* Changing the meaning of constant buffer pointers from a dynamic state
2814 * offset to an absolute address is only safe if the kernel isolates other
2815 * contexts from our changes.
2817 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2818 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2820 screen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].PositionAlwaysInvariant
= driQueryOptionb(&screen
->optionCache
, "vs_position_always_invariant");
2822 screen
->compiler
->supports_pull_constants
= true;
2823 screen
->compiler
->compact_params
= true;
2824 screen
->compiler
->lower_variable_group_size
= true;
2826 screen
->has_exec_fence
=
2827 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2829 intel_screen_init_surface_formats(screen
);
2831 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2832 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2834 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2835 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2836 fprintf(stderr
, " - User priority sorting enabled\n");
2837 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2838 fprintf(stderr
, " - Preemption enabled\n");
2842 brw_disk_cache_init(screen
);
2844 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2847 struct intel_buffer
{
2852 static __DRIbuffer
*
2853 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2854 unsigned attachment
, unsigned format
,
2855 int width
, int height
)
2857 struct intel_buffer
*intelBuffer
;
2858 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2860 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2861 attachment
== __DRI_BUFFER_BACK_LEFT
);
2863 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2864 if (intelBuffer
== NULL
)
2867 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2868 * supports Y tiled and compressed buffers, but there is no way to plumb that
2869 * through to here. */
2871 int cpp
= format
/ 8;
2872 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2873 "intelAllocateBuffer",
2878 I915_TILING_X
, &pitch
,
2881 if (intelBuffer
->bo
== NULL
) {
2886 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2888 intelBuffer
->base
.attachment
= attachment
;
2889 intelBuffer
->base
.cpp
= cpp
;
2890 intelBuffer
->base
.pitch
= pitch
;
2892 return &intelBuffer
->base
;
2896 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2898 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2900 brw_bo_unreference(intelBuffer
->bo
);
2904 static const struct __DriverAPIRec brw_driver_api
= {
2905 .InitScreen
= intelInitScreen2
,
2906 .DestroyScreen
= intelDestroyScreen
,
2907 .CreateContext
= brwCreateContext
,
2908 .DestroyContext
= intelDestroyContext
,
2909 .CreateBuffer
= intelCreateBuffer
,
2910 .DestroyBuffer
= intelDestroyBuffer
,
2911 .MakeCurrent
= intelMakeCurrent
,
2912 .UnbindContext
= intelUnbindContext
,
2913 .AllocateBuffer
= intelAllocateBuffer
,
2914 .ReleaseBuffer
= intelReleaseBuffer
2917 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2918 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2919 .vtable
= &brw_driver_api
,
2922 static const __DRIextension
*brw_driver_extensions
[] = {
2923 &driCoreExtension
.base
,
2924 &driImageDriverExtension
.base
,
2925 &driDRI2Extension
.base
,
2927 &brw_config_options
.base
,
2931 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2933 globalDriverAPI
= &brw_driver_api
;
2935 return brw_driver_extensions
;