2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_MISCELLANEOUS
93 DRI_CONF_GLSL_ZERO_INIT("false")
98 #include "intel_batchbuffer.h"
99 #include "intel_buffers.h"
100 #include "intel_bufmgr.h"
101 #include "intel_fbo.h"
102 #include "intel_mipmap_tree.h"
103 #include "intel_screen.h"
104 #include "intel_tex.h"
105 #include "intel_image.h"
107 #include "brw_context.h"
109 #include "i915_drm.h"
112 * For debugging purposes, this returns a time in seconds.
119 clock_gettime(CLOCK_MONOTONIC
, &tp
);
121 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
125 aub_dump_bmp(struct gl_context
*ctx
)
127 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
129 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
130 struct intel_renderbuffer
*irb
=
131 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
133 if (irb
&& irb
->mt
) {
134 enum aub_dump_bmp_format format
;
136 switch (irb
->Base
.Base
.Format
) {
137 case MESA_FORMAT_B8G8R8A8_UNORM
:
138 case MESA_FORMAT_B8G8R8X8_UNORM
:
139 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
145 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
148 irb
->Base
.Base
.Width
,
149 irb
->Base
.Base
.Height
,
157 static const __DRItexBufferExtension intelTexBufferExtension
= {
158 .base
= { __DRI_TEX_BUFFER
, 3 },
160 .setTexBuffer
= intelSetTexBuffer
,
161 .setTexBuffer2
= intelSetTexBuffer2
,
162 .releaseTexBuffer
= NULL
,
166 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
167 __DRIdrawable
*dPriv
,
169 enum __DRI2throttleReason reason
)
171 struct brw_context
*brw
= cPriv
->driverPrivate
;
176 struct gl_context
*ctx
= &brw
->ctx
;
178 FLUSH_VERTICES(ctx
, 0);
180 if (flags
& __DRI2_FLUSH_DRAWABLE
)
181 intel_resolve_for_dri2_flush(brw
, dPriv
);
183 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
184 brw
->need_swap_throttle
= true;
185 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
186 brw
->need_flush_throttle
= true;
188 intel_batchbuffer_flush(brw
);
190 if (INTEL_DEBUG
& DEBUG_AUB
) {
196 * Provides compatibility with loaders that only support the older (version
197 * 1-3) flush interface.
199 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
202 intel_dri2_flush(__DRIdrawable
*drawable
)
204 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
205 __DRI2_FLUSH_DRAWABLE
,
206 __DRI2_THROTTLE_SWAPBUFFER
);
209 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
210 .base
= { __DRI2_FLUSH
, 4 },
212 .flush
= intel_dri2_flush
,
213 .invalidate
= dri2InvalidateDrawable
,
214 .flush_with_flags
= intel_dri2_flush_with_flags
,
217 static struct intel_image_format intel_image_formats
[] = {
218 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
221 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
224 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
227 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
230 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
233 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
236 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
239 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
242 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
277 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
282 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
287 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
288 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
289 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
290 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
292 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
294 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
296 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
297 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
298 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
300 /* For YUYV buffers, we set up two overlapping DRI images and treat
301 * them as planar buffers in the compositors. Plane 0 is GR88 and
302 * samples YU or YV pairs and places Y into the R component, while
303 * plane 1 is ARGB and samples YUYV clusters and places pairs and
304 * places U into the G component and V into A. This lets the
305 * texture sampler interpolate the Y components correctly when
306 * sampling from plane 0, and interpolate U and V correctly when
307 * sampling from plane 1. */
308 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
309 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
310 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
314 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
316 uint32_t tiling
, swizzle
;
317 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
319 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
320 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
321 func
, image
->offset
);
325 static struct intel_image_format
*
326 intel_image_format_lookup(int fourcc
)
328 struct intel_image_format
*f
= NULL
;
330 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
331 if (intel_image_formats
[i
].fourcc
== fourcc
) {
332 f
= &intel_image_formats
[i
];
340 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
342 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
343 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
344 *fourcc
= intel_image_formats
[i
].fourcc
;
352 intel_allocate_image(int dri_format
, void *loaderPrivate
)
356 image
= calloc(1, sizeof *image
);
360 image
->dri_format
= dri_format
;
363 image
->format
= driImageFormatToGLFormat(dri_format
);
364 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
365 image
->format
== MESA_FORMAT_NONE
) {
370 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
371 image
->data
= loaderPrivate
;
377 * Sets up a DRIImage structure to point to a slice out of a miptree.
380 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
381 struct intel_mipmap_tree
*mt
, GLuint level
,
384 intel_miptree_make_shareable(brw
, mt
);
386 intel_miptree_check_level_layer(mt
, level
, zoffset
);
388 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
389 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
390 image
->pitch
= mt
->pitch
;
392 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
396 drm_intel_bo_unreference(image
->bo
);
398 drm_intel_bo_reference(mt
->bo
);
402 intel_create_image_from_name(__DRIscreen
*screen
,
403 int width
, int height
, int format
,
404 int name
, int pitch
, void *loaderPrivate
)
406 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
410 image
= intel_allocate_image(format
, loaderPrivate
);
414 if (image
->format
== MESA_FORMAT_NONE
)
417 cpp
= _mesa_get_format_bytes(image
->format
);
419 image
->width
= width
;
420 image
->height
= height
;
421 image
->pitch
= pitch
* cpp
;
422 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
433 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
434 int renderbuffer
, void *loaderPrivate
)
437 struct brw_context
*brw
= context
->driverPrivate
;
438 struct gl_context
*ctx
= &brw
->ctx
;
439 struct gl_renderbuffer
*rb
;
440 struct intel_renderbuffer
*irb
;
442 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
444 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
448 irb
= intel_renderbuffer(rb
);
449 intel_miptree_make_shareable(brw
, irb
->mt
);
450 image
= calloc(1, sizeof *image
);
454 image
->internal_format
= rb
->InternalFormat
;
455 image
->format
= rb
->Format
;
457 image
->data
= loaderPrivate
;
458 drm_intel_bo_unreference(image
->bo
);
459 image
->bo
= irb
->mt
->bo
;
460 drm_intel_bo_reference(irb
->mt
->bo
);
461 image
->width
= rb
->Width
;
462 image
->height
= rb
->Height
;
463 image
->pitch
= irb
->mt
->pitch
;
464 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
465 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
467 rb
->NeedsFinishRenderTexture
= true;
472 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
473 unsigned texture
, int zoffset
,
479 struct brw_context
*brw
= context
->driverPrivate
;
480 struct gl_texture_object
*obj
;
481 struct intel_texture_object
*iobj
;
484 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
485 if (!obj
|| obj
->Target
!= target
) {
486 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
490 if (target
== GL_TEXTURE_CUBE_MAP
)
493 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
494 iobj
= intel_texture_object(obj
);
495 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
496 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
500 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
501 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
505 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
506 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
509 image
= calloc(1, sizeof *image
);
511 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
515 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
516 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
517 image
->data
= loaderPrivate
;
518 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
519 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
520 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
521 if (image
->dri_format
== MESA_FORMAT_NONE
) {
522 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
527 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
532 intel_destroy_image(__DRIimage
*image
)
534 drm_intel_bo_unreference(image
->bo
);
539 intel_create_image(__DRIscreen
*screen
,
540 int width
, int height
, int format
,
545 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
550 tiling
= I915_TILING_X
;
551 if (use
& __DRI_IMAGE_USE_CURSOR
) {
552 if (width
!= 64 || height
!= 64)
554 tiling
= I915_TILING_NONE
;
557 if (use
& __DRI_IMAGE_USE_LINEAR
)
558 tiling
= I915_TILING_NONE
;
560 image
= intel_allocate_image(format
, loaderPrivate
);
564 cpp
= _mesa_get_format_bytes(image
->format
);
565 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
566 width
, height
, cpp
, &tiling
,
568 if (image
->bo
== NULL
) {
572 image
->width
= width
;
573 image
->height
= height
;
574 image
->pitch
= pitch
;
580 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
583 case __DRI_IMAGE_ATTRIB_STRIDE
:
584 *value
= image
->pitch
;
586 case __DRI_IMAGE_ATTRIB_HANDLE
:
587 *value
= image
->bo
->handle
;
589 case __DRI_IMAGE_ATTRIB_NAME
:
590 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
591 case __DRI_IMAGE_ATTRIB_FORMAT
:
592 *value
= image
->dri_format
;
594 case __DRI_IMAGE_ATTRIB_WIDTH
:
595 *value
= image
->width
;
597 case __DRI_IMAGE_ATTRIB_HEIGHT
:
598 *value
= image
->height
;
600 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
601 if (image
->planar_format
== NULL
)
603 *value
= image
->planar_format
->components
;
605 case __DRI_IMAGE_ATTRIB_FD
:
606 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
607 case __DRI_IMAGE_ATTRIB_FOURCC
:
608 return intel_lookup_fourcc(image
->dri_format
, value
);
609 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
619 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
623 image
= calloc(1, sizeof *image
);
627 drm_intel_bo_reference(orig_image
->bo
);
628 image
->bo
= orig_image
->bo
;
629 image
->internal_format
= orig_image
->internal_format
;
630 image
->planar_format
= orig_image
->planar_format
;
631 image
->dri_format
= orig_image
->dri_format
;
632 image
->format
= orig_image
->format
;
633 image
->offset
= orig_image
->offset
;
634 image
->width
= orig_image
->width
;
635 image
->height
= orig_image
->height
;
636 image
->pitch
= orig_image
->pitch
;
637 image
->tile_x
= orig_image
->tile_x
;
638 image
->tile_y
= orig_image
->tile_y
;
639 image
->has_depthstencil
= orig_image
->has_depthstencil
;
640 image
->data
= loaderPrivate
;
642 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
643 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
649 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
651 if (use
& __DRI_IMAGE_USE_CURSOR
) {
652 if (image
->width
!= 64 || image
->height
!= 64)
660 intel_create_image_from_names(__DRIscreen
*screen
,
661 int width
, int height
, int fourcc
,
662 int *names
, int num_names
,
663 int *strides
, int *offsets
,
666 struct intel_image_format
*f
= NULL
;
670 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
673 f
= intel_image_format_lookup(fourcc
);
677 image
= intel_create_image_from_name(screen
, width
, height
,
678 __DRI_IMAGE_FORMAT_NONE
,
679 names
[0], strides
[0],
685 image
->planar_format
= f
;
686 for (i
= 0; i
< f
->nplanes
; i
++) {
687 index
= f
->planes
[i
].buffer_index
;
688 image
->offsets
[index
] = offsets
[index
];
689 image
->strides
[index
] = strides
[index
];
696 intel_create_image_from_fds(__DRIscreen
*screen
,
697 int width
, int height
, int fourcc
,
698 int *fds
, int num_fds
, int *strides
, int *offsets
,
701 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
702 struct intel_image_format
*f
;
706 if (fds
== NULL
|| num_fds
< 1)
709 /* We only support all planes from the same bo */
710 for (i
= 0; i
< num_fds
; i
++)
711 if (fds
[0] != fds
[i
])
714 f
= intel_image_format_lookup(fourcc
);
719 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
721 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
726 image
->width
= width
;
727 image
->height
= height
;
728 image
->pitch
= strides
[0];
730 image
->planar_format
= f
;
732 for (i
= 0; i
< f
->nplanes
; i
++) {
733 index
= f
->planes
[i
].buffer_index
;
734 image
->offsets
[index
] = offsets
[index
];
735 image
->strides
[index
] = strides
[index
];
737 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
738 const int end
= offsets
[index
] + plane_height
* strides
[index
];
743 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
745 if (image
->bo
== NULL
) {
750 if (f
->nplanes
== 1) {
751 image
->offset
= image
->offsets
[0];
752 intel_image_warn_if_unaligned(image
, __func__
);
759 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
760 int width
, int height
, int fourcc
,
761 int *fds
, int num_fds
,
762 int *strides
, int *offsets
,
763 enum __DRIYUVColorSpace yuv_color_space
,
764 enum __DRISampleRange sample_range
,
765 enum __DRIChromaSiting horizontal_siting
,
766 enum __DRIChromaSiting vertical_siting
,
771 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
774 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
778 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
779 num_fds
, strides
, offsets
,
783 * Invalid parameters and any inconsistencies between are assumed to be
784 * checked by the caller. Therefore besides unsupported formats one can fail
785 * only in allocation.
788 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
792 image
->dma_buf_imported
= true;
793 image
->yuv_color_space
= yuv_color_space
;
794 image
->sample_range
= sample_range
;
795 image
->horizontal_siting
= horizontal_siting
;
796 image
->vertical_siting
= vertical_siting
;
798 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
803 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
805 int width
, height
, offset
, stride
, dri_format
, index
;
806 struct intel_image_format
*f
;
809 if (parent
== NULL
|| parent
->planar_format
== NULL
)
812 f
= parent
->planar_format
;
814 if (plane
>= f
->nplanes
)
817 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
818 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
819 dri_format
= f
->planes
[plane
].dri_format
;
820 index
= f
->planes
[plane
].buffer_index
;
821 offset
= parent
->offsets
[index
];
822 stride
= parent
->strides
[index
];
824 image
= intel_allocate_image(dri_format
, loaderPrivate
);
828 if (offset
+ height
* stride
> parent
->bo
->size
) {
829 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
834 image
->bo
= parent
->bo
;
835 drm_intel_bo_reference(parent
->bo
);
837 image
->width
= width
;
838 image
->height
= height
;
839 image
->pitch
= stride
;
840 image
->offset
= offset
;
842 intel_image_warn_if_unaligned(image
, __func__
);
847 static const __DRIimageExtension intelImageExtension
= {
848 .base
= { __DRI_IMAGE
, 11 },
850 .createImageFromName
= intel_create_image_from_name
,
851 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
852 .destroyImage
= intel_destroy_image
,
853 .createImage
= intel_create_image
,
854 .queryImage
= intel_query_image
,
855 .dupImage
= intel_dup_image
,
856 .validateUsage
= intel_validate_usage
,
857 .createImageFromNames
= intel_create_image_from_names
,
858 .fromPlanar
= intel_from_planar
,
859 .createImageFromTexture
= intel_create_image_from_texture
,
860 .createImageFromFds
= intel_create_image_from_fds
,
861 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
863 .getCapabilities
= NULL
867 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
869 const struct intel_screen
*const intelScreen
=
870 (struct intel_screen
*) psp
->driverPrivate
;
873 case __DRI2_RENDERER_VENDOR_ID
:
876 case __DRI2_RENDERER_DEVICE_ID
:
877 value
[0] = intelScreen
->deviceID
;
879 case __DRI2_RENDERER_ACCELERATED
:
882 case __DRI2_RENDERER_VIDEO_MEMORY
: {
883 /* Once a batch uses more than 75% of the maximum mappable size, we
884 * assume that there's some fragmentation, and we start doing extra
885 * flushing, etc. That's the big cliff apps will care about.
888 size_t mappable_size
;
890 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
892 const unsigned gpu_mappable_megabytes
=
893 (aper_size
/ (1024 * 1024)) * 3 / 4;
895 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
896 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
898 if (system_memory_pages
<= 0 || system_page_size
<= 0)
901 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
902 * (uint64_t) system_page_size
;
904 const unsigned system_memory_megabytes
=
905 (unsigned) (system_memory_bytes
/ (1024 * 1024));
907 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
910 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
914 return driQueryRendererIntegerCommon(psp
, param
, value
);
921 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
923 const struct intel_screen
*intelScreen
=
924 (struct intel_screen
*) psp
->driverPrivate
;
927 case __DRI2_RENDERER_VENDOR_ID
:
928 value
[0] = brw_vendor_string
;
930 case __DRI2_RENDERER_DEVICE_ID
:
931 value
[0] = brw_get_renderer_string(intelScreen
);
940 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
941 .base
= { __DRI2_RENDERER_QUERY
, 1 },
943 .queryInteger
= brw_query_renderer_integer
,
944 .queryString
= brw_query_renderer_string
947 static const __DRIrobustnessExtension dri2Robustness
= {
948 .base
= { __DRI2_ROBUSTNESS
, 1 }
951 static const __DRIextension
*intelScreenExtensions
[] = {
952 &intelTexBufferExtension
.base
,
953 &intelFenceExtension
.base
,
954 &intelFlushExtension
.base
,
955 &intelImageExtension
.base
,
956 &intelRendererQueryExtension
.base
,
957 &dri2ConfigQueryExtension
.base
,
961 static const __DRIextension
*intelRobustScreenExtensions
[] = {
962 &intelTexBufferExtension
.base
,
963 &intelFenceExtension
.base
,
964 &intelFlushExtension
.base
,
965 &intelImageExtension
.base
,
966 &intelRendererQueryExtension
.base
,
967 &dri2ConfigQueryExtension
.base
,
968 &dri2Robustness
.base
,
973 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
976 struct drm_i915_getparam gp
;
978 memset(&gp
, 0, sizeof(gp
));
982 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
985 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
992 intel_get_boolean(struct intel_screen
*screen
, int param
)
995 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
999 intel_get_integer(struct intel_screen
*screen
, int param
)
1003 if (intel_get_param(screen
, param
, &value
) == 0)
1010 intelDestroyScreen(__DRIscreen
* sPriv
)
1012 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
1014 dri_bufmgr_destroy(intelScreen
->bufmgr
);
1015 driDestroyOptionInfo(&intelScreen
->optionCache
);
1017 ralloc_free(intelScreen
);
1018 sPriv
->driverPrivate
= NULL
;
1023 * This is called when we need to set up GL rendering to a new X window.
1026 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
1027 __DRIdrawable
* driDrawPriv
,
1028 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1030 struct intel_renderbuffer
*rb
;
1031 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
1032 mesa_format rgbFormat
;
1033 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
1034 struct gl_framebuffer
*fb
;
1039 fb
= CALLOC_STRUCT(gl_framebuffer
);
1043 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1045 if (screen
->winsys_msaa_samples_override
!= -1) {
1046 num_samples
= screen
->winsys_msaa_samples_override
;
1047 fb
->Visual
.samples
= num_samples
;
1050 if (mesaVis
->redBits
== 5) {
1051 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1052 : MESA_FORMAT_B5G6R5_UNORM
;
1053 } else if (mesaVis
->sRGBCapable
) {
1054 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1055 : MESA_FORMAT_B8G8R8A8_SRGB
;
1056 } else if (mesaVis
->alphaBits
== 0) {
1057 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1058 : MESA_FORMAT_B8G8R8X8_UNORM
;
1060 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1061 : MESA_FORMAT_B8G8R8A8_SRGB
;
1062 fb
->Visual
.sRGBCapable
= true;
1065 /* setup the hardware-based renderbuffers */
1066 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1067 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1069 if (mesaVis
->doubleBufferMode
) {
1070 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1071 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1075 * Assert here that the gl_config has an expected depth/stencil bit
1076 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1077 * which constructs the advertised configs.)
1079 if (mesaVis
->depthBits
== 24) {
1080 assert(mesaVis
->stencilBits
== 8);
1082 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1083 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1085 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1086 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1088 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1091 * Use combined depth/stencil. Note that the renderbuffer is
1092 * attached to two attachment points.
1094 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1096 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1097 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1100 else if (mesaVis
->depthBits
== 16) {
1101 assert(mesaVis
->stencilBits
== 0);
1102 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1104 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1107 assert(mesaVis
->depthBits
== 0);
1108 assert(mesaVis
->stencilBits
== 0);
1111 /* now add any/all software-based renderbuffers we may need */
1112 _swrast_add_soft_renderbuffers(fb
,
1113 false, /* never sw color */
1114 false, /* never sw depth */
1115 false, /* never sw stencil */
1116 mesaVis
->accumRedBits
> 0,
1117 false, /* never sw alpha */
1118 false /* never sw aux */ );
1119 driDrawPriv
->driverPrivate
= fb
;
1125 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1127 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1129 _mesa_reference_framebuffer(&fb
, NULL
);
1133 intel_detect_sseu(struct intel_screen
*intelScreen
)
1135 assert(intelScreen
->devinfo
->gen
>= 8);
1138 intelScreen
->subslice_total
= -1;
1139 intelScreen
->eu_total
= -1;
1141 ret
= intel_get_param(intelScreen
, I915_PARAM_SUBSLICE_TOTAL
,
1142 &intelScreen
->subslice_total
);
1143 if (ret
< 0 && ret
!= -EINVAL
)
1146 ret
= intel_get_param(intelScreen
,
1147 I915_PARAM_EU_TOTAL
, &intelScreen
->eu_total
);
1148 if (ret
< 0 && ret
!= -EINVAL
)
1151 /* Without this information, we cannot get the right Braswell brandstrings,
1152 * and we have to use conservative numbers for GPGPU on many platforms, but
1153 * otherwise, things will just work.
1155 if (intelScreen
->subslice_total
< 1 || intelScreen
->eu_total
< 1)
1157 "Kernel 4.1 required to properly query GPU properties.\n");
1162 intelScreen
->subslice_total
= -1;
1163 intelScreen
->eu_total
= -1;
1164 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1168 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1170 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1172 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1174 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1175 if (intelScreen
->bufmgr
== NULL
) {
1176 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1177 __func__
, __LINE__
);
1181 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1183 if (!intel_get_boolean(intelScreen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1184 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1192 intel_detect_swizzling(struct intel_screen
*screen
)
1194 drm_intel_bo
*buffer
;
1195 unsigned long flags
= 0;
1196 unsigned long aligned_pitch
;
1197 uint32_t tiling
= I915_TILING_X
;
1198 uint32_t swizzle_mode
= 0;
1200 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1202 &tiling
, &aligned_pitch
, flags
);
1206 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1207 drm_intel_bo_unreference(buffer
);
1209 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1216 intel_detect_timestamp(struct intel_screen
*screen
)
1218 uint64_t dummy
= 0, last
= 0;
1219 int upper
, lower
, loops
;
1221 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1222 * TIMESTAMP register being shifted and the low 32bits always zero.
1224 * More recent kernels offer an interface to read the full 36bits
1227 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1230 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1231 * upper 32bits for a rapidly changing timestamp.
1233 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1237 for (loops
= 0; loops
< 10; loops
++) {
1238 /* The TIMESTAMP should change every 80ns, so several round trips
1239 * through the kernel should be enough to advance it.
1241 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1244 upper
+= (dummy
>> 32) != (last
>> 32);
1245 if (upper
> 1) /* beware 32bit counter overflow */
1246 return 2; /* upper dword holds the low 32bits of the timestamp */
1248 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1250 return 1; /* timestamp is unshifted */
1255 /* No advancement? No timestamp! */
1260 * Return array of MSAA modes supported by the hardware. The array is
1261 * zero-terminated and sorted in decreasing order.
1264 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1266 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1267 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1268 static const int gen7_modes
[] = {8, 4, 0, -1};
1269 static const int gen6_modes
[] = {4, 0, -1};
1270 static const int gen4_modes
[] = {0, -1};
1272 if (screen
->devinfo
->gen
>= 9) {
1274 } else if (screen
->devinfo
->gen
>= 8) {
1276 } else if (screen
->devinfo
->gen
>= 7) {
1278 } else if (screen
->devinfo
->gen
== 6) {
1285 static __DRIconfig
**
1286 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1288 static const mesa_format formats
[] = {
1289 MESA_FORMAT_B5G6R5_UNORM
,
1290 MESA_FORMAT_B8G8R8A8_UNORM
,
1291 MESA_FORMAT_B8G8R8X8_UNORM
1294 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1295 static const GLenum back_buffer_modes
[] = {
1296 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1299 static const uint8_t singlesample_samples
[1] = {0};
1300 static const uint8_t multisample_samples
[2] = {4, 8};
1302 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1303 const struct gen_device_info
*devinfo
= screen
->devinfo
;
1304 uint8_t depth_bits
[4], stencil_bits
[4];
1305 __DRIconfig
**configs
= NULL
;
1307 /* Generate singlesample configs without accumulation buffer. */
1308 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1309 __DRIconfig
**new_configs
;
1310 int num_depth_stencil_bits
= 2;
1312 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1313 * buffer that has a different number of bits per pixel than the color
1314 * buffer, gen >= 6 supports this.
1317 stencil_bits
[0] = 0;
1319 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1321 stencil_bits
[1] = 0;
1322 if (devinfo
->gen
>= 6) {
1324 stencil_bits
[2] = 8;
1325 num_depth_stencil_bits
= 3;
1329 stencil_bits
[1] = 8;
1332 new_configs
= driCreateConfigs(formats
[i
],
1335 num_depth_stencil_bits
,
1336 back_buffer_modes
, 2,
1337 singlesample_samples
, 1,
1339 configs
= driConcatConfigs(configs
, new_configs
);
1342 /* Generate the minimum possible set of configs that include an
1343 * accumulation buffer.
1345 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1346 __DRIconfig
**new_configs
;
1348 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1350 stencil_bits
[0] = 0;
1353 stencil_bits
[0] = 8;
1356 new_configs
= driCreateConfigs(formats
[i
],
1357 depth_bits
, stencil_bits
, 1,
1358 back_buffer_modes
, 1,
1359 singlesample_samples
, 1,
1361 configs
= driConcatConfigs(configs
, new_configs
);
1364 /* Generate multisample configs.
1366 * This loop breaks early, and hence is a no-op, on gen < 6.
1368 * Multisample configs must follow the singlesample configs in order to
1369 * work around an X server bug present in 1.12. The X server chooses to
1370 * associate the first listed RGBA888-Z24S8 config, regardless of its
1371 * sample count, with the 32-bit depth visual used for compositing.
1373 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1374 * supported. Singlebuffer configs are not supported because no one wants
1377 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1378 if (devinfo
->gen
< 6)
1381 __DRIconfig
**new_configs
;
1382 const int num_depth_stencil_bits
= 2;
1383 int num_msaa_modes
= 0;
1386 stencil_bits
[0] = 0;
1388 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1390 stencil_bits
[1] = 0;
1393 stencil_bits
[1] = 8;
1396 if (devinfo
->gen
>= 7)
1398 else if (devinfo
->gen
== 6)
1401 new_configs
= driCreateConfigs(formats
[i
],
1404 num_depth_stencil_bits
,
1405 back_buffer_modes
, 1,
1406 multisample_samples
,
1409 configs
= driConcatConfigs(configs
, new_configs
);
1412 if (configs
== NULL
) {
1413 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1422 set_max_gl_versions(struct intel_screen
*screen
)
1424 __DRIscreen
*psp
= screen
->driScrnPriv
;
1426 switch (screen
->devinfo
->gen
) {
1429 psp
->max_gl_core_version
= 44;
1430 psp
->max_gl_compat_version
= 30;
1431 psp
->max_gl_es1_version
= 11;
1432 psp
->max_gl_es2_version
= 31;
1435 psp
->max_gl_core_version
= 33;
1436 psp
->max_gl_compat_version
= 30;
1437 psp
->max_gl_es1_version
= 11;
1438 psp
->max_gl_es2_version
= screen
->devinfo
->is_haswell
? 31 : 30;
1441 psp
->max_gl_core_version
= 33;
1442 psp
->max_gl_compat_version
= 30;
1443 psp
->max_gl_es1_version
= 11;
1444 psp
->max_gl_es2_version
= 30;
1448 psp
->max_gl_core_version
= 0;
1449 psp
->max_gl_compat_version
= 21;
1450 psp
->max_gl_es1_version
= 11;
1451 psp
->max_gl_es2_version
= 20;
1454 unreachable("unrecognized intel_screen::gen");
1459 * Return the revision (generally the revid field of the PCI header) of the
1462 * XXX: This function is useful to keep around even if it is not currently in
1463 * use. It is necessary for new platforms and revision specific workarounds or
1464 * features. Please don't remove it so that we know it at least continues to
1467 static __attribute__((__unused__
)) int
1468 brw_get_revision(int fd
)
1470 struct drm_i915_getparam gp
;
1474 memset(&gp
, 0, sizeof(gp
));
1475 gp
.param
= I915_PARAM_REVISION
;
1476 gp
.value
= &revision
;
1478 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1485 /* Drop when RS headers get pulled to libdrm */
1486 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1487 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1491 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1493 struct brw_context
*brw
= (struct brw_context
*)data
;
1496 va_start(args
, fmt
);
1498 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1499 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1500 MESA_DEBUG_TYPE_OTHER
,
1501 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1506 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1508 struct brw_context
*brw
= (struct brw_context
*)data
;
1511 va_start(args
, fmt
);
1513 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1515 va_copy(args_copy
, args
);
1516 vfprintf(stderr
, fmt
, args_copy
);
1520 if (brw
->perf_debug
) {
1522 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1523 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1524 MESA_DEBUG_TYPE_PERFORMANCE
,
1525 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1531 * This is the driver specific part of the createNewScreen entry point.
1532 * Called when using DRI2.
1534 * \return the struct gl_config supported by this driver
1537 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1539 struct intel_screen
*intelScreen
;
1541 if (psp
->image
.loader
) {
1542 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1543 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1545 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1546 "support required\n");
1550 /* Allocate the private area */
1551 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1553 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1556 /* parse information in __driConfigOptions */
1557 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1559 intelScreen
->driScrnPriv
= psp
;
1560 psp
->driverPrivate
= (void *) intelScreen
;
1562 if (!intel_init_bufmgr(intelScreen
))
1565 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1566 intelScreen
->devinfo
= gen_get_device_info(intelScreen
->deviceID
);
1567 if (!intelScreen
->devinfo
)
1570 brw_process_intel_debug_variable();
1572 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1573 dri_bufmgr_set_debug(intelScreen
->bufmgr
, true);
1575 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && intelScreen
->devinfo
->gen
< 7) {
1577 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1578 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1581 if (INTEL_DEBUG
& DEBUG_AUB
)
1582 drm_intel_bufmgr_gem_set_aub_dump(intelScreen
->bufmgr
, true);
1584 #ifndef I915_PARAM_MMAP_GTT_VERSION
1585 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
1587 if (intel_get_integer(intelScreen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1588 /* Theorectically unlimited! At least for individual objects...
1590 * Currently the entire (global) address space for all GTT maps is
1591 * limited to 64bits. That is all objects on the system that are
1592 * setup for GTT mmapping must fit within 64bits. An attempt to use
1593 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1595 * Long before we hit that limit, we will be practically limited by
1596 * that any single object must fit in physical memory (RAM). The upper
1597 * limit on the CPU's address space is currently 48bits (Skylake), of
1598 * which only 39bits can be physical memory. (The GPU itself also has
1599 * a 48bit addressable virtual space.) We can fit over 32 million
1600 * objects of the current maximum allocable size before running out
1603 intelScreen
->max_gtt_map_object_size
= UINT64_MAX
;
1605 /* Estimate the size of the mappable aperture into the GTT. There's an
1606 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1607 * It turns out it's basically always 256MB, though some ancient hardware
1610 uint32_t gtt_size
= 256 * 1024 * 1024;
1612 /* We don't want to map two objects such that a memcpy between them would
1613 * just fault one mapping in and then the other over and over forever. So
1614 * we would need to divide the GTT size by 2. Additionally, some GTT is
1615 * taken up by things like the framebuffer and the ringbuffer and such, so
1616 * be more conservative.
1618 intelScreen
->max_gtt_map_object_size
= gtt_size
/ 4;
1621 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1622 intelScreen
->hw_has_timestamp
= intel_detect_timestamp(intelScreen
);
1624 /* GENs prior to 8 do not support EU/Subslice info */
1625 if (intelScreen
->devinfo
->gen
>= 8) {
1626 intel_detect_sseu(intelScreen
);
1627 } else if (intelScreen
->devinfo
->gen
== 7) {
1628 intelScreen
->subslice_total
= 1 << (intelScreen
->devinfo
->gt
- 1);
1631 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1633 intelScreen
->winsys_msaa_samples_override
=
1634 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1635 printf("Forcing winsys sample count to %d\n",
1636 intelScreen
->winsys_msaa_samples_override
);
1638 intelScreen
->winsys_msaa_samples_override
= -1;
1641 set_max_gl_versions(intelScreen
);
1643 /* Notification of GPU resets requires hardware contexts and a kernel new
1644 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1645 * supported, calling it with a context of 0 will either generate EPERM or
1646 * no error. If the ioctl is not supported, it always generate EINVAL.
1647 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1648 * extension to the loader.
1650 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1652 if (intelScreen
->devinfo
->gen
>= 6) {
1653 struct drm_i915_reset_stats stats
;
1654 memset(&stats
, 0, sizeof(stats
));
1656 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1658 intelScreen
->has_context_reset_notification
=
1659 (ret
!= -1 || errno
!= EINVAL
);
1662 if (intel_get_param(intelScreen
, I915_PARAM_CMD_PARSER_VERSION
,
1663 &intelScreen
->cmd_parser_version
) < 0) {
1664 intelScreen
->cmd_parser_version
= 0;
1667 /* Haswell requires command parser version 6 in order to write to the
1668 * MI_MATH GPR registers, and version 7 in order to use
1669 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1671 intelScreen
->has_mi_math_and_lrr
= intelScreen
->devinfo
->gen
>= 8 ||
1672 (intelScreen
->devinfo
->is_haswell
&&
1673 intelScreen
->cmd_parser_version
>= 7);
1675 psp
->extensions
= !intelScreen
->has_context_reset_notification
1676 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1678 intelScreen
->compiler
= brw_compiler_create(intelScreen
,
1679 intelScreen
->devinfo
);
1680 intelScreen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1681 intelScreen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1682 intelScreen
->program_id
= 1;
1684 if (intelScreen
->devinfo
->has_resource_streamer
) {
1685 intelScreen
->has_resource_streamer
=
1686 intel_get_boolean(intelScreen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1689 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1692 struct intel_buffer
{
1697 static __DRIbuffer
*
1698 intelAllocateBuffer(__DRIscreen
*screen
,
1699 unsigned attachment
, unsigned format
,
1700 int width
, int height
)
1702 struct intel_buffer
*intelBuffer
;
1703 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1705 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1706 attachment
== __DRI_BUFFER_BACK_LEFT
);
1708 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1709 if (intelBuffer
== NULL
)
1712 /* The front and back buffers are color buffers, which are X tiled. */
1713 uint32_t tiling
= I915_TILING_X
;
1714 unsigned long pitch
;
1715 int cpp
= format
/ 8;
1716 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1717 "intelAllocateBuffer",
1722 BO_ALLOC_FOR_RENDER
);
1724 if (intelBuffer
->bo
== NULL
) {
1729 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1731 intelBuffer
->base
.attachment
= attachment
;
1732 intelBuffer
->base
.cpp
= cpp
;
1733 intelBuffer
->base
.pitch
= pitch
;
1735 return &intelBuffer
->base
;
1739 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1741 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1743 drm_intel_bo_unreference(intelBuffer
->bo
);
1747 static const struct __DriverAPIRec brw_driver_api
= {
1748 .InitScreen
= intelInitScreen2
,
1749 .DestroyScreen
= intelDestroyScreen
,
1750 .CreateContext
= brwCreateContext
,
1751 .DestroyContext
= intelDestroyContext
,
1752 .CreateBuffer
= intelCreateBuffer
,
1753 .DestroyBuffer
= intelDestroyBuffer
,
1754 .MakeCurrent
= intelMakeCurrent
,
1755 .UnbindContext
= intelUnbindContext
,
1756 .AllocateBuffer
= intelAllocateBuffer
,
1757 .ReleaseBuffer
= intelReleaseBuffer
1760 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1761 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1762 .vtable
= &brw_driver_api
,
1765 static const __DRIextension
*brw_driver_extensions
[] = {
1766 &driCoreExtension
.base
,
1767 &driImageDriverExtension
.base
,
1768 &driDRI2Extension
.base
,
1770 &brw_config_options
.base
,
1774 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1776 globalDriverAPI
= &brw_driver_api
;
1778 return brw_driver_extensions
;