2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_defines.h"
39 #include "compiler/nir/nir.h"
44 #ifndef DRM_FORMAT_MOD_INVALID
45 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
48 #ifndef DRM_FORMAT_MOD_LINEAR
49 #define DRM_FORMAT_MOD_LINEAR 0
52 static const __DRIconfigOptionsExtension brw_config_options
= {
53 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
56 DRI_CONF_SECTION_PERFORMANCE
57 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
58 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
59 * DRI_CONF_BO_REUSE_ALL
61 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
62 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
63 DRI_CONF_ENUM(0, "Disable buffer object reuse")
64 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
69 DRI_CONF_SECTION_QUALITY
70 DRI_CONF_FORCE_S3TC_ENABLE("false")
72 DRI_CONF_PRECISE_TRIG("false")
74 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
75 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
76 "given integer. If negative, then do not clamp.")
80 DRI_CONF_SECTION_DEBUG
81 DRI_CONF_NO_RAST("false")
82 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
83 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
84 DRI_CONF_DISABLE_THROTTLING("false")
85 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
86 DRI_CONF_FORCE_GLSL_VERSION(0)
87 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
88 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
89 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
90 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
91 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
93 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
94 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
98 DRI_CONF_SECTION_MISCELLANEOUS
99 DRI_CONF_GLSL_ZERO_INIT("false")
104 #include "intel_batchbuffer.h"
105 #include "intel_buffers.h"
106 #include "intel_bufmgr.h"
107 #include "intel_fbo.h"
108 #include "intel_mipmap_tree.h"
109 #include "intel_screen.h"
110 #include "intel_tex.h"
111 #include "intel_image.h"
113 #include "brw_context.h"
115 #include "i915_drm.h"
118 * For debugging purposes, this returns a time in seconds.
125 clock_gettime(CLOCK_MONOTONIC
, &tp
);
127 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
130 static const __DRItexBufferExtension intelTexBufferExtension
= {
131 .base
= { __DRI_TEX_BUFFER
, 3 },
133 .setTexBuffer
= intelSetTexBuffer
,
134 .setTexBuffer2
= intelSetTexBuffer2
,
135 .releaseTexBuffer
= NULL
,
139 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
140 __DRIdrawable
*dPriv
,
142 enum __DRI2throttleReason reason
)
144 struct brw_context
*brw
= cPriv
->driverPrivate
;
149 struct gl_context
*ctx
= &brw
->ctx
;
151 FLUSH_VERTICES(ctx
, 0);
153 if (flags
& __DRI2_FLUSH_DRAWABLE
)
154 intel_resolve_for_dri2_flush(brw
, dPriv
);
156 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
157 brw
->need_swap_throttle
= true;
158 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
159 brw
->need_flush_throttle
= true;
161 intel_batchbuffer_flush(brw
);
165 * Provides compatibility with loaders that only support the older (version
166 * 1-3) flush interface.
168 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
171 intel_dri2_flush(__DRIdrawable
*drawable
)
173 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
174 __DRI2_FLUSH_DRAWABLE
,
175 __DRI2_THROTTLE_SWAPBUFFER
);
178 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
179 .base
= { __DRI2_FLUSH
, 4 },
181 .flush
= intel_dri2_flush
,
182 .invalidate
= dri2InvalidateDrawable
,
183 .flush_with_flags
= intel_dri2_flush_with_flags
,
186 static struct intel_image_format intel_image_formats
[] = {
187 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
188 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
190 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
193 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
196 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
199 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
202 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
205 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
208 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
211 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
214 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
217 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
220 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
222 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
223 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
225 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
227 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
228 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
230 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
235 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
240 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
245 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
250 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
260 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
265 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
270 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
274 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
278 /* For YUYV buffers, we set up two overlapping DRI images and treat
279 * them as planar buffers in the compositors. Plane 0 is GR88 and
280 * samples YU or YV pairs and places Y into the R component, while
281 * plane 1 is ARGB and samples YUYV clusters and places pairs and
282 * places U into the G component and V into A. This lets the
283 * texture sampler interpolate the Y components correctly when
284 * sampling from plane 0, and interpolate U and V correctly when
285 * sampling from plane 1. */
286 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
288 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
292 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
294 uint32_t tiling
, swizzle
;
295 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
297 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
298 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
299 func
, image
->offset
);
303 static struct intel_image_format
*
304 intel_image_format_lookup(int fourcc
)
306 struct intel_image_format
*f
= NULL
;
308 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
309 if (intel_image_formats
[i
].fourcc
== fourcc
) {
310 f
= &intel_image_formats
[i
];
318 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
320 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
321 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
322 *fourcc
= intel_image_formats
[i
].fourcc
;
330 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
335 image
= calloc(1, sizeof *image
);
339 image
->screen
= screen
;
340 image
->dri_format
= dri_format
;
343 image
->format
= driImageFormatToGLFormat(dri_format
);
344 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
345 image
->format
== MESA_FORMAT_NONE
) {
350 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
351 image
->data
= loaderPrivate
;
357 * Sets up a DRIImage structure to point to a slice out of a miptree.
360 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
361 struct intel_mipmap_tree
*mt
, GLuint level
,
364 intel_miptree_make_shareable(brw
, mt
);
366 intel_miptree_check_level_layer(mt
, level
, zoffset
);
368 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
369 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
370 image
->pitch
= mt
->pitch
;
372 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
376 drm_intel_bo_unreference(image
->bo
);
378 drm_intel_bo_reference(mt
->bo
);
382 intel_create_image_from_name(__DRIscreen
*dri_screen
,
383 int width
, int height
, int format
,
384 int name
, int pitch
, void *loaderPrivate
)
386 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
390 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
394 if (image
->format
== MESA_FORMAT_NONE
)
397 cpp
= _mesa_get_format_bytes(image
->format
);
399 image
->width
= width
;
400 image
->height
= height
;
401 image
->pitch
= pitch
* cpp
;
402 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
413 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
414 int renderbuffer
, void *loaderPrivate
)
417 struct brw_context
*brw
= context
->driverPrivate
;
418 struct gl_context
*ctx
= &brw
->ctx
;
419 struct gl_renderbuffer
*rb
;
420 struct intel_renderbuffer
*irb
;
422 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
424 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
428 irb
= intel_renderbuffer(rb
);
429 intel_miptree_make_shareable(brw
, irb
->mt
);
430 image
= calloc(1, sizeof *image
);
434 image
->internal_format
= rb
->InternalFormat
;
435 image
->format
= rb
->Format
;
437 image
->data
= loaderPrivate
;
438 drm_intel_bo_unreference(image
->bo
);
439 image
->bo
= irb
->mt
->bo
;
440 drm_intel_bo_reference(irb
->mt
->bo
);
441 image
->width
= rb
->Width
;
442 image
->height
= rb
->Height
;
443 image
->pitch
= irb
->mt
->pitch
;
444 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
445 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
447 rb
->NeedsFinishRenderTexture
= true;
452 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
453 unsigned texture
, int zoffset
,
459 struct brw_context
*brw
= context
->driverPrivate
;
460 struct gl_texture_object
*obj
;
461 struct intel_texture_object
*iobj
;
464 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
465 if (!obj
|| obj
->Target
!= target
) {
466 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
470 if (target
== GL_TEXTURE_CUBE_MAP
)
473 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
474 iobj
= intel_texture_object(obj
);
475 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
476 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
480 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
481 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
485 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
486 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
489 image
= calloc(1, sizeof *image
);
491 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
495 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
496 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
497 image
->data
= loaderPrivate
;
498 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
499 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
500 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
501 if (image
->dri_format
== MESA_FORMAT_NONE
) {
502 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
507 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
512 intel_destroy_image(__DRIimage
*image
)
514 drm_intel_bo_unreference(image
->bo
);
518 enum modifier_priority
{
519 MODIFIER_PRIORITY_INVALID
= 0,
520 MODIFIER_PRIORITY_LINEAR
,
523 const uint64_t priority_to_modifier
[] = {
524 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
525 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
529 select_best_modifier(struct gen_device_info
*devinfo
,
530 const uint64_t *modifiers
,
531 const unsigned count
)
534 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
536 for (int i
= 0; i
< count
; i
++) {
537 switch (modifiers
[i
]) {
538 case DRM_FORMAT_MOD_LINEAR
:
539 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
541 case DRM_FORMAT_MOD_INVALID
:
547 return priority_to_modifier
[prio
];
551 intel_create_image_common(__DRIscreen
*dri_screen
,
552 int width
, int height
, int format
,
554 const uint64_t *modifiers
,
559 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
560 /* Historically, X-tiled was the default, and so lack of modifier means
563 uint32_t tiling
= I915_TILING_X
;
567 /* Callers of this may specify a modifier, or a dri usage, but not both. The
568 * newer modifier interface deprecates the older usage flags newer modifier
569 * interface deprecates the older usage flags.
571 assert(!(use
&& count
));
573 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
575 case DRM_FORMAT_MOD_LINEAR
:
576 tiling
= I915_TILING_NONE
;
578 case DRM_FORMAT_MOD_INVALID
:
585 if (use
& __DRI_IMAGE_USE_CURSOR
) {
586 if (width
!= 64 || height
!= 64)
588 tiling
= I915_TILING_NONE
;
591 if (use
& __DRI_IMAGE_USE_LINEAR
)
592 tiling
= I915_TILING_NONE
;
594 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
598 cpp
= _mesa_get_format_bytes(image
->format
);
599 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
600 width
, height
, cpp
, &tiling
,
602 if (image
->bo
== NULL
) {
606 image
->width
= width
;
607 image
->height
= height
;
608 image
->pitch
= pitch
;
609 image
->modifier
= modifier
;
615 intel_create_image(__DRIscreen
*dri_screen
,
616 int width
, int height
, int format
,
620 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
625 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
626 int width
, int height
, int format
,
627 const uint64_t *modifiers
,
628 const unsigned count
,
631 return intel_create_image_common(dri_screen
, width
, height
, format
, 0, NULL
,
636 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
639 case __DRI_IMAGE_ATTRIB_STRIDE
:
640 *value
= image
->pitch
;
642 case __DRI_IMAGE_ATTRIB_HANDLE
:
643 *value
= image
->bo
->handle
;
645 case __DRI_IMAGE_ATTRIB_NAME
:
646 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
647 case __DRI_IMAGE_ATTRIB_FORMAT
:
648 *value
= image
->dri_format
;
650 case __DRI_IMAGE_ATTRIB_WIDTH
:
651 *value
= image
->width
;
653 case __DRI_IMAGE_ATTRIB_HEIGHT
:
654 *value
= image
->height
;
656 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
657 if (image
->planar_format
== NULL
)
659 *value
= image
->planar_format
->components
;
661 case __DRI_IMAGE_ATTRIB_FD
:
662 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
663 case __DRI_IMAGE_ATTRIB_FOURCC
:
664 return intel_lookup_fourcc(image
->dri_format
, value
);
665 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
668 case __DRI_IMAGE_ATTRIB_OFFSET
:
669 *value
= image
->offset
;
671 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
672 *value
= (image
->modifier
& 0xffffffff);
674 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
675 *value
= ((image
->modifier
>> 32) & 0xffffffff);
684 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
688 image
= calloc(1, sizeof *image
);
692 drm_intel_bo_reference(orig_image
->bo
);
693 image
->bo
= orig_image
->bo
;
694 image
->internal_format
= orig_image
->internal_format
;
695 image
->planar_format
= orig_image
->planar_format
;
696 image
->dri_format
= orig_image
->dri_format
;
697 image
->format
= orig_image
->format
;
698 image
->offset
= orig_image
->offset
;
699 image
->width
= orig_image
->width
;
700 image
->height
= orig_image
->height
;
701 image
->pitch
= orig_image
->pitch
;
702 image
->tile_x
= orig_image
->tile_x
;
703 image
->tile_y
= orig_image
->tile_y
;
704 image
->has_depthstencil
= orig_image
->has_depthstencil
;
705 image
->data
= loaderPrivate
;
707 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
708 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
714 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
716 if (use
& __DRI_IMAGE_USE_CURSOR
) {
717 if (image
->width
!= 64 || image
->height
!= 64)
725 intel_create_image_from_names(__DRIscreen
*dri_screen
,
726 int width
, int height
, int fourcc
,
727 int *names
, int num_names
,
728 int *strides
, int *offsets
,
731 struct intel_image_format
*f
= NULL
;
735 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
738 f
= intel_image_format_lookup(fourcc
);
742 image
= intel_create_image_from_name(dri_screen
, width
, height
,
743 __DRI_IMAGE_FORMAT_NONE
,
744 names
[0], strides
[0],
750 image
->planar_format
= f
;
751 for (i
= 0; i
< f
->nplanes
; i
++) {
752 index
= f
->planes
[i
].buffer_index
;
753 image
->offsets
[index
] = offsets
[index
];
754 image
->strides
[index
] = strides
[index
];
761 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
762 int width
, int height
, int fourcc
,
763 int *fds
, int num_fds
, int *strides
, int *offsets
,
766 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
767 struct intel_image_format
*f
;
771 if (fds
== NULL
|| num_fds
< 1)
774 /* We only support all planes from the same bo */
775 for (i
= 0; i
< num_fds
; i
++)
776 if (fds
[0] != fds
[i
])
779 f
= intel_image_format_lookup(fourcc
);
784 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
787 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
793 image
->width
= width
;
794 image
->height
= height
;
795 image
->pitch
= strides
[0];
797 image
->planar_format
= f
;
799 for (i
= 0; i
< f
->nplanes
; i
++) {
800 index
= f
->planes
[i
].buffer_index
;
801 image
->offsets
[index
] = offsets
[index
];
802 image
->strides
[index
] = strides
[index
];
804 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
805 const int end
= offsets
[index
] + plane_height
* strides
[index
];
810 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
812 if (image
->bo
== NULL
) {
817 if (f
->nplanes
== 1) {
818 image
->offset
= image
->offsets
[0];
819 intel_image_warn_if_unaligned(image
, __func__
);
826 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
827 int width
, int height
, int fourcc
,
828 int *fds
, int num_fds
,
829 int *strides
, int *offsets
,
830 enum __DRIYUVColorSpace yuv_color_space
,
831 enum __DRISampleRange sample_range
,
832 enum __DRIChromaSiting horizontal_siting
,
833 enum __DRIChromaSiting vertical_siting
,
838 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
841 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
845 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
846 num_fds
, strides
, offsets
,
850 * Invalid parameters and any inconsistencies between are assumed to be
851 * checked by the caller. Therefore besides unsupported formats one can fail
852 * only in allocation.
855 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
859 image
->dma_buf_imported
= true;
860 image
->yuv_color_space
= yuv_color_space
;
861 image
->sample_range
= sample_range
;
862 image
->horizontal_siting
= horizontal_siting
;
863 image
->vertical_siting
= vertical_siting
;
865 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
870 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
872 int width
, height
, offset
, stride
, dri_format
, index
;
873 struct intel_image_format
*f
;
876 if (parent
== NULL
|| parent
->planar_format
== NULL
)
879 f
= parent
->planar_format
;
881 if (plane
>= f
->nplanes
)
884 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
885 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
886 dri_format
= f
->planes
[plane
].dri_format
;
887 index
= f
->planes
[plane
].buffer_index
;
888 offset
= parent
->offsets
[index
];
889 stride
= parent
->strides
[index
];
891 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
895 if (offset
+ height
* stride
> parent
->bo
->size
) {
896 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
901 image
->bo
= parent
->bo
;
902 drm_intel_bo_reference(parent
->bo
);
904 image
->width
= width
;
905 image
->height
= height
;
906 image
->pitch
= stride
;
907 image
->offset
= offset
;
909 intel_image_warn_if_unaligned(image
, __func__
);
914 static const __DRIimageExtension intelImageExtension
= {
915 .base
= { __DRI_IMAGE
, 13 },
917 .createImageFromName
= intel_create_image_from_name
,
918 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
919 .destroyImage
= intel_destroy_image
,
920 .createImage
= intel_create_image
,
921 .queryImage
= intel_query_image
,
922 .dupImage
= intel_dup_image
,
923 .validateUsage
= intel_validate_usage
,
924 .createImageFromNames
= intel_create_image_from_names
,
925 .fromPlanar
= intel_from_planar
,
926 .createImageFromTexture
= intel_create_image_from_texture
,
927 .createImageFromFds
= intel_create_image_from_fds
,
928 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
930 .getCapabilities
= NULL
,
933 .createImageWithModifiers
= intel_create_image_with_modifiers
,
937 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
938 int param
, unsigned int *value
)
940 const struct intel_screen
*const screen
=
941 (struct intel_screen
*) dri_screen
->driverPrivate
;
944 case __DRI2_RENDERER_VENDOR_ID
:
947 case __DRI2_RENDERER_DEVICE_ID
:
948 value
[0] = screen
->deviceID
;
950 case __DRI2_RENDERER_ACCELERATED
:
953 case __DRI2_RENDERER_VIDEO_MEMORY
: {
954 /* Once a batch uses more than 75% of the maximum mappable size, we
955 * assume that there's some fragmentation, and we start doing extra
956 * flushing, etc. That's the big cliff apps will care about.
959 size_t mappable_size
;
961 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
963 const unsigned gpu_mappable_megabytes
=
964 (aper_size
/ (1024 * 1024)) * 3 / 4;
966 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
967 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
969 if (system_memory_pages
<= 0 || system_page_size
<= 0)
972 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
973 * (uint64_t) system_page_size
;
975 const unsigned system_memory_megabytes
=
976 (unsigned) (system_memory_bytes
/ (1024 * 1024));
978 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
981 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
984 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
988 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
995 brw_query_renderer_string(__DRIscreen
*dri_screen
,
996 int param
, const char **value
)
998 const struct intel_screen
*screen
=
999 (struct intel_screen
*) dri_screen
->driverPrivate
;
1002 case __DRI2_RENDERER_VENDOR_ID
:
1003 value
[0] = brw_vendor_string
;
1005 case __DRI2_RENDERER_DEVICE_ID
:
1006 value
[0] = brw_get_renderer_string(screen
);
1015 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1016 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1018 .queryInteger
= brw_query_renderer_integer
,
1019 .queryString
= brw_query_renderer_string
1022 static const __DRIrobustnessExtension dri2Robustness
= {
1023 .base
= { __DRI2_ROBUSTNESS
, 1 }
1026 static const __DRIextension
*screenExtensions
[] = {
1027 &intelTexBufferExtension
.base
,
1028 &intelFenceExtension
.base
,
1029 &intelFlushExtension
.base
,
1030 &intelImageExtension
.base
,
1031 &intelRendererQueryExtension
.base
,
1032 &dri2ConfigQueryExtension
.base
,
1036 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1037 &intelTexBufferExtension
.base
,
1038 &intelFenceExtension
.base
,
1039 &intelFlushExtension
.base
,
1040 &intelImageExtension
.base
,
1041 &intelRendererQueryExtension
.base
,
1042 &dri2ConfigQueryExtension
.base
,
1043 &dri2Robustness
.base
,
1048 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1051 struct drm_i915_getparam gp
;
1053 memset(&gp
, 0, sizeof(gp
));
1057 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1060 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1067 intel_get_boolean(struct intel_screen
*screen
, int param
)
1070 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1074 intel_get_integer(struct intel_screen
*screen
, int param
)
1078 if (intel_get_param(screen
, param
, &value
) == 0)
1085 intelDestroyScreen(__DRIscreen
* sPriv
)
1087 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1089 dri_bufmgr_destroy(screen
->bufmgr
);
1090 driDestroyOptionInfo(&screen
->optionCache
);
1092 ralloc_free(screen
);
1093 sPriv
->driverPrivate
= NULL
;
1098 * This is called when we need to set up GL rendering to a new X window.
1101 intelCreateBuffer(__DRIscreen
*dri_screen
,
1102 __DRIdrawable
* driDrawPriv
,
1103 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1105 struct intel_renderbuffer
*rb
;
1106 struct intel_screen
*screen
= (struct intel_screen
*)
1107 dri_screen
->driverPrivate
;
1108 mesa_format rgbFormat
;
1109 unsigned num_samples
=
1110 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1111 struct gl_framebuffer
*fb
;
1116 fb
= CALLOC_STRUCT(gl_framebuffer
);
1120 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1122 if (screen
->winsys_msaa_samples_override
!= -1) {
1123 num_samples
= screen
->winsys_msaa_samples_override
;
1124 fb
->Visual
.samples
= num_samples
;
1127 if (mesaVis
->redBits
== 5) {
1128 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1129 : MESA_FORMAT_B5G6R5_UNORM
;
1130 } else if (mesaVis
->sRGBCapable
) {
1131 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1132 : MESA_FORMAT_B8G8R8A8_SRGB
;
1133 } else if (mesaVis
->alphaBits
== 0) {
1134 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1135 : MESA_FORMAT_B8G8R8X8_UNORM
;
1137 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1138 : MESA_FORMAT_B8G8R8A8_SRGB
;
1139 fb
->Visual
.sRGBCapable
= true;
1142 /* setup the hardware-based renderbuffers */
1143 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1144 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1146 if (mesaVis
->doubleBufferMode
) {
1147 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1148 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1152 * Assert here that the gl_config has an expected depth/stencil bit
1153 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1154 * which constructs the advertised configs.)
1156 if (mesaVis
->depthBits
== 24) {
1157 assert(mesaVis
->stencilBits
== 8);
1159 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1160 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1162 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1163 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1165 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1168 * Use combined depth/stencil. Note that the renderbuffer is
1169 * attached to two attachment points.
1171 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1173 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1174 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1177 else if (mesaVis
->depthBits
== 16) {
1178 assert(mesaVis
->stencilBits
== 0);
1179 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1181 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1184 assert(mesaVis
->depthBits
== 0);
1185 assert(mesaVis
->stencilBits
== 0);
1188 /* now add any/all software-based renderbuffers we may need */
1189 _swrast_add_soft_renderbuffers(fb
,
1190 false, /* never sw color */
1191 false, /* never sw depth */
1192 false, /* never sw stencil */
1193 mesaVis
->accumRedBits
> 0,
1194 false, /* never sw alpha */
1195 false /* never sw aux */ );
1196 driDrawPriv
->driverPrivate
= fb
;
1202 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1204 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1206 _mesa_reference_framebuffer(&fb
, NULL
);
1210 intel_detect_sseu(struct intel_screen
*screen
)
1212 assert(screen
->devinfo
.gen
>= 8);
1215 screen
->subslice_total
= -1;
1216 screen
->eu_total
= -1;
1218 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1219 &screen
->subslice_total
);
1220 if (ret
< 0 && ret
!= -EINVAL
)
1223 ret
= intel_get_param(screen
,
1224 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1225 if (ret
< 0 && ret
!= -EINVAL
)
1228 /* Without this information, we cannot get the right Braswell brandstrings,
1229 * and we have to use conservative numbers for GPGPU on many platforms, but
1230 * otherwise, things will just work.
1232 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1234 "Kernel 4.1 required to properly query GPU properties.\n");
1239 screen
->subslice_total
= -1;
1240 screen
->eu_total
= -1;
1241 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1245 intel_init_bufmgr(struct intel_screen
*screen
)
1247 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1249 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1251 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1252 if (screen
->bufmgr
== NULL
) {
1253 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1254 __func__
, __LINE__
);
1258 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1260 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1261 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1269 intel_detect_swizzling(struct intel_screen
*screen
)
1271 drm_intel_bo
*buffer
;
1272 unsigned long flags
= 0;
1273 unsigned long aligned_pitch
;
1274 uint32_t tiling
= I915_TILING_X
;
1275 uint32_t swizzle_mode
= 0;
1277 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1279 &tiling
, &aligned_pitch
, flags
);
1283 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1284 drm_intel_bo_unreference(buffer
);
1286 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1293 intel_detect_timestamp(struct intel_screen
*screen
)
1295 uint64_t dummy
= 0, last
= 0;
1296 int upper
, lower
, loops
;
1298 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1299 * TIMESTAMP register being shifted and the low 32bits always zero.
1301 * More recent kernels offer an interface to read the full 36bits
1304 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1307 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1308 * upper 32bits for a rapidly changing timestamp.
1310 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1314 for (loops
= 0; loops
< 10; loops
++) {
1315 /* The TIMESTAMP should change every 80ns, so several round trips
1316 * through the kernel should be enough to advance it.
1318 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1321 upper
+= (dummy
>> 32) != (last
>> 32);
1322 if (upper
> 1) /* beware 32bit counter overflow */
1323 return 2; /* upper dword holds the low 32bits of the timestamp */
1325 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1327 return 1; /* timestamp is unshifted */
1332 /* No advancement? No timestamp! */
1337 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1339 * Some combinations of hardware and kernel versions allow this feature,
1340 * while others don't. Instead of trying to enumerate every case, just
1341 * try and write a register and see if works.
1344 intel_detect_pipelined_register(struct intel_screen
*screen
,
1345 int reg
, uint32_t expected_value
, bool reset
)
1347 drm_intel_bo
*results
, *bo
;
1349 uint32_t offset
= 0;
1350 bool success
= false;
1352 /* Create a zero'ed temporary buffer for reading our results */
1353 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1354 if (results
== NULL
)
1357 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1361 if (drm_intel_bo_map(bo
, 1))
1364 batch
= bo
->virtual;
1366 /* Write the register. */
1367 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1369 *batch
++ = expected_value
;
1371 /* Save the register's value back to the buffer. */
1372 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1374 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1375 results
, offset
*sizeof(uint32_t),
1376 I915_GEM_DOMAIN_INSTRUCTION
,
1377 I915_GEM_DOMAIN_INSTRUCTION
);
1378 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1380 /* And afterwards clear the register */
1382 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1387 *batch
++ = MI_BATCH_BUFFER_END
;
1389 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1393 /* Check whether the value got written. */
1394 if (drm_intel_bo_map(results
, false) == 0) {
1395 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1396 drm_intel_bo_unmap(results
);
1400 drm_intel_bo_unreference(bo
);
1402 drm_intel_bo_unreference(results
);
1408 intel_detect_pipelined_so(struct intel_screen
*screen
)
1410 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1412 /* Supposedly, Broadwell just works. */
1413 if (devinfo
->gen
>= 8)
1416 if (devinfo
->gen
<= 6)
1419 /* See the big explanation about command parser versions below */
1420 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1423 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1424 * statistics registers), and we already reset it to zero before using it.
1426 return intel_detect_pipelined_register(screen
,
1427 GEN7_SO_WRITE_OFFSET(0),
1433 * Return array of MSAA modes supported by the hardware. The array is
1434 * zero-terminated and sorted in decreasing order.
1437 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1439 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1440 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1441 static const int gen7_modes
[] = {8, 4, 0, -1};
1442 static const int gen6_modes
[] = {4, 0, -1};
1443 static const int gen4_modes
[] = {0, -1};
1445 if (screen
->devinfo
.gen
>= 9) {
1447 } else if (screen
->devinfo
.gen
>= 8) {
1449 } else if (screen
->devinfo
.gen
>= 7) {
1451 } else if (screen
->devinfo
.gen
== 6) {
1458 static __DRIconfig
**
1459 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1461 static const mesa_format formats
[] = {
1462 MESA_FORMAT_B5G6R5_UNORM
,
1463 MESA_FORMAT_B8G8R8A8_UNORM
,
1464 MESA_FORMAT_B8G8R8X8_UNORM
1467 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1468 static const GLenum back_buffer_modes
[] = {
1469 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1472 static const uint8_t singlesample_samples
[1] = {0};
1473 static const uint8_t multisample_samples
[2] = {4, 8};
1475 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1476 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1477 uint8_t depth_bits
[4], stencil_bits
[4];
1478 __DRIconfig
**configs
= NULL
;
1480 /* Generate singlesample configs without accumulation buffer. */
1481 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1482 __DRIconfig
**new_configs
;
1483 int num_depth_stencil_bits
= 2;
1485 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1486 * buffer that has a different number of bits per pixel than the color
1487 * buffer, gen >= 6 supports this.
1490 stencil_bits
[0] = 0;
1492 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1494 stencil_bits
[1] = 0;
1495 if (devinfo
->gen
>= 6) {
1497 stencil_bits
[2] = 8;
1498 num_depth_stencil_bits
= 3;
1502 stencil_bits
[1] = 8;
1505 new_configs
= driCreateConfigs(formats
[i
],
1508 num_depth_stencil_bits
,
1509 back_buffer_modes
, 2,
1510 singlesample_samples
, 1,
1512 configs
= driConcatConfigs(configs
, new_configs
);
1515 /* Generate the minimum possible set of configs that include an
1516 * accumulation buffer.
1518 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1519 __DRIconfig
**new_configs
;
1521 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1523 stencil_bits
[0] = 0;
1526 stencil_bits
[0] = 8;
1529 new_configs
= driCreateConfigs(formats
[i
],
1530 depth_bits
, stencil_bits
, 1,
1531 back_buffer_modes
, 1,
1532 singlesample_samples
, 1,
1534 configs
= driConcatConfigs(configs
, new_configs
);
1537 /* Generate multisample configs.
1539 * This loop breaks early, and hence is a no-op, on gen < 6.
1541 * Multisample configs must follow the singlesample configs in order to
1542 * work around an X server bug present in 1.12. The X server chooses to
1543 * associate the first listed RGBA888-Z24S8 config, regardless of its
1544 * sample count, with the 32-bit depth visual used for compositing.
1546 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1547 * supported. Singlebuffer configs are not supported because no one wants
1550 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1551 if (devinfo
->gen
< 6)
1554 __DRIconfig
**new_configs
;
1555 const int num_depth_stencil_bits
= 2;
1556 int num_msaa_modes
= 0;
1559 stencil_bits
[0] = 0;
1561 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1563 stencil_bits
[1] = 0;
1566 stencil_bits
[1] = 8;
1569 if (devinfo
->gen
>= 7)
1571 else if (devinfo
->gen
== 6)
1574 new_configs
= driCreateConfigs(formats
[i
],
1577 num_depth_stencil_bits
,
1578 back_buffer_modes
, 1,
1579 multisample_samples
,
1582 configs
= driConcatConfigs(configs
, new_configs
);
1585 if (configs
== NULL
) {
1586 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1595 set_max_gl_versions(struct intel_screen
*screen
)
1597 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1598 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1600 switch (screen
->devinfo
.gen
) {
1603 dri_screen
->max_gl_core_version
= 45;
1604 dri_screen
->max_gl_compat_version
= 30;
1605 dri_screen
->max_gl_es1_version
= 11;
1606 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1609 dri_screen
->max_gl_core_version
= 33;
1610 if (screen
->devinfo
.is_haswell
&&
1611 can_do_pipelined_register_writes(screen
)) {
1612 dri_screen
->max_gl_core_version
= 42;
1613 if (can_do_compute_dispatch(screen
))
1614 dri_screen
->max_gl_core_version
= 43;
1615 if (can_do_mi_math_and_lrr(screen
))
1616 dri_screen
->max_gl_core_version
= 45;
1618 dri_screen
->max_gl_compat_version
= 30;
1619 dri_screen
->max_gl_es1_version
= 11;
1620 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1623 dri_screen
->max_gl_core_version
= 33;
1624 dri_screen
->max_gl_compat_version
= 30;
1625 dri_screen
->max_gl_es1_version
= 11;
1626 dri_screen
->max_gl_es2_version
= 30;
1630 dri_screen
->max_gl_core_version
= 0;
1631 dri_screen
->max_gl_compat_version
= 21;
1632 dri_screen
->max_gl_es1_version
= 11;
1633 dri_screen
->max_gl_es2_version
= 20;
1636 unreachable("unrecognized intel_screen::gen");
1641 * Return the revision (generally the revid field of the PCI header) of the
1644 * XXX: This function is useful to keep around even if it is not currently in
1645 * use. It is necessary for new platforms and revision specific workarounds or
1646 * features. Please don't remove it so that we know it at least continues to
1649 static __attribute__((__unused__
)) int
1650 brw_get_revision(int fd
)
1652 struct drm_i915_getparam gp
;
1656 memset(&gp
, 0, sizeof(gp
));
1657 gp
.param
= I915_PARAM_REVISION
;
1658 gp
.value
= &revision
;
1660 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1668 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1670 struct brw_context
*brw
= (struct brw_context
*)data
;
1673 va_start(args
, fmt
);
1675 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1676 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1677 MESA_DEBUG_TYPE_OTHER
,
1678 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1683 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1685 struct brw_context
*brw
= (struct brw_context
*)data
;
1688 va_start(args
, fmt
);
1690 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1692 va_copy(args_copy
, args
);
1693 vfprintf(stderr
, fmt
, args_copy
);
1697 if (brw
->perf_debug
) {
1699 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1700 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1701 MESA_DEBUG_TYPE_PERFORMANCE
,
1702 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1708 * This is the driver specific part of the createNewScreen entry point.
1709 * Called when using DRI2.
1711 * \return the struct gl_config supported by this driver
1714 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1716 struct intel_screen
*screen
;
1718 if (dri_screen
->image
.loader
) {
1719 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1720 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1722 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1723 "support required\n");
1727 /* Allocate the private area */
1728 screen
= rzalloc(NULL
, struct intel_screen
);
1730 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1733 /* parse information in __driConfigOptions */
1734 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1736 screen
->driScrnPriv
= dri_screen
;
1737 dri_screen
->driverPrivate
= (void *) screen
;
1739 if (!intel_init_bufmgr(screen
))
1742 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1743 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1746 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1748 brw_process_intel_debug_variable();
1750 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1751 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1753 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1755 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1756 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1759 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1760 /* Theorectically unlimited! At least for individual objects...
1762 * Currently the entire (global) address space for all GTT maps is
1763 * limited to 64bits. That is all objects on the system that are
1764 * setup for GTT mmapping must fit within 64bits. An attempt to use
1765 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1767 * Long before we hit that limit, we will be practically limited by
1768 * that any single object must fit in physical memory (RAM). The upper
1769 * limit on the CPU's address space is currently 48bits (Skylake), of
1770 * which only 39bits can be physical memory. (The GPU itself also has
1771 * a 48bit addressable virtual space.) We can fit over 32 million
1772 * objects of the current maximum allocable size before running out
1775 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1777 /* Estimate the size of the mappable aperture into the GTT. There's an
1778 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1779 * It turns out it's basically always 256MB, though some ancient hardware
1782 uint32_t gtt_size
= 256 * 1024 * 1024;
1784 /* We don't want to map two objects such that a memcpy between them would
1785 * just fault one mapping in and then the other over and over forever. So
1786 * we would need to divide the GTT size by 2. Additionally, some GTT is
1787 * taken up by things like the framebuffer and the ringbuffer and such, so
1788 * be more conservative.
1790 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1793 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1794 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1796 /* GENs prior to 8 do not support EU/Subslice info */
1797 if (devinfo
->gen
>= 8) {
1798 intel_detect_sseu(screen
);
1799 } else if (devinfo
->gen
== 7) {
1800 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1803 /* Gen7-7.5 kernel requirements / command parser saga:
1806 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1808 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1809 * all batches secure, allowing them to use any feature with no checking.
1810 * This is effectively equivalent to a command parser version of
1811 * \infinity - everything is possible.
1813 * The command parser does not exist, and querying the version will
1817 * The kernel enables the command parser by default, for systems with
1818 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1819 * hardware checker is still enabled, so Haswell and Baytrail cannot
1822 * Ivybridge goes from "everything is possible" to "only what the
1823 * command parser allows" (if the user boots with i915.cmd_parser=0,
1824 * then everything is possible again). We can only safely use features
1825 * allowed by the supported command parser version.
1827 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1828 * implemented by the kernel, even if it's turned off. So, checking
1829 * for version > 0 does not mean that you can write registers. We have
1830 * to try it and see. The version does, however, indicate the age of
1833 * Instead of matching the hardware checker's behavior of converting
1834 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1835 * -EINVAL, making it dangerous to try and use privileged features.
1837 * Effective command parser versions:
1838 * - Haswell: 0 (reporting 1, writes don't work)
1839 * - Baytrail: 0 (reporting 1, writes don't work)
1840 * - Ivybridge: 1 (enabled) or infinite (disabled)
1843 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1844 * effectively version 1 (enabled) or infinite (disabled).
1846 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1847 * Command parser v2 supports predicate writes.
1849 * - Haswell: 0 (reporting 1, writes don't work)
1850 * - Baytrail: 2 (enabled) or infinite (disabled)
1851 * - Ivybridge: 2 (enabled) or infinite (disabled)
1853 * So version >= 2 is enough to know that Ivybridge and Baytrail
1854 * will work. Haswell still can't do anything.
1856 * - v4.0: Version 3 happened. Largely not relevant.
1858 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1859 * L3 config registers are properly saved and restored as part
1860 * of the hardware context. We can approximately detect this point
1861 * in time by checking if I915_PARAM_REVISION is recognized - it
1862 * landed in a later commit, but in the same release cycle.
1864 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1865 * Command parser finally gains secure batch promotion. On Haswell,
1866 * the hardware checker gets disabled, which finally allows it to do
1867 * privileged commands.
1869 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1870 * - Haswell: 3 (enabled) or 0 (disabled)
1871 * - Baytrail: 3 (enabled) or infinite (disabled)
1872 * - Ivybridge: 3 (enabled) or infinite (disabled)
1874 * Unfortunately, detecting this point in time is tricky, because
1875 * no version bump happened when this important change occurred.
1876 * On Haswell, if we can write any register, then the kernel is at
1877 * least this new, and we can start trusting the version number.
1879 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
1880 * Command parser reaches version 4, allowing access to Haswell
1881 * atomic scratch and chicken3 registers. If version >= 4, we know
1882 * the kernel is new enough to support privileged features on all
1883 * hardware. However, the user might have disabled it...and the
1884 * kernel will still report version 4. So we still have to guess
1887 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
1888 * Command parser v5 whitelists indirect compute shader dispatch
1889 * registers, needed for OpenGL 4.3 and later.
1892 * Command parser v7 lets us use MI_MATH on Haswell.
1894 * Additionally, the kernel begins reporting version 0 when
1895 * the command parser is disabled, allowing us to skip the
1896 * guess-and-check step on Haswell. Unfortunately, this also
1897 * means that we can no longer use it as an indicator of the
1898 * age of the kernel.
1900 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1901 &screen
->cmd_parser_version
) < 0) {
1902 /* Command parser does not exist - getparam is unrecognized */
1903 screen
->cmd_parser_version
= 0;
1906 if (!intel_detect_pipelined_so(screen
)) {
1907 /* We can't do anything, so the effective version is 0. */
1908 screen
->cmd_parser_version
= 0;
1910 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1913 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1915 screen
->winsys_msaa_samples_override
=
1916 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1917 printf("Forcing winsys sample count to %d\n",
1918 screen
->winsys_msaa_samples_override
);
1920 screen
->winsys_msaa_samples_override
= -1;
1923 set_max_gl_versions(screen
);
1925 /* Notification of GPU resets requires hardware contexts and a kernel new
1926 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1927 * supported, calling it with a context of 0 will either generate EPERM or
1928 * no error. If the ioctl is not supported, it always generate EINVAL.
1929 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1930 * extension to the loader.
1932 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1934 if (devinfo
->gen
>= 6) {
1935 struct drm_i915_reset_stats stats
;
1936 memset(&stats
, 0, sizeof(stats
));
1938 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1940 screen
->has_context_reset_notification
=
1941 (ret
!= -1 || errno
!= EINVAL
);
1944 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
1945 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1947 /* Haswell requires command parser version 4 in order to have L3
1948 * atomic scratch1 and chicken3 bits
1950 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
1951 screen
->kernel_features
|=
1952 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1955 /* Haswell requires command parser version 6 in order to write to the
1956 * MI_MATH GPR registers, and version 7 in order to use
1957 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1959 if (devinfo
->gen
>= 8 ||
1960 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1961 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1964 /* Gen7 needs at least command parser version 5 to support compute */
1965 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
1966 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1968 dri_screen
->extensions
= !screen
->has_context_reset_notification
1969 ? screenExtensions
: intelRobustScreenExtensions
;
1971 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
1972 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1973 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1974 screen
->program_id
= 1;
1976 screen
->has_exec_fence
=
1977 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
1979 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1982 struct intel_buffer
{
1987 static __DRIbuffer
*
1988 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1989 unsigned attachment
, unsigned format
,
1990 int width
, int height
)
1992 struct intel_buffer
*intelBuffer
;
1993 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1995 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1996 attachment
== __DRI_BUFFER_BACK_LEFT
);
1998 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1999 if (intelBuffer
== NULL
)
2002 /* The front and back buffers are color buffers, which are X tiled. */
2003 uint32_t tiling
= I915_TILING_X
;
2004 unsigned long pitch
;
2005 int cpp
= format
/ 8;
2006 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
2007 "intelAllocateBuffer",
2012 BO_ALLOC_FOR_RENDER
);
2014 if (intelBuffer
->bo
== NULL
) {
2019 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2021 intelBuffer
->base
.attachment
= attachment
;
2022 intelBuffer
->base
.cpp
= cpp
;
2023 intelBuffer
->base
.pitch
= pitch
;
2025 return &intelBuffer
->base
;
2029 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2031 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2033 drm_intel_bo_unreference(intelBuffer
->bo
);
2037 static const struct __DriverAPIRec brw_driver_api
= {
2038 .InitScreen
= intelInitScreen2
,
2039 .DestroyScreen
= intelDestroyScreen
,
2040 .CreateContext
= brwCreateContext
,
2041 .DestroyContext
= intelDestroyContext
,
2042 .CreateBuffer
= intelCreateBuffer
,
2043 .DestroyBuffer
= intelDestroyBuffer
,
2044 .MakeCurrent
= intelMakeCurrent
,
2045 .UnbindContext
= intelUnbindContext
,
2046 .AllocateBuffer
= intelAllocateBuffer
,
2047 .ReleaseBuffer
= intelReleaseBuffer
2050 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2051 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2052 .vtable
= &brw_driver_api
,
2055 static const __DRIextension
*brw_driver_extensions
[] = {
2056 &driCoreExtension
.base
,
2057 &driImageDriverExtension
.base
,
2058 &driDRI2Extension
.base
,
2060 &brw_config_options
.base
,
2064 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2066 globalDriverAPI
= &brw_driver_api
;
2068 return brw_driver_extensions
;