2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_MISCELLANEOUS
93 DRI_CONF_GLSL_ZERO_INIT("false")
98 #include "intel_batchbuffer.h"
99 #include "intel_buffers.h"
100 #include "intel_bufmgr.h"
101 #include "intel_fbo.h"
102 #include "intel_mipmap_tree.h"
103 #include "intel_screen.h"
104 #include "intel_tex.h"
105 #include "intel_image.h"
107 #include "brw_context.h"
109 #include "i915_drm.h"
112 * For debugging purposes, this returns a time in seconds.
119 clock_gettime(CLOCK_MONOTONIC
, &tp
);
121 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
125 aub_dump_bmp(struct gl_context
*ctx
)
127 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
129 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
130 struct intel_renderbuffer
*irb
=
131 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
133 if (irb
&& irb
->mt
) {
134 enum aub_dump_bmp_format format
;
136 switch (irb
->Base
.Base
.Format
) {
137 case MESA_FORMAT_B8G8R8A8_UNORM
:
138 case MESA_FORMAT_B8G8R8X8_UNORM
:
139 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
145 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
148 irb
->Base
.Base
.Width
,
149 irb
->Base
.Base
.Height
,
157 static const __DRItexBufferExtension intelTexBufferExtension
= {
158 .base
= { __DRI_TEX_BUFFER
, 3 },
160 .setTexBuffer
= intelSetTexBuffer
,
161 .setTexBuffer2
= intelSetTexBuffer2
,
162 .releaseTexBuffer
= NULL
,
166 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
167 __DRIdrawable
*dPriv
,
169 enum __DRI2throttleReason reason
)
171 struct brw_context
*brw
= cPriv
->driverPrivate
;
176 struct gl_context
*ctx
= &brw
->ctx
;
178 FLUSH_VERTICES(ctx
, 0);
180 if (flags
& __DRI2_FLUSH_DRAWABLE
)
181 intel_resolve_for_dri2_flush(brw
, dPriv
);
183 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
184 brw
->need_swap_throttle
= true;
185 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
186 brw
->need_flush_throttle
= true;
188 intel_batchbuffer_flush(brw
);
190 if (INTEL_DEBUG
& DEBUG_AUB
) {
196 * Provides compatibility with loaders that only support the older (version
197 * 1-3) flush interface.
199 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
202 intel_dri2_flush(__DRIdrawable
*drawable
)
204 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
205 __DRI2_FLUSH_DRAWABLE
,
206 __DRI2_THROTTLE_SWAPBUFFER
);
209 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
210 .base
= { __DRI2_FLUSH
, 4 },
212 .flush
= intel_dri2_flush
,
213 .invalidate
= dri2InvalidateDrawable
,
214 .flush_with_flags
= intel_dri2_flush_with_flags
,
217 static struct intel_image_format intel_image_formats
[] = {
218 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
221 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
224 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
227 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
230 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
233 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
236 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
239 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
242 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
245 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
248 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
251 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
271 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
276 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
281 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
286 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
289 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
291 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
292 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
293 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
294 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
296 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
297 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
298 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
299 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
301 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
302 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
303 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
305 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
306 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
307 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
309 /* For YUYV buffers, we set up two overlapping DRI images and treat
310 * them as planar buffers in the compositors. Plane 0 is GR88 and
311 * samples YU or YV pairs and places Y into the R component, while
312 * plane 1 is ARGB and samples YUYV clusters and places pairs and
313 * places U into the G component and V into A. This lets the
314 * texture sampler interpolate the Y components correctly when
315 * sampling from plane 0, and interpolate U and V correctly when
316 * sampling from plane 1. */
317 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
318 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
319 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
323 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
325 uint32_t tiling
, swizzle
;
326 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
328 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
329 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
330 func
, image
->offset
);
334 static struct intel_image_format
*
335 intel_image_format_lookup(int fourcc
)
337 struct intel_image_format
*f
= NULL
;
339 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
340 if (intel_image_formats
[i
].fourcc
== fourcc
) {
341 f
= &intel_image_formats
[i
];
349 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
351 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
352 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
353 *fourcc
= intel_image_formats
[i
].fourcc
;
361 intel_allocate_image(int dri_format
, void *loaderPrivate
)
365 image
= calloc(1, sizeof *image
);
369 image
->dri_format
= dri_format
;
372 image
->format
= driImageFormatToGLFormat(dri_format
);
373 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
374 image
->format
== MESA_FORMAT_NONE
) {
379 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
380 image
->data
= loaderPrivate
;
386 * Sets up a DRIImage structure to point to a slice out of a miptree.
389 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
390 struct intel_mipmap_tree
*mt
, GLuint level
,
393 intel_miptree_make_shareable(brw
, mt
);
395 intel_miptree_check_level_layer(mt
, level
, zoffset
);
397 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
398 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
399 image
->pitch
= mt
->pitch
;
401 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
405 drm_intel_bo_unreference(image
->bo
);
407 drm_intel_bo_reference(mt
->bo
);
411 intel_create_image_from_name(__DRIscreen
*dri_screen
,
412 int width
, int height
, int format
,
413 int name
, int pitch
, void *loaderPrivate
)
415 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
419 image
= intel_allocate_image(format
, loaderPrivate
);
423 if (image
->format
== MESA_FORMAT_NONE
)
426 cpp
= _mesa_get_format_bytes(image
->format
);
428 image
->width
= width
;
429 image
->height
= height
;
430 image
->pitch
= pitch
* cpp
;
431 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
442 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
443 int renderbuffer
, void *loaderPrivate
)
446 struct brw_context
*brw
= context
->driverPrivate
;
447 struct gl_context
*ctx
= &brw
->ctx
;
448 struct gl_renderbuffer
*rb
;
449 struct intel_renderbuffer
*irb
;
451 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
453 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
457 irb
= intel_renderbuffer(rb
);
458 intel_miptree_make_shareable(brw
, irb
->mt
);
459 image
= calloc(1, sizeof *image
);
463 image
->internal_format
= rb
->InternalFormat
;
464 image
->format
= rb
->Format
;
466 image
->data
= loaderPrivate
;
467 drm_intel_bo_unreference(image
->bo
);
468 image
->bo
= irb
->mt
->bo
;
469 drm_intel_bo_reference(irb
->mt
->bo
);
470 image
->width
= rb
->Width
;
471 image
->height
= rb
->Height
;
472 image
->pitch
= irb
->mt
->pitch
;
473 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
474 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
476 rb
->NeedsFinishRenderTexture
= true;
481 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
482 unsigned texture
, int zoffset
,
488 struct brw_context
*brw
= context
->driverPrivate
;
489 struct gl_texture_object
*obj
;
490 struct intel_texture_object
*iobj
;
493 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
494 if (!obj
|| obj
->Target
!= target
) {
495 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
499 if (target
== GL_TEXTURE_CUBE_MAP
)
502 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
503 iobj
= intel_texture_object(obj
);
504 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
505 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
509 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
510 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
514 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
515 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
518 image
= calloc(1, sizeof *image
);
520 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
524 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
525 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
526 image
->data
= loaderPrivate
;
527 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
528 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
529 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
530 if (image
->dri_format
== MESA_FORMAT_NONE
) {
531 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
536 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
541 intel_destroy_image(__DRIimage
*image
)
543 drm_intel_bo_unreference(image
->bo
);
548 intel_create_image(__DRIscreen
*dri_screen
,
549 int width
, int height
, int format
,
554 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
559 tiling
= I915_TILING_X
;
560 if (use
& __DRI_IMAGE_USE_CURSOR
) {
561 if (width
!= 64 || height
!= 64)
563 tiling
= I915_TILING_NONE
;
566 if (use
& __DRI_IMAGE_USE_LINEAR
)
567 tiling
= I915_TILING_NONE
;
569 image
= intel_allocate_image(format
, loaderPrivate
);
573 cpp
= _mesa_get_format_bytes(image
->format
);
574 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
575 width
, height
, cpp
, &tiling
,
577 if (image
->bo
== NULL
) {
581 image
->width
= width
;
582 image
->height
= height
;
583 image
->pitch
= pitch
;
589 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
592 case __DRI_IMAGE_ATTRIB_STRIDE
:
593 *value
= image
->pitch
;
595 case __DRI_IMAGE_ATTRIB_HANDLE
:
596 *value
= image
->bo
->handle
;
598 case __DRI_IMAGE_ATTRIB_NAME
:
599 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
600 case __DRI_IMAGE_ATTRIB_FORMAT
:
601 *value
= image
->dri_format
;
603 case __DRI_IMAGE_ATTRIB_WIDTH
:
604 *value
= image
->width
;
606 case __DRI_IMAGE_ATTRIB_HEIGHT
:
607 *value
= image
->height
;
609 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
610 if (image
->planar_format
== NULL
)
612 *value
= image
->planar_format
->components
;
614 case __DRI_IMAGE_ATTRIB_FD
:
615 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
616 case __DRI_IMAGE_ATTRIB_FOURCC
:
617 return intel_lookup_fourcc(image
->dri_format
, value
);
618 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
621 case __DRI_IMAGE_ATTRIB_OFFSET
:
622 *value
= image
->offset
;
631 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
635 image
= calloc(1, sizeof *image
);
639 drm_intel_bo_reference(orig_image
->bo
);
640 image
->bo
= orig_image
->bo
;
641 image
->internal_format
= orig_image
->internal_format
;
642 image
->planar_format
= orig_image
->planar_format
;
643 image
->dri_format
= orig_image
->dri_format
;
644 image
->format
= orig_image
->format
;
645 image
->offset
= orig_image
->offset
;
646 image
->width
= orig_image
->width
;
647 image
->height
= orig_image
->height
;
648 image
->pitch
= orig_image
->pitch
;
649 image
->tile_x
= orig_image
->tile_x
;
650 image
->tile_y
= orig_image
->tile_y
;
651 image
->has_depthstencil
= orig_image
->has_depthstencil
;
652 image
->data
= loaderPrivate
;
654 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
655 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
661 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
663 if (use
& __DRI_IMAGE_USE_CURSOR
) {
664 if (image
->width
!= 64 || image
->height
!= 64)
672 intel_create_image_from_names(__DRIscreen
*dri_screen
,
673 int width
, int height
, int fourcc
,
674 int *names
, int num_names
,
675 int *strides
, int *offsets
,
678 struct intel_image_format
*f
= NULL
;
682 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
685 f
= intel_image_format_lookup(fourcc
);
689 image
= intel_create_image_from_name(dri_screen
, width
, height
,
690 __DRI_IMAGE_FORMAT_NONE
,
691 names
[0], strides
[0],
697 image
->planar_format
= f
;
698 for (i
= 0; i
< f
->nplanes
; i
++) {
699 index
= f
->planes
[i
].buffer_index
;
700 image
->offsets
[index
] = offsets
[index
];
701 image
->strides
[index
] = strides
[index
];
708 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
709 int width
, int height
, int fourcc
,
710 int *fds
, int num_fds
, int *strides
, int *offsets
,
713 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
714 struct intel_image_format
*f
;
718 if (fds
== NULL
|| num_fds
< 1)
721 /* We only support all planes from the same bo */
722 for (i
= 0; i
< num_fds
; i
++)
723 if (fds
[0] != fds
[i
])
726 f
= intel_image_format_lookup(fourcc
);
731 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
733 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
738 image
->width
= width
;
739 image
->height
= height
;
740 image
->pitch
= strides
[0];
742 image
->planar_format
= f
;
744 for (i
= 0; i
< f
->nplanes
; i
++) {
745 index
= f
->planes
[i
].buffer_index
;
746 image
->offsets
[index
] = offsets
[index
];
747 image
->strides
[index
] = strides
[index
];
749 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
750 const int end
= offsets
[index
] + plane_height
* strides
[index
];
755 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
757 if (image
->bo
== NULL
) {
762 if (f
->nplanes
== 1) {
763 image
->offset
= image
->offsets
[0];
764 intel_image_warn_if_unaligned(image
, __func__
);
771 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
772 int width
, int height
, int fourcc
,
773 int *fds
, int num_fds
,
774 int *strides
, int *offsets
,
775 enum __DRIYUVColorSpace yuv_color_space
,
776 enum __DRISampleRange sample_range
,
777 enum __DRIChromaSiting horizontal_siting
,
778 enum __DRIChromaSiting vertical_siting
,
783 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
786 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
790 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
791 num_fds
, strides
, offsets
,
795 * Invalid parameters and any inconsistencies between are assumed to be
796 * checked by the caller. Therefore besides unsupported formats one can fail
797 * only in allocation.
800 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
804 image
->dma_buf_imported
= true;
805 image
->yuv_color_space
= yuv_color_space
;
806 image
->sample_range
= sample_range
;
807 image
->horizontal_siting
= horizontal_siting
;
808 image
->vertical_siting
= vertical_siting
;
810 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
815 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
817 int width
, height
, offset
, stride
, dri_format
, index
;
818 struct intel_image_format
*f
;
821 if (parent
== NULL
|| parent
->planar_format
== NULL
)
824 f
= parent
->planar_format
;
826 if (plane
>= f
->nplanes
)
829 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
830 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
831 dri_format
= f
->planes
[plane
].dri_format
;
832 index
= f
->planes
[plane
].buffer_index
;
833 offset
= parent
->offsets
[index
];
834 stride
= parent
->strides
[index
];
836 image
= intel_allocate_image(dri_format
, loaderPrivate
);
840 if (offset
+ height
* stride
> parent
->bo
->size
) {
841 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
846 image
->bo
= parent
->bo
;
847 drm_intel_bo_reference(parent
->bo
);
849 image
->width
= width
;
850 image
->height
= height
;
851 image
->pitch
= stride
;
852 image
->offset
= offset
;
854 intel_image_warn_if_unaligned(image
, __func__
);
859 static const __DRIimageExtension intelImageExtension
= {
860 .base
= { __DRI_IMAGE
, 13 },
862 .createImageFromName
= intel_create_image_from_name
,
863 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
864 .destroyImage
= intel_destroy_image
,
865 .createImage
= intel_create_image
,
866 .queryImage
= intel_query_image
,
867 .dupImage
= intel_dup_image
,
868 .validateUsage
= intel_validate_usage
,
869 .createImageFromNames
= intel_create_image_from_names
,
870 .fromPlanar
= intel_from_planar
,
871 .createImageFromTexture
= intel_create_image_from_texture
,
872 .createImageFromFds
= intel_create_image_from_fds
,
873 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
875 .getCapabilities
= NULL
,
881 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
882 int param
, unsigned int *value
)
884 const struct intel_screen
*const screen
=
885 (struct intel_screen
*) dri_screen
->driverPrivate
;
888 case __DRI2_RENDERER_VENDOR_ID
:
891 case __DRI2_RENDERER_DEVICE_ID
:
892 value
[0] = screen
->deviceID
;
894 case __DRI2_RENDERER_ACCELERATED
:
897 case __DRI2_RENDERER_VIDEO_MEMORY
: {
898 /* Once a batch uses more than 75% of the maximum mappable size, we
899 * assume that there's some fragmentation, and we start doing extra
900 * flushing, etc. That's the big cliff apps will care about.
903 size_t mappable_size
;
905 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
907 const unsigned gpu_mappable_megabytes
=
908 (aper_size
/ (1024 * 1024)) * 3 / 4;
910 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
911 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
913 if (system_memory_pages
<= 0 || system_page_size
<= 0)
916 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
917 * (uint64_t) system_page_size
;
919 const unsigned system_memory_megabytes
=
920 (unsigned) (system_memory_bytes
/ (1024 * 1024));
922 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
925 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
928 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
932 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
939 brw_query_renderer_string(__DRIscreen
*dri_screen
,
940 int param
, const char **value
)
942 const struct intel_screen
*screen
=
943 (struct intel_screen
*) dri_screen
->driverPrivate
;
946 case __DRI2_RENDERER_VENDOR_ID
:
947 value
[0] = brw_vendor_string
;
949 case __DRI2_RENDERER_DEVICE_ID
:
950 value
[0] = brw_get_renderer_string(screen
);
959 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
960 .base
= { __DRI2_RENDERER_QUERY
, 1 },
962 .queryInteger
= brw_query_renderer_integer
,
963 .queryString
= brw_query_renderer_string
966 static const __DRIrobustnessExtension dri2Robustness
= {
967 .base
= { __DRI2_ROBUSTNESS
, 1 }
970 static const __DRIextension
*screenExtensions
[] = {
971 &intelTexBufferExtension
.base
,
972 &intelFenceExtension
.base
,
973 &intelFlushExtension
.base
,
974 &intelImageExtension
.base
,
975 &intelRendererQueryExtension
.base
,
976 &dri2ConfigQueryExtension
.base
,
980 static const __DRIextension
*intelRobustScreenExtensions
[] = {
981 &intelTexBufferExtension
.base
,
982 &intelFenceExtension
.base
,
983 &intelFlushExtension
.base
,
984 &intelImageExtension
.base
,
985 &intelRendererQueryExtension
.base
,
986 &dri2ConfigQueryExtension
.base
,
987 &dri2Robustness
.base
,
992 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
995 struct drm_i915_getparam gp
;
997 memset(&gp
, 0, sizeof(gp
));
1001 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1004 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1011 intel_get_boolean(struct intel_screen
*screen
, int param
)
1014 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1018 intel_get_integer(struct intel_screen
*screen
, int param
)
1022 if (intel_get_param(screen
, param
, &value
) == 0)
1029 intelDestroyScreen(__DRIscreen
* sPriv
)
1031 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1033 dri_bufmgr_destroy(screen
->bufmgr
);
1034 driDestroyOptionInfo(&screen
->optionCache
);
1036 ralloc_free(screen
);
1037 sPriv
->driverPrivate
= NULL
;
1042 * This is called when we need to set up GL rendering to a new X window.
1045 intelCreateBuffer(__DRIscreen
*dri_screen
,
1046 __DRIdrawable
* driDrawPriv
,
1047 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1049 struct intel_renderbuffer
*rb
;
1050 struct intel_screen
*screen
= (struct intel_screen
*)
1051 dri_screen
->driverPrivate
;
1052 mesa_format rgbFormat
;
1053 unsigned num_samples
=
1054 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1055 struct gl_framebuffer
*fb
;
1060 fb
= CALLOC_STRUCT(gl_framebuffer
);
1064 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1066 if (screen
->winsys_msaa_samples_override
!= -1) {
1067 num_samples
= screen
->winsys_msaa_samples_override
;
1068 fb
->Visual
.samples
= num_samples
;
1071 if (mesaVis
->redBits
== 5) {
1072 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1073 : MESA_FORMAT_B5G6R5_UNORM
;
1074 } else if (mesaVis
->sRGBCapable
) {
1075 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1076 : MESA_FORMAT_B8G8R8A8_SRGB
;
1077 } else if (mesaVis
->alphaBits
== 0) {
1078 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1079 : MESA_FORMAT_B8G8R8X8_UNORM
;
1081 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1082 : MESA_FORMAT_B8G8R8A8_SRGB
;
1083 fb
->Visual
.sRGBCapable
= true;
1086 /* setup the hardware-based renderbuffers */
1087 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1088 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1090 if (mesaVis
->doubleBufferMode
) {
1091 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1092 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1096 * Assert here that the gl_config has an expected depth/stencil bit
1097 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1098 * which constructs the advertised configs.)
1100 if (mesaVis
->depthBits
== 24) {
1101 assert(mesaVis
->stencilBits
== 8);
1103 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1104 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1106 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1107 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1109 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1112 * Use combined depth/stencil. Note that the renderbuffer is
1113 * attached to two attachment points.
1115 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1117 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1118 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1121 else if (mesaVis
->depthBits
== 16) {
1122 assert(mesaVis
->stencilBits
== 0);
1123 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1125 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1128 assert(mesaVis
->depthBits
== 0);
1129 assert(mesaVis
->stencilBits
== 0);
1132 /* now add any/all software-based renderbuffers we may need */
1133 _swrast_add_soft_renderbuffers(fb
,
1134 false, /* never sw color */
1135 false, /* never sw depth */
1136 false, /* never sw stencil */
1137 mesaVis
->accumRedBits
> 0,
1138 false, /* never sw alpha */
1139 false /* never sw aux */ );
1140 driDrawPriv
->driverPrivate
= fb
;
1146 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1148 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1150 _mesa_reference_framebuffer(&fb
, NULL
);
1154 intel_detect_sseu(struct intel_screen
*screen
)
1156 assert(screen
->devinfo
.gen
>= 8);
1159 screen
->subslice_total
= -1;
1160 screen
->eu_total
= -1;
1162 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1163 &screen
->subslice_total
);
1164 if (ret
< 0 && ret
!= -EINVAL
)
1167 ret
= intel_get_param(screen
,
1168 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1169 if (ret
< 0 && ret
!= -EINVAL
)
1172 /* Without this information, we cannot get the right Braswell brandstrings,
1173 * and we have to use conservative numbers for GPGPU on many platforms, but
1174 * otherwise, things will just work.
1176 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1178 "Kernel 4.1 required to properly query GPU properties.\n");
1183 screen
->subslice_total
= -1;
1184 screen
->eu_total
= -1;
1185 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1189 intel_init_bufmgr(struct intel_screen
*screen
)
1191 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1193 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1195 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1196 if (screen
->bufmgr
== NULL
) {
1197 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1198 __func__
, __LINE__
);
1202 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1204 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1205 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1213 intel_detect_swizzling(struct intel_screen
*screen
)
1215 drm_intel_bo
*buffer
;
1216 unsigned long flags
= 0;
1217 unsigned long aligned_pitch
;
1218 uint32_t tiling
= I915_TILING_X
;
1219 uint32_t swizzle_mode
= 0;
1221 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1223 &tiling
, &aligned_pitch
, flags
);
1227 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1228 drm_intel_bo_unreference(buffer
);
1230 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1237 intel_detect_timestamp(struct intel_screen
*screen
)
1239 uint64_t dummy
= 0, last
= 0;
1240 int upper
, lower
, loops
;
1242 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1243 * TIMESTAMP register being shifted and the low 32bits always zero.
1245 * More recent kernels offer an interface to read the full 36bits
1248 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1251 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1252 * upper 32bits for a rapidly changing timestamp.
1254 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1258 for (loops
= 0; loops
< 10; loops
++) {
1259 /* The TIMESTAMP should change every 80ns, so several round trips
1260 * through the kernel should be enough to advance it.
1262 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1265 upper
+= (dummy
>> 32) != (last
>> 32);
1266 if (upper
> 1) /* beware 32bit counter overflow */
1267 return 2; /* upper dword holds the low 32bits of the timestamp */
1269 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1271 return 1; /* timestamp is unshifted */
1276 /* No advancement? No timestamp! */
1281 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1283 * Some combinations of hardware and kernel versions allow this feature,
1284 * while others don't. Instead of trying to enumerate every case, just
1285 * try and write a register and see if works.
1288 intel_detect_pipelined_register(struct intel_screen
*screen
,
1289 int reg
, uint32_t expected_value
, bool reset
)
1291 drm_intel_bo
*results
, *bo
;
1293 uint32_t offset
= 0;
1294 bool success
= false;
1296 /* Create a zero'ed temporary buffer for reading our results */
1297 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1298 if (results
== NULL
)
1301 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1305 if (drm_intel_bo_map(bo
, 1))
1308 batch
= bo
->virtual;
1310 /* Write the register. */
1311 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1313 *batch
++ = expected_value
;
1315 /* Save the register's value back to the buffer. */
1316 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1318 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1319 results
, offset
*sizeof(uint32_t),
1320 I915_GEM_DOMAIN_INSTRUCTION
,
1321 I915_GEM_DOMAIN_INSTRUCTION
);
1322 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1324 /* And afterwards clear the register */
1326 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1331 *batch
++ = MI_BATCH_BUFFER_END
;
1333 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1337 /* Check whether the value got written. */
1338 if (drm_intel_bo_map(results
, false) == 0) {
1339 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1340 drm_intel_bo_unmap(results
);
1344 drm_intel_bo_unreference(bo
);
1346 drm_intel_bo_unreference(results
);
1352 intel_detect_pipelined_so(struct intel_screen
*screen
)
1354 /* Supposedly, Broadwell just works. */
1355 if (screen
->devinfo
.gen
>= 8)
1358 if (screen
->devinfo
.gen
<= 6)
1361 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1362 * statistics registers), and we already reset it to zero before using it.
1364 return intel_detect_pipelined_register(screen
,
1365 GEN7_SO_WRITE_OFFSET(0),
1371 * Return array of MSAA modes supported by the hardware. The array is
1372 * zero-terminated and sorted in decreasing order.
1375 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1377 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1378 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1379 static const int gen7_modes
[] = {8, 4, 0, -1};
1380 static const int gen6_modes
[] = {4, 0, -1};
1381 static const int gen4_modes
[] = {0, -1};
1383 if (screen
->devinfo
.gen
>= 9) {
1385 } else if (screen
->devinfo
.gen
>= 8) {
1387 } else if (screen
->devinfo
.gen
>= 7) {
1389 } else if (screen
->devinfo
.gen
== 6) {
1396 static __DRIconfig
**
1397 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1399 static const mesa_format formats
[] = {
1400 MESA_FORMAT_B5G6R5_UNORM
,
1401 MESA_FORMAT_B8G8R8A8_UNORM
,
1402 MESA_FORMAT_B8G8R8X8_UNORM
1405 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1406 static const GLenum back_buffer_modes
[] = {
1407 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1410 static const uint8_t singlesample_samples
[1] = {0};
1411 static const uint8_t multisample_samples
[2] = {4, 8};
1413 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1414 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1415 uint8_t depth_bits
[4], stencil_bits
[4];
1416 __DRIconfig
**configs
= NULL
;
1418 /* Generate singlesample configs without accumulation buffer. */
1419 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1420 __DRIconfig
**new_configs
;
1421 int num_depth_stencil_bits
= 2;
1423 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1424 * buffer that has a different number of bits per pixel than the color
1425 * buffer, gen >= 6 supports this.
1428 stencil_bits
[0] = 0;
1430 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1432 stencil_bits
[1] = 0;
1433 if (devinfo
->gen
>= 6) {
1435 stencil_bits
[2] = 8;
1436 num_depth_stencil_bits
= 3;
1440 stencil_bits
[1] = 8;
1443 new_configs
= driCreateConfigs(formats
[i
],
1446 num_depth_stencil_bits
,
1447 back_buffer_modes
, 2,
1448 singlesample_samples
, 1,
1450 configs
= driConcatConfigs(configs
, new_configs
);
1453 /* Generate the minimum possible set of configs that include an
1454 * accumulation buffer.
1456 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1457 __DRIconfig
**new_configs
;
1459 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1461 stencil_bits
[0] = 0;
1464 stencil_bits
[0] = 8;
1467 new_configs
= driCreateConfigs(formats
[i
],
1468 depth_bits
, stencil_bits
, 1,
1469 back_buffer_modes
, 1,
1470 singlesample_samples
, 1,
1472 configs
= driConcatConfigs(configs
, new_configs
);
1475 /* Generate multisample configs.
1477 * This loop breaks early, and hence is a no-op, on gen < 6.
1479 * Multisample configs must follow the singlesample configs in order to
1480 * work around an X server bug present in 1.12. The X server chooses to
1481 * associate the first listed RGBA888-Z24S8 config, regardless of its
1482 * sample count, with the 32-bit depth visual used for compositing.
1484 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1485 * supported. Singlebuffer configs are not supported because no one wants
1488 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1489 if (devinfo
->gen
< 6)
1492 __DRIconfig
**new_configs
;
1493 const int num_depth_stencil_bits
= 2;
1494 int num_msaa_modes
= 0;
1497 stencil_bits
[0] = 0;
1499 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1501 stencil_bits
[1] = 0;
1504 stencil_bits
[1] = 8;
1507 if (devinfo
->gen
>= 7)
1509 else if (devinfo
->gen
== 6)
1512 new_configs
= driCreateConfigs(formats
[i
],
1515 num_depth_stencil_bits
,
1516 back_buffer_modes
, 1,
1517 multisample_samples
,
1520 configs
= driConcatConfigs(configs
, new_configs
);
1523 if (configs
== NULL
) {
1524 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1533 set_max_gl_versions(struct intel_screen
*screen
)
1535 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1536 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1538 switch (screen
->devinfo
.gen
) {
1541 dri_screen
->max_gl_core_version
= 45;
1542 dri_screen
->max_gl_compat_version
= 30;
1543 dri_screen
->max_gl_es1_version
= 11;
1544 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1547 dri_screen
->max_gl_core_version
= screen
->devinfo
.is_haswell
&&
1548 can_do_pipelined_register_writes(screen
) ? 45 : 33;
1549 dri_screen
->max_gl_compat_version
= 30;
1550 dri_screen
->max_gl_es1_version
= 11;
1551 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1554 dri_screen
->max_gl_core_version
= 33;
1555 dri_screen
->max_gl_compat_version
= 30;
1556 dri_screen
->max_gl_es1_version
= 11;
1557 dri_screen
->max_gl_es2_version
= 30;
1561 dri_screen
->max_gl_core_version
= 0;
1562 dri_screen
->max_gl_compat_version
= 21;
1563 dri_screen
->max_gl_es1_version
= 11;
1564 dri_screen
->max_gl_es2_version
= 20;
1567 unreachable("unrecognized intel_screen::gen");
1572 * Return the revision (generally the revid field of the PCI header) of the
1575 * XXX: This function is useful to keep around even if it is not currently in
1576 * use. It is necessary for new platforms and revision specific workarounds or
1577 * features. Please don't remove it so that we know it at least continues to
1580 static __attribute__((__unused__
)) int
1581 brw_get_revision(int fd
)
1583 struct drm_i915_getparam gp
;
1587 memset(&gp
, 0, sizeof(gp
));
1588 gp
.param
= I915_PARAM_REVISION
;
1589 gp
.value
= &revision
;
1591 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1598 /* Drop when RS headers get pulled to libdrm */
1599 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1600 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1604 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1606 struct brw_context
*brw
= (struct brw_context
*)data
;
1609 va_start(args
, fmt
);
1611 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1612 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1613 MESA_DEBUG_TYPE_OTHER
,
1614 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1619 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1621 struct brw_context
*brw
= (struct brw_context
*)data
;
1624 va_start(args
, fmt
);
1626 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1628 va_copy(args_copy
, args
);
1629 vfprintf(stderr
, fmt
, args_copy
);
1633 if (brw
->perf_debug
) {
1635 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1636 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1637 MESA_DEBUG_TYPE_PERFORMANCE
,
1638 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1644 * This is the driver specific part of the createNewScreen entry point.
1645 * Called when using DRI2.
1647 * \return the struct gl_config supported by this driver
1650 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1652 struct intel_screen
*screen
;
1654 if (dri_screen
->image
.loader
) {
1655 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1656 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1658 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1659 "support required\n");
1663 /* Allocate the private area */
1664 screen
= rzalloc(NULL
, struct intel_screen
);
1666 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1669 /* parse information in __driConfigOptions */
1670 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1672 screen
->driScrnPriv
= dri_screen
;
1673 dri_screen
->driverPrivate
= (void *) screen
;
1675 if (!intel_init_bufmgr(screen
))
1678 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1679 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1682 brw_process_intel_debug_variable();
1684 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1685 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1687 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && screen
->devinfo
.gen
< 7) {
1689 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1690 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1693 if (INTEL_DEBUG
& DEBUG_AUB
)
1694 drm_intel_bufmgr_gem_set_aub_dump(screen
->bufmgr
, true);
1696 #ifndef I915_PARAM_MMAP_GTT_VERSION
1697 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
1699 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1700 /* Theorectically unlimited! At least for individual objects...
1702 * Currently the entire (global) address space for all GTT maps is
1703 * limited to 64bits. That is all objects on the system that are
1704 * setup for GTT mmapping must fit within 64bits. An attempt to use
1705 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1707 * Long before we hit that limit, we will be practically limited by
1708 * that any single object must fit in physical memory (RAM). The upper
1709 * limit on the CPU's address space is currently 48bits (Skylake), of
1710 * which only 39bits can be physical memory. (The GPU itself also has
1711 * a 48bit addressable virtual space.) We can fit over 32 million
1712 * objects of the current maximum allocable size before running out
1715 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1717 /* Estimate the size of the mappable aperture into the GTT. There's an
1718 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1719 * It turns out it's basically always 256MB, though some ancient hardware
1722 uint32_t gtt_size
= 256 * 1024 * 1024;
1724 /* We don't want to map two objects such that a memcpy between them would
1725 * just fault one mapping in and then the other over and over forever. So
1726 * we would need to divide the GTT size by 2. Additionally, some GTT is
1727 * taken up by things like the framebuffer and the ringbuffer and such, so
1728 * be more conservative.
1730 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1733 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1734 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1736 /* GENs prior to 8 do not support EU/Subslice info */
1737 if (screen
->devinfo
.gen
>= 8) {
1738 intel_detect_sseu(screen
);
1739 } else if (screen
->devinfo
.gen
== 7) {
1740 screen
->subslice_total
= 1 << (screen
->devinfo
.gt
- 1);
1743 if (intel_detect_pipelined_so(screen
))
1744 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1746 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1748 screen
->winsys_msaa_samples_override
=
1749 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1750 printf("Forcing winsys sample count to %d\n",
1751 screen
->winsys_msaa_samples_override
);
1753 screen
->winsys_msaa_samples_override
= -1;
1756 set_max_gl_versions(screen
);
1758 /* Notification of GPU resets requires hardware contexts and a kernel new
1759 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1760 * supported, calling it with a context of 0 will either generate EPERM or
1761 * no error. If the ioctl is not supported, it always generate EINVAL.
1762 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1763 * extension to the loader.
1765 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1767 if (screen
->devinfo
.gen
>= 6) {
1768 struct drm_i915_reset_stats stats
;
1769 memset(&stats
, 0, sizeof(stats
));
1771 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1773 screen
->has_context_reset_notification
=
1774 (ret
!= -1 || errno
!= EINVAL
);
1777 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1778 &screen
->cmd_parser_version
) < 0) {
1779 screen
->cmd_parser_version
= 0;
1782 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 2)
1783 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1785 /* Haswell requires command parser version 4 in order to have L3
1786 * atomic scratch1 and chicken3 bits
1788 if (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 4) {
1789 screen
->kernel_features
|=
1790 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1793 /* Haswell requires command parser version 6 in order to write to the
1794 * MI_MATH GPR registers, and version 7 in order to use
1795 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1797 if (screen
->devinfo
.gen
>= 8 ||
1798 (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1799 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1802 /* Gen7 needs at least command parser version 5 to support compute */
1803 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 5)
1804 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1806 dri_screen
->extensions
= !screen
->has_context_reset_notification
1807 ? screenExtensions
: intelRobustScreenExtensions
;
1809 screen
->compiler
= brw_compiler_create(screen
,
1811 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1812 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1813 screen
->program_id
= 1;
1815 if (screen
->devinfo
.has_resource_streamer
) {
1816 screen
->has_resource_streamer
=
1817 intel_get_boolean(screen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1820 screen
->has_exec_fence
=
1821 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
1823 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1826 struct intel_buffer
{
1831 static __DRIbuffer
*
1832 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1833 unsigned attachment
, unsigned format
,
1834 int width
, int height
)
1836 struct intel_buffer
*intelBuffer
;
1837 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1839 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1840 attachment
== __DRI_BUFFER_BACK_LEFT
);
1842 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1843 if (intelBuffer
== NULL
)
1846 /* The front and back buffers are color buffers, which are X tiled. */
1847 uint32_t tiling
= I915_TILING_X
;
1848 unsigned long pitch
;
1849 int cpp
= format
/ 8;
1850 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
1851 "intelAllocateBuffer",
1856 BO_ALLOC_FOR_RENDER
);
1858 if (intelBuffer
->bo
== NULL
) {
1863 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1865 intelBuffer
->base
.attachment
= attachment
;
1866 intelBuffer
->base
.cpp
= cpp
;
1867 intelBuffer
->base
.pitch
= pitch
;
1869 return &intelBuffer
->base
;
1873 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
1875 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1877 drm_intel_bo_unreference(intelBuffer
->bo
);
1881 static const struct __DriverAPIRec brw_driver_api
= {
1882 .InitScreen
= intelInitScreen2
,
1883 .DestroyScreen
= intelDestroyScreen
,
1884 .CreateContext
= brwCreateContext
,
1885 .DestroyContext
= intelDestroyContext
,
1886 .CreateBuffer
= intelCreateBuffer
,
1887 .DestroyBuffer
= intelDestroyBuffer
,
1888 .MakeCurrent
= intelMakeCurrent
,
1889 .UnbindContext
= intelUnbindContext
,
1890 .AllocateBuffer
= intelAllocateBuffer
,
1891 .ReleaseBuffer
= intelReleaseBuffer
1894 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1895 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1896 .vtable
= &brw_driver_api
,
1899 static const __DRIextension
*brw_driver_extensions
[] = {
1900 &driCoreExtension
.base
,
1901 &driImageDriverExtension
.base
,
1902 &driDRI2Extension
.base
,
1904 &brw_config_options
.base
,
1908 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1910 globalDriverAPI
= &brw_driver_api
;
1912 return brw_driver_extensions
;