2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
46 #ifndef DRM_FORMAT_MOD_INVALID
47 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
50 #ifndef DRM_FORMAT_MOD_LINEAR
51 #define DRM_FORMAT_MOD_LINEAR 0
54 static const __DRIconfigOptionsExtension brw_config_options
= {
55 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
58 DRI_CONF_SECTION_PERFORMANCE
59 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
60 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
61 * DRI_CONF_BO_REUSE_ALL
63 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
64 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
65 DRI_CONF_ENUM(0, "Disable buffer object reuse")
66 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
71 DRI_CONF_SECTION_QUALITY
72 DRI_CONF_FORCE_S3TC_ENABLE("false")
74 DRI_CONF_PRECISE_TRIG("false")
76 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
77 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
78 "given integer. If negative, then do not clamp.")
82 DRI_CONF_SECTION_DEBUG
83 DRI_CONF_NO_RAST("false")
84 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
85 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
86 DRI_CONF_DISABLE_THROTTLING("false")
87 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
88 DRI_CONF_FORCE_GLSL_VERSION(0)
89 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
90 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
91 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
92 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
93 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
94 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
95 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
97 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
98 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
102 DRI_CONF_SECTION_MISCELLANEOUS
103 DRI_CONF_GLSL_ZERO_INIT("false")
108 #include "intel_batchbuffer.h"
109 #include "intel_buffers.h"
110 #include "brw_bufmgr.h"
111 #include "intel_fbo.h"
112 #include "intel_mipmap_tree.h"
113 #include "intel_screen.h"
114 #include "intel_tex.h"
115 #include "intel_image.h"
117 #include "brw_context.h"
119 #include "i915_drm.h"
122 * For debugging purposes, this returns a time in seconds.
129 clock_gettime(CLOCK_MONOTONIC
, &tp
);
131 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
134 static const __DRItexBufferExtension intelTexBufferExtension
= {
135 .base
= { __DRI_TEX_BUFFER
, 3 },
137 .setTexBuffer
= intelSetTexBuffer
,
138 .setTexBuffer2
= intelSetTexBuffer2
,
139 .releaseTexBuffer
= NULL
,
143 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
144 __DRIdrawable
*dPriv
,
146 enum __DRI2throttleReason reason
)
148 struct brw_context
*brw
= cPriv
->driverPrivate
;
153 struct gl_context
*ctx
= &brw
->ctx
;
155 FLUSH_VERTICES(ctx
, 0);
157 if (flags
& __DRI2_FLUSH_DRAWABLE
)
158 intel_resolve_for_dri2_flush(brw
, dPriv
);
160 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
161 brw
->need_swap_throttle
= true;
162 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
163 brw
->need_flush_throttle
= true;
165 intel_batchbuffer_flush(brw
);
169 * Provides compatibility with loaders that only support the older (version
170 * 1-3) flush interface.
172 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
175 intel_dri2_flush(__DRIdrawable
*drawable
)
177 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
178 __DRI2_FLUSH_DRAWABLE
,
179 __DRI2_THROTTLE_SWAPBUFFER
);
182 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
183 .base
= { __DRI2_FLUSH
, 4 },
185 .flush
= intel_dri2_flush
,
186 .invalidate
= dri2InvalidateDrawable
,
187 .flush_with_flags
= intel_dri2_flush_with_flags
,
190 static struct intel_image_format intel_image_formats
[] = {
191 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
194 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
197 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
200 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
203 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
206 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
209 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
212 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
215 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
218 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
221 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
224 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
227 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
229 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
234 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
239 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
244 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
249 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
269 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
274 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
278 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
279 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
282 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
283 * and treat them as planar buffers in the compositors.
284 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
285 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
286 * clusters and places pairs and places U into the G component and
287 * V into A. This lets the texture sampler interpolate the Y
288 * components correctly when sampling from plane 0, and interpolate
289 * U and V correctly when sampling from plane 1. */
290 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
292 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
293 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
294 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
295 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
298 static const struct {
302 unsigned height_align
;
303 } tiling_modifier_map
[] = {
304 { .tiling
= I915_TILING_NONE
, .modifier
= DRM_FORMAT_MOD_LINEAR
,
305 .since_gen
= 1, .height_align
= 1 },
306 { .tiling
= I915_TILING_X
, .modifier
= I915_FORMAT_MOD_X_TILED
,
307 .since_gen
= 1, .height_align
= 8 },
308 { .tiling
= I915_TILING_Y
, .modifier
= I915_FORMAT_MOD_Y_TILED
,
309 .since_gen
= 6, .height_align
= 32 },
313 modifier_is_supported(uint64_t modifier
)
317 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
318 if (tiling_modifier_map
[i
].modifier
== modifier
)
326 tiling_to_modifier(uint32_t tiling
)
330 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
331 if (tiling_modifier_map
[i
].tiling
== tiling
)
332 return tiling_modifier_map
[i
].modifier
;
335 unreachable("tiling_to_modifier received unknown tiling mode");
339 get_tiled_height(uint64_t modifier
, unsigned height
)
343 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
344 if (tiling_modifier_map
[i
].modifier
== modifier
)
345 return ALIGN(height
, tiling_modifier_map
[i
].height_align
);
348 unreachable("get_tiled_height received unknown tiling mode");
352 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
354 uint32_t tiling
, swizzle
;
355 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
357 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
358 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
359 func
, image
->offset
);
363 static struct intel_image_format
*
364 intel_image_format_lookup(int fourcc
)
366 struct intel_image_format
*f
= NULL
;
368 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
369 if (intel_image_formats
[i
].fourcc
== fourcc
) {
370 f
= &intel_image_formats
[i
];
378 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
380 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
381 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
382 *fourcc
= intel_image_formats
[i
].fourcc
;
390 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
395 image
= calloc(1, sizeof *image
);
399 image
->screen
= screen
;
400 image
->dri_format
= dri_format
;
403 image
->format
= driImageFormatToGLFormat(dri_format
);
404 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
405 image
->format
== MESA_FORMAT_NONE
) {
410 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
411 image
->data
= loaderPrivate
;
417 * Sets up a DRIImage structure to point to a slice out of a miptree.
420 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
421 struct intel_mipmap_tree
*mt
, GLuint level
,
424 intel_miptree_make_shareable(brw
, mt
);
426 intel_miptree_check_level_layer(mt
, level
, zoffset
);
428 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
429 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
430 image
->pitch
= mt
->pitch
;
432 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
436 brw_bo_unreference(image
->bo
);
438 brw_bo_reference(mt
->bo
);
442 intel_create_image_from_name(__DRIscreen
*dri_screen
,
443 int width
, int height
, int format
,
444 int name
, int pitch
, void *loaderPrivate
)
446 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
450 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
454 if (image
->format
== MESA_FORMAT_NONE
)
457 cpp
= _mesa_get_format_bytes(image
->format
);
459 image
->width
= width
;
460 image
->height
= height
;
461 image
->pitch
= pitch
* cpp
;
462 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
468 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
474 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
475 int renderbuffer
, void *loaderPrivate
)
478 struct brw_context
*brw
= context
->driverPrivate
;
479 struct gl_context
*ctx
= &brw
->ctx
;
480 struct gl_renderbuffer
*rb
;
481 struct intel_renderbuffer
*irb
;
483 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
485 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
489 irb
= intel_renderbuffer(rb
);
490 intel_miptree_make_shareable(brw
, irb
->mt
);
491 image
= calloc(1, sizeof *image
);
495 image
->internal_format
= rb
->InternalFormat
;
496 image
->format
= rb
->Format
;
497 image
->modifier
= tiling_to_modifier(irb
->mt
->tiling
);
499 image
->data
= loaderPrivate
;
500 brw_bo_unreference(image
->bo
);
501 image
->bo
= irb
->mt
->bo
;
502 brw_bo_reference(irb
->mt
->bo
);
503 image
->width
= rb
->Width
;
504 image
->height
= rb
->Height
;
505 image
->pitch
= irb
->mt
->pitch
;
506 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
507 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
509 rb
->NeedsFinishRenderTexture
= true;
514 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
515 unsigned texture
, int zoffset
,
521 struct brw_context
*brw
= context
->driverPrivate
;
522 struct gl_texture_object
*obj
;
523 struct intel_texture_object
*iobj
;
526 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
527 if (!obj
|| obj
->Target
!= target
) {
528 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
532 if (target
== GL_TEXTURE_CUBE_MAP
)
535 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
536 iobj
= intel_texture_object(obj
);
537 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
538 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
542 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
543 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
547 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
548 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
551 image
= calloc(1, sizeof *image
);
553 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
557 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
558 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
559 image
->modifier
= tiling_to_modifier(iobj
->mt
->tiling
);
560 image
->data
= loaderPrivate
;
561 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
562 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
563 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
564 if (image
->dri_format
== MESA_FORMAT_NONE
) {
565 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
570 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
575 intel_destroy_image(__DRIimage
*image
)
577 brw_bo_unreference(image
->bo
);
581 enum modifier_priority
{
582 MODIFIER_PRIORITY_INVALID
= 0,
583 MODIFIER_PRIORITY_LINEAR
,
588 const uint64_t priority_to_modifier
[] = {
589 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
590 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
591 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
592 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
596 select_best_modifier(struct gen_device_info
*devinfo
,
597 const uint64_t *modifiers
,
598 const unsigned count
)
600 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
602 for (int i
= 0; i
< count
; i
++) {
603 switch (modifiers
[i
]) {
604 case I915_FORMAT_MOD_Y_TILED
:
605 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
607 case I915_FORMAT_MOD_X_TILED
:
608 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
610 case DRM_FORMAT_MOD_LINEAR
:
611 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
613 case DRM_FORMAT_MOD_INVALID
:
619 return priority_to_modifier
[prio
];
623 intel_create_image_common(__DRIscreen
*dri_screen
,
624 int width
, int height
, int format
,
626 const uint64_t *modifiers
,
631 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
632 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
635 /* Callers of this may specify a modifier, or a dri usage, but not both. The
636 * newer modifier interface deprecates the older usage flags newer modifier
637 * interface deprecates the older usage flags.
639 assert(!(use
&& count
));
641 if (use
& __DRI_IMAGE_USE_CURSOR
) {
642 if (width
!= 64 || height
!= 64)
644 modifier
= DRM_FORMAT_MOD_LINEAR
;
647 if (use
& __DRI_IMAGE_USE_LINEAR
)
648 modifier
= DRM_FORMAT_MOD_LINEAR
;
650 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
652 /* User requested specific modifiers */
653 modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
654 if (modifier
== DRM_FORMAT_MOD_INVALID
)
657 /* Historically, X-tiled was the default, and so lack of modifier means
660 modifier
= I915_FORMAT_MOD_X_TILED
;
664 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
668 const struct isl_drm_modifier_info
*mod_info
=
669 isl_drm_modifier_get_info(modifier
);
671 struct isl_surf surf
;
672 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
673 .dim
= ISL_SURF_DIM_2D
,
674 .format
= brw_isl_format_for_mesa_format(image
->format
),
681 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
682 ISL_SURF_USAGE_TEXTURE_BIT
|
683 ISL_SURF_USAGE_STORAGE_BIT
,
684 .tiling_flags
= (1 << mod_info
->tiling
));
691 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image", surf
.size
,
692 isl_tiling_to_i915_tiling(mod_info
->tiling
),
694 if (image
->bo
== NULL
) {
698 image
->width
= width
;
699 image
->height
= height
;
700 image
->pitch
= surf
.row_pitch
;
701 image
->modifier
= modifier
;
707 intel_create_image(__DRIscreen
*dri_screen
,
708 int width
, int height
, int format
,
712 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
717 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
718 int width
, int height
, int format
,
719 const uint64_t *modifiers
,
720 const unsigned count
,
723 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
724 modifiers
, count
, loaderPrivate
);
728 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
731 case __DRI_IMAGE_ATTRIB_STRIDE
:
732 *value
= image
->pitch
;
734 case __DRI_IMAGE_ATTRIB_HANDLE
:
735 *value
= image
->bo
->gem_handle
;
737 case __DRI_IMAGE_ATTRIB_NAME
:
738 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
739 case __DRI_IMAGE_ATTRIB_FORMAT
:
740 *value
= image
->dri_format
;
742 case __DRI_IMAGE_ATTRIB_WIDTH
:
743 *value
= image
->width
;
745 case __DRI_IMAGE_ATTRIB_HEIGHT
:
746 *value
= image
->height
;
748 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
749 if (image
->planar_format
== NULL
)
751 *value
= image
->planar_format
->components
;
753 case __DRI_IMAGE_ATTRIB_FD
:
754 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
755 case __DRI_IMAGE_ATTRIB_FOURCC
:
756 return intel_lookup_fourcc(image
->dri_format
, value
);
757 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
760 case __DRI_IMAGE_ATTRIB_OFFSET
:
761 *value
= image
->offset
;
763 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
764 *value
= (image
->modifier
& 0xffffffff);
766 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
767 *value
= ((image
->modifier
>> 32) & 0xffffffff);
776 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
780 image
= calloc(1, sizeof *image
);
784 brw_bo_reference(orig_image
->bo
);
785 image
->bo
= orig_image
->bo
;
786 image
->internal_format
= orig_image
->internal_format
;
787 image
->planar_format
= orig_image
->planar_format
;
788 image
->dri_format
= orig_image
->dri_format
;
789 image
->format
= orig_image
->format
;
790 image
->modifier
= orig_image
->modifier
;
791 image
->offset
= orig_image
->offset
;
792 image
->width
= orig_image
->width
;
793 image
->height
= orig_image
->height
;
794 image
->pitch
= orig_image
->pitch
;
795 image
->tile_x
= orig_image
->tile_x
;
796 image
->tile_y
= orig_image
->tile_y
;
797 image
->has_depthstencil
= orig_image
->has_depthstencil
;
798 image
->data
= loaderPrivate
;
800 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
801 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
807 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
809 if (use
& __DRI_IMAGE_USE_CURSOR
) {
810 if (image
->width
!= 64 || image
->height
!= 64)
818 intel_create_image_from_names(__DRIscreen
*dri_screen
,
819 int width
, int height
, int fourcc
,
820 int *names
, int num_names
,
821 int *strides
, int *offsets
,
824 struct intel_image_format
*f
= NULL
;
828 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
831 f
= intel_image_format_lookup(fourcc
);
835 image
= intel_create_image_from_name(dri_screen
, width
, height
,
836 __DRI_IMAGE_FORMAT_NONE
,
837 names
[0], strides
[0],
843 image
->planar_format
= f
;
844 for (i
= 0; i
< f
->nplanes
; i
++) {
845 index
= f
->planes
[i
].buffer_index
;
846 image
->offsets
[index
] = offsets
[index
];
847 image
->strides
[index
] = strides
[index
];
854 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
855 int width
, int height
, int fourcc
,
856 uint64_t modifier
, int *fds
, int num_fds
,
857 int *strides
, int *offsets
,
860 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
861 struct intel_image_format
*f
;
863 unsigned tiled_height
;
866 if (fds
== NULL
|| num_fds
< 1)
869 f
= intel_image_format_lookup(fourcc
);
873 if (modifier
!= DRM_FORMAT_MOD_INVALID
&& !modifier_is_supported(modifier
))
877 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
880 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
886 image
->width
= width
;
887 image
->height
= height
;
888 image
->pitch
= strides
[0];
890 image
->planar_format
= f
;
892 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
893 if (image
->bo
== NULL
) {
898 /* We only support all planes from the same bo.
899 * brw_bo_gem_create_from_prime() should return the same pointer for all
900 * fds received here */
901 for (i
= 1; i
< num_fds
; i
++) {
902 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
903 brw_bo_unreference(aux
);
904 if (aux
!= image
->bo
) {
905 brw_bo_unreference(image
->bo
);
911 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
912 image
->modifier
= modifier
;
914 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
915 tiled_height
= get_tiled_height(image
->modifier
, height
);
918 for (i
= 0; i
< f
->nplanes
; i
++) {
919 index
= f
->planes
[i
].buffer_index
;
920 image
->offsets
[index
] = offsets
[index
];
921 image
->strides
[index
] = strides
[index
];
923 const int plane_height
= tiled_height
>> f
->planes
[i
].height_shift
;
924 const int end
= offsets
[index
] + plane_height
* strides
[index
];
929 /* Check that the requested image actually fits within the BO. 'size'
930 * is already relative to the offsets, so we don't need to add that. */
931 if (image
->bo
->size
== 0) {
932 image
->bo
->size
= size
;
933 } else if (size
> image
->bo
->size
) {
934 brw_bo_unreference(image
->bo
);
939 if (f
->nplanes
== 1) {
940 image
->offset
= image
->offsets
[0];
941 intel_image_warn_if_unaligned(image
, __func__
);
948 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
949 int width
, int height
, int fourcc
,
950 int *fds
, int num_fds
, int *strides
, int *offsets
,
953 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
954 DRM_FORMAT_MOD_INVALID
,
955 fds
, num_fds
, strides
, offsets
,
960 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
961 int width
, int height
,
962 int fourcc
, uint64_t modifier
,
963 int *fds
, int num_fds
,
964 int *strides
, int *offsets
,
965 enum __DRIYUVColorSpace yuv_color_space
,
966 enum __DRISampleRange sample_range
,
967 enum __DRIChromaSiting horizontal_siting
,
968 enum __DRIChromaSiting vertical_siting
,
973 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
976 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
980 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
982 fds
, num_fds
, strides
, offsets
,
986 * Invalid parameters and any inconsistencies between are assumed to be
987 * checked by the caller. Therefore besides unsupported formats one can fail
988 * only in allocation.
991 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
995 image
->dma_buf_imported
= true;
996 image
->yuv_color_space
= yuv_color_space
;
997 image
->sample_range
= sample_range
;
998 image
->horizontal_siting
= horizontal_siting
;
999 image
->vertical_siting
= vertical_siting
;
1001 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1006 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1007 int width
, int height
, int fourcc
,
1008 int *fds
, int num_fds
,
1009 int *strides
, int *offsets
,
1010 enum __DRIYUVColorSpace yuv_color_space
,
1011 enum __DRISampleRange sample_range
,
1012 enum __DRIChromaSiting horizontal_siting
,
1013 enum __DRIChromaSiting vertical_siting
,
1015 void *loaderPrivate
)
1017 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1018 fourcc
, DRM_FORMAT_MOD_INVALID
,
1019 fds
, num_fds
, strides
, offsets
,
1029 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1030 int *formats
, int *count
)
1035 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1039 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1040 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1042 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1050 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1051 uint64_t *modifiers
,
1052 unsigned int *external_only
,
1055 struct intel_screen
*screen
= _screen
->driverPrivate
;
1056 struct intel_image_format
*f
;
1057 int num_mods
= 0, i
;
1059 f
= intel_image_format_lookup(fourcc
);
1063 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
1064 if (screen
->devinfo
.gen
< tiling_modifier_map
[i
].since_gen
)
1071 modifiers
[num_mods
- 1] = tiling_modifier_map
[i
].modifier
;
1072 if (num_mods
>= max
)
1076 if (external_only
!= NULL
) {
1077 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1078 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1079 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1080 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1081 external_only
[i
] = GL_TRUE
;
1084 external_only
[i
] = GL_FALSE
;
1094 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1096 int width
, height
, offset
, stride
, dri_format
, index
;
1097 struct intel_image_format
*f
;
1100 if (parent
== NULL
|| parent
->planar_format
== NULL
)
1103 f
= parent
->planar_format
;
1105 if (plane
>= f
->nplanes
)
1108 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1109 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1110 dri_format
= f
->planes
[plane
].dri_format
;
1111 index
= f
->planes
[plane
].buffer_index
;
1112 offset
= parent
->offsets
[index
];
1113 stride
= parent
->strides
[index
];
1115 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1119 if (offset
+ height
* stride
> parent
->bo
->size
) {
1120 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1125 image
->bo
= parent
->bo
;
1126 brw_bo_reference(parent
->bo
);
1127 image
->modifier
= parent
->modifier
;
1129 image
->width
= width
;
1130 image
->height
= height
;
1131 image
->pitch
= stride
;
1132 image
->offset
= offset
;
1134 intel_image_warn_if_unaligned(image
, __func__
);
1139 static const __DRIimageExtension intelImageExtension
= {
1140 .base
= { __DRI_IMAGE
, 15 },
1142 .createImageFromName
= intel_create_image_from_name
,
1143 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1144 .destroyImage
= intel_destroy_image
,
1145 .createImage
= intel_create_image
,
1146 .queryImage
= intel_query_image
,
1147 .dupImage
= intel_dup_image
,
1148 .validateUsage
= intel_validate_usage
,
1149 .createImageFromNames
= intel_create_image_from_names
,
1150 .fromPlanar
= intel_from_planar
,
1151 .createImageFromTexture
= intel_create_image_from_texture
,
1152 .createImageFromFds
= intel_create_image_from_fds
,
1153 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1155 .getCapabilities
= NULL
,
1158 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1159 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1160 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1161 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1165 get_aperture_size(int fd
)
1167 struct drm_i915_gem_get_aperture aperture
;
1169 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1172 return aperture
.aper_size
;
1176 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1177 int param
, unsigned int *value
)
1179 const struct intel_screen
*const screen
=
1180 (struct intel_screen
*) dri_screen
->driverPrivate
;
1183 case __DRI2_RENDERER_VENDOR_ID
:
1186 case __DRI2_RENDERER_DEVICE_ID
:
1187 value
[0] = screen
->deviceID
;
1189 case __DRI2_RENDERER_ACCELERATED
:
1192 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1193 /* Once a batch uses more than 75% of the maximum mappable size, we
1194 * assume that there's some fragmentation, and we start doing extra
1195 * flushing, etc. That's the big cliff apps will care about.
1197 const unsigned gpu_mappable_megabytes
=
1198 screen
->aperture_threshold
/ (1024 * 1024);
1200 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1201 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1203 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1206 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1207 * (uint64_t) system_page_size
;
1209 const unsigned system_memory_megabytes
=
1210 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1212 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1215 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1218 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1222 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1229 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1230 int param
, const char **value
)
1232 const struct intel_screen
*screen
=
1233 (struct intel_screen
*) dri_screen
->driverPrivate
;
1236 case __DRI2_RENDERER_VENDOR_ID
:
1237 value
[0] = brw_vendor_string
;
1239 case __DRI2_RENDERER_DEVICE_ID
:
1240 value
[0] = brw_get_renderer_string(screen
);
1249 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1250 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1252 .queryInteger
= brw_query_renderer_integer
,
1253 .queryString
= brw_query_renderer_string
1256 static const __DRIrobustnessExtension dri2Robustness
= {
1257 .base
= { __DRI2_ROBUSTNESS
, 1 }
1260 static const __DRIextension
*screenExtensions
[] = {
1261 &intelTexBufferExtension
.base
,
1262 &intelFenceExtension
.base
,
1263 &intelFlushExtension
.base
,
1264 &intelImageExtension
.base
,
1265 &intelRendererQueryExtension
.base
,
1266 &dri2ConfigQueryExtension
.base
,
1270 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1271 &intelTexBufferExtension
.base
,
1272 &intelFenceExtension
.base
,
1273 &intelFlushExtension
.base
,
1274 &intelImageExtension
.base
,
1275 &intelRendererQueryExtension
.base
,
1276 &dri2ConfigQueryExtension
.base
,
1277 &dri2Robustness
.base
,
1282 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1285 struct drm_i915_getparam gp
;
1287 memset(&gp
, 0, sizeof(gp
));
1291 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1294 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1301 intel_get_boolean(struct intel_screen
*screen
, int param
)
1304 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1308 intel_get_integer(struct intel_screen
*screen
, int param
)
1312 if (intel_get_param(screen
, param
, &value
) == 0)
1319 intelDestroyScreen(__DRIscreen
* sPriv
)
1321 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1323 brw_bufmgr_destroy(screen
->bufmgr
);
1324 driDestroyOptionInfo(&screen
->optionCache
);
1326 ralloc_free(screen
);
1327 sPriv
->driverPrivate
= NULL
;
1332 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1334 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1335 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1336 * this does not allocate GPU memory.
1339 intelCreateBuffer(__DRIscreen
*dri_screen
,
1340 __DRIdrawable
* driDrawPriv
,
1341 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1343 struct intel_renderbuffer
*rb
;
1344 struct intel_screen
*screen
= (struct intel_screen
*)
1345 dri_screen
->driverPrivate
;
1346 mesa_format rgbFormat
;
1347 unsigned num_samples
=
1348 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1353 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1357 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1359 if (screen
->winsys_msaa_samples_override
!= -1) {
1360 num_samples
= screen
->winsys_msaa_samples_override
;
1361 fb
->Visual
.samples
= num_samples
;
1364 if (mesaVis
->redBits
== 5) {
1365 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1366 : MESA_FORMAT_B5G6R5_UNORM
;
1367 } else if (mesaVis
->sRGBCapable
) {
1368 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1369 : MESA_FORMAT_B8G8R8A8_SRGB
;
1370 } else if (mesaVis
->alphaBits
== 0) {
1371 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1372 : MESA_FORMAT_B8G8R8X8_UNORM
;
1374 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1375 : MESA_FORMAT_B8G8R8A8_SRGB
;
1376 fb
->Visual
.sRGBCapable
= true;
1379 /* setup the hardware-based renderbuffers */
1380 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1381 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1383 if (mesaVis
->doubleBufferMode
) {
1384 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1385 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1389 * Assert here that the gl_config has an expected depth/stencil bit
1390 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1391 * which constructs the advertised configs.)
1393 if (mesaVis
->depthBits
== 24) {
1394 assert(mesaVis
->stencilBits
== 8);
1396 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1397 rb
= intel_create_private_renderbuffer(screen
,
1398 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1400 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1401 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1403 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1406 * Use combined depth/stencil. Note that the renderbuffer is
1407 * attached to two attachment points.
1409 rb
= intel_create_private_renderbuffer(screen
,
1410 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1412 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1413 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1416 else if (mesaVis
->depthBits
== 16) {
1417 assert(mesaVis
->stencilBits
== 0);
1418 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1420 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1423 assert(mesaVis
->depthBits
== 0);
1424 assert(mesaVis
->stencilBits
== 0);
1427 /* now add any/all software-based renderbuffers we may need */
1428 _swrast_add_soft_renderbuffers(fb
,
1429 false, /* never sw color */
1430 false, /* never sw depth */
1431 false, /* never sw stencil */
1432 mesaVis
->accumRedBits
> 0,
1433 false, /* never sw alpha */
1434 false /* never sw aux */ );
1435 driDrawPriv
->driverPrivate
= fb
;
1441 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1443 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1445 _mesa_reference_framebuffer(&fb
, NULL
);
1449 intel_detect_sseu(struct intel_screen
*screen
)
1451 assert(screen
->devinfo
.gen
>= 8);
1454 screen
->subslice_total
= -1;
1455 screen
->eu_total
= -1;
1457 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1458 &screen
->subslice_total
);
1459 if (ret
< 0 && ret
!= -EINVAL
)
1462 ret
= intel_get_param(screen
,
1463 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1464 if (ret
< 0 && ret
!= -EINVAL
)
1467 /* Without this information, we cannot get the right Braswell brandstrings,
1468 * and we have to use conservative numbers for GPGPU on many platforms, but
1469 * otherwise, things will just work.
1471 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1473 "Kernel 4.1 required to properly query GPU properties.\n");
1478 screen
->subslice_total
= -1;
1479 screen
->eu_total
= -1;
1480 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1484 intel_init_bufmgr(struct intel_screen
*screen
)
1486 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1488 if (getenv("INTEL_NO_HW") != NULL
)
1489 screen
->no_hw
= true;
1491 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1492 if (screen
->bufmgr
== NULL
) {
1493 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1494 __func__
, __LINE__
);
1498 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1499 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1507 intel_detect_swizzling(struct intel_screen
*screen
)
1509 struct brw_bo
*buffer
;
1511 uint32_t aligned_pitch
;
1512 uint32_t tiling
= I915_TILING_X
;
1513 uint32_t swizzle_mode
= 0;
1515 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1516 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1520 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1521 brw_bo_unreference(buffer
);
1523 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1530 intel_detect_timestamp(struct intel_screen
*screen
)
1532 uint64_t dummy
= 0, last
= 0;
1533 int upper
, lower
, loops
;
1535 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1536 * TIMESTAMP register being shifted and the low 32bits always zero.
1538 * More recent kernels offer an interface to read the full 36bits
1541 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1544 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1545 * upper 32bits for a rapidly changing timestamp.
1547 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1551 for (loops
= 0; loops
< 10; loops
++) {
1552 /* The TIMESTAMP should change every 80ns, so several round trips
1553 * through the kernel should be enough to advance it.
1555 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1558 upper
+= (dummy
>> 32) != (last
>> 32);
1559 if (upper
> 1) /* beware 32bit counter overflow */
1560 return 2; /* upper dword holds the low 32bits of the timestamp */
1562 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1564 return 1; /* timestamp is unshifted */
1569 /* No advancement? No timestamp! */
1574 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1576 * Some combinations of hardware and kernel versions allow this feature,
1577 * while others don't. Instead of trying to enumerate every case, just
1578 * try and write a register and see if works.
1581 intel_detect_pipelined_register(struct intel_screen
*screen
,
1582 int reg
, uint32_t expected_value
, bool reset
)
1587 struct brw_bo
*results
, *bo
;
1589 uint32_t offset
= 0;
1591 bool success
= false;
1593 /* Create a zero'ed temporary buffer for reading our results */
1594 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1595 if (results
== NULL
)
1598 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1602 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1608 /* Write the register. */
1609 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1611 *batch
++ = expected_value
;
1613 /* Save the register's value back to the buffer. */
1614 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1616 struct drm_i915_gem_relocation_entry reloc
= {
1617 .offset
= (char *) batch
- (char *) map
,
1618 .delta
= offset
* sizeof(uint32_t),
1619 .target_handle
= results
->gem_handle
,
1620 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1621 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1623 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1625 /* And afterwards clear the register */
1627 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1632 *batch
++ = MI_BATCH_BUFFER_END
;
1634 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1636 .handle
= results
->gem_handle
,
1639 .handle
= bo
->gem_handle
,
1640 .relocation_count
= 1,
1641 .relocs_ptr
= (uintptr_t) &reloc
,
1645 struct drm_i915_gem_execbuffer2 execbuf
= {
1646 .buffers_ptr
= (uintptr_t) exec_objects
,
1648 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1649 .flags
= I915_EXEC_RENDER
,
1652 /* Don't bother with error checking - if the execbuf fails, the
1653 * value won't be written and we'll just report that there's no access.
1655 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1656 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1658 /* Check whether the value got written. */
1659 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1661 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1662 brw_bo_unmap(results
);
1666 brw_bo_unreference(bo
);
1668 brw_bo_unreference(results
);
1674 intel_detect_pipelined_so(struct intel_screen
*screen
)
1676 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1678 /* Supposedly, Broadwell just works. */
1679 if (devinfo
->gen
>= 8)
1682 if (devinfo
->gen
<= 6)
1685 /* See the big explanation about command parser versions below */
1686 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1689 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1690 * statistics registers), and we already reset it to zero before using it.
1692 return intel_detect_pipelined_register(screen
,
1693 GEN7_SO_WRITE_OFFSET(0),
1699 * Return array of MSAA modes supported by the hardware. The array is
1700 * zero-terminated and sorted in decreasing order.
1703 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1705 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1706 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1707 static const int gen7_modes
[] = {8, 4, 0, -1};
1708 static const int gen6_modes
[] = {4, 0, -1};
1709 static const int gen4_modes
[] = {0, -1};
1711 if (screen
->devinfo
.gen
>= 9) {
1713 } else if (screen
->devinfo
.gen
>= 8) {
1715 } else if (screen
->devinfo
.gen
>= 7) {
1717 } else if (screen
->devinfo
.gen
== 6) {
1724 static __DRIconfig
**
1725 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1727 static const mesa_format formats
[] = {
1728 MESA_FORMAT_B5G6R5_UNORM
,
1729 MESA_FORMAT_B8G8R8A8_UNORM
,
1730 MESA_FORMAT_B8G8R8X8_UNORM
,
1732 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1733 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1734 * server may disagree on which format the GLXFBConfig represents,
1735 * resulting in swapped color channels.
1737 * The problem, as of 2017-05-30:
1738 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1739 * order and chooses the first __DRIconfig with the expected channel
1740 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1741 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1743 * EGL does not suffer from this problem. It correctly compares the
1744 * channel masks when matching EGLConfig to __DRIconfig.
1747 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
1748 MESA_FORMAT_R8G8B8A8_UNORM
,
1750 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
1751 MESA_FORMAT_R8G8B8X8_UNORM
,
1754 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1755 static const GLenum back_buffer_modes
[] = {
1756 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1759 static const uint8_t singlesample_samples
[1] = {0};
1760 static const uint8_t multisample_samples
[2] = {4, 8};
1762 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1763 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1764 uint8_t depth_bits
[4], stencil_bits
[4];
1765 __DRIconfig
**configs
= NULL
;
1767 /* Generate singlesample configs without accumulation buffer. */
1768 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1769 __DRIconfig
**new_configs
;
1770 int num_depth_stencil_bits
= 2;
1772 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1773 * buffer that has a different number of bits per pixel than the color
1774 * buffer, gen >= 6 supports this.
1777 stencil_bits
[0] = 0;
1779 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1781 stencil_bits
[1] = 0;
1782 if (devinfo
->gen
>= 6) {
1784 stencil_bits
[2] = 8;
1785 num_depth_stencil_bits
= 3;
1789 stencil_bits
[1] = 8;
1792 new_configs
= driCreateConfigs(formats
[i
],
1795 num_depth_stencil_bits
,
1796 back_buffer_modes
, 2,
1797 singlesample_samples
, 1,
1799 configs
= driConcatConfigs(configs
, new_configs
);
1802 /* Generate the minimum possible set of configs that include an
1803 * accumulation buffer.
1805 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1806 __DRIconfig
**new_configs
;
1808 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1810 stencil_bits
[0] = 0;
1813 stencil_bits
[0] = 8;
1816 new_configs
= driCreateConfigs(formats
[i
],
1817 depth_bits
, stencil_bits
, 1,
1818 back_buffer_modes
, 1,
1819 singlesample_samples
, 1,
1821 configs
= driConcatConfigs(configs
, new_configs
);
1824 /* Generate multisample configs.
1826 * This loop breaks early, and hence is a no-op, on gen < 6.
1828 * Multisample configs must follow the singlesample configs in order to
1829 * work around an X server bug present in 1.12. The X server chooses to
1830 * associate the first listed RGBA888-Z24S8 config, regardless of its
1831 * sample count, with the 32-bit depth visual used for compositing.
1833 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1834 * supported. Singlebuffer configs are not supported because no one wants
1837 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1838 if (devinfo
->gen
< 6)
1841 __DRIconfig
**new_configs
;
1842 const int num_depth_stencil_bits
= 2;
1843 int num_msaa_modes
= 0;
1846 stencil_bits
[0] = 0;
1848 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1850 stencil_bits
[1] = 0;
1853 stencil_bits
[1] = 8;
1856 if (devinfo
->gen
>= 7)
1858 else if (devinfo
->gen
== 6)
1861 new_configs
= driCreateConfigs(formats
[i
],
1864 num_depth_stencil_bits
,
1865 back_buffer_modes
, 1,
1866 multisample_samples
,
1869 configs
= driConcatConfigs(configs
, new_configs
);
1872 if (configs
== NULL
) {
1873 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1882 set_max_gl_versions(struct intel_screen
*screen
)
1884 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1885 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1887 switch (screen
->devinfo
.gen
) {
1891 dri_screen
->max_gl_core_version
= 45;
1892 dri_screen
->max_gl_compat_version
= 30;
1893 dri_screen
->max_gl_es1_version
= 11;
1894 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1897 dri_screen
->max_gl_core_version
= 33;
1898 if (can_do_pipelined_register_writes(screen
)) {
1899 dri_screen
->max_gl_core_version
= 42;
1900 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1901 dri_screen
->max_gl_core_version
= 43;
1902 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1903 dri_screen
->max_gl_core_version
= 45;
1905 dri_screen
->max_gl_compat_version
= 30;
1906 dri_screen
->max_gl_es1_version
= 11;
1907 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1910 dri_screen
->max_gl_core_version
= 33;
1911 dri_screen
->max_gl_compat_version
= 30;
1912 dri_screen
->max_gl_es1_version
= 11;
1913 dri_screen
->max_gl_es2_version
= 30;
1917 dri_screen
->max_gl_core_version
= 0;
1918 dri_screen
->max_gl_compat_version
= 21;
1919 dri_screen
->max_gl_es1_version
= 11;
1920 dri_screen
->max_gl_es2_version
= 20;
1923 unreachable("unrecognized intel_screen::gen");
1928 * Return the revision (generally the revid field of the PCI header) of the
1931 * XXX: This function is useful to keep around even if it is not currently in
1932 * use. It is necessary for new platforms and revision specific workarounds or
1933 * features. Please don't remove it so that we know it at least continues to
1936 static __attribute__((__unused__
)) int
1937 brw_get_revision(int fd
)
1939 struct drm_i915_getparam gp
;
1943 memset(&gp
, 0, sizeof(gp
));
1944 gp
.param
= I915_PARAM_REVISION
;
1945 gp
.value
= &revision
;
1947 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1955 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1957 struct brw_context
*brw
= (struct brw_context
*)data
;
1960 va_start(args
, fmt
);
1962 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1963 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1964 MESA_DEBUG_TYPE_OTHER
,
1965 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1970 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1972 struct brw_context
*brw
= (struct brw_context
*)data
;
1975 va_start(args
, fmt
);
1977 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1979 va_copy(args_copy
, args
);
1980 vfprintf(stderr
, fmt
, args_copy
);
1984 if (brw
->perf_debug
) {
1986 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1987 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1988 MESA_DEBUG_TYPE_PERFORMANCE
,
1989 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1995 parse_devid_override(const char *devid_override
)
1997 static const struct {
2014 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2015 if (!strcmp(name_map
[i
].name
, devid_override
))
2016 return name_map
[i
].pci_id
;
2019 return strtod(devid_override
, NULL
);
2023 * Get the PCI ID for the device. This can be overridden by setting the
2024 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2026 * Returns -1 on ioctl failure.
2029 get_pci_device_id(struct intel_screen
*screen
)
2031 if (geteuid() == getuid()) {
2032 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2033 if (devid_override
) {
2034 screen
->no_hw
= true;
2035 return parse_devid_override(devid_override
);
2039 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2043 * This is the driver specific part of the createNewScreen entry point.
2044 * Called when using DRI2.
2046 * \return the struct gl_config supported by this driver
2049 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2051 struct intel_screen
*screen
;
2053 if (dri_screen
->image
.loader
) {
2054 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2055 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2057 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2058 "support required\n");
2062 /* Allocate the private area */
2063 screen
= rzalloc(NULL
, struct intel_screen
);
2065 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2068 /* parse information in __driConfigOptions */
2069 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2071 screen
->driScrnPriv
= dri_screen
;
2072 dri_screen
->driverPrivate
= (void *) screen
;
2074 screen
->deviceID
= get_pci_device_id(screen
);
2076 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2079 if (!intel_init_bufmgr(screen
))
2082 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2084 brw_process_intel_debug_variable();
2086 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2088 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2089 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2092 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2093 /* Theorectically unlimited! At least for individual objects...
2095 * Currently the entire (global) address space for all GTT maps is
2096 * limited to 64bits. That is all objects on the system that are
2097 * setup for GTT mmapping must fit within 64bits. An attempt to use
2098 * one that exceeds the limit with fail in brw_bo_map_gtt().
2100 * Long before we hit that limit, we will be practically limited by
2101 * that any single object must fit in physical memory (RAM). The upper
2102 * limit on the CPU's address space is currently 48bits (Skylake), of
2103 * which only 39bits can be physical memory. (The GPU itself also has
2104 * a 48bit addressable virtual space.) We can fit over 32 million
2105 * objects of the current maximum allocable size before running out
2108 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2110 /* Estimate the size of the mappable aperture into the GTT. There's an
2111 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2112 * It turns out it's basically always 256MB, though some ancient hardware
2115 uint32_t gtt_size
= 256 * 1024 * 1024;
2117 /* We don't want to map two objects such that a memcpy between them would
2118 * just fault one mapping in and then the other over and over forever. So
2119 * we would need to divide the GTT size by 2. Additionally, some GTT is
2120 * taken up by things like the framebuffer and the ringbuffer and such, so
2121 * be more conservative.
2123 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2126 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2128 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2129 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2131 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2132 screen
->hw_has_swizzling
);
2134 /* GENs prior to 8 do not support EU/Subslice info */
2135 if (devinfo
->gen
>= 8) {
2136 intel_detect_sseu(screen
);
2137 } else if (devinfo
->gen
== 7) {
2138 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2141 /* Gen7-7.5 kernel requirements / command parser saga:
2144 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2146 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2147 * all batches secure, allowing them to use any feature with no checking.
2148 * This is effectively equivalent to a command parser version of
2149 * \infinity - everything is possible.
2151 * The command parser does not exist, and querying the version will
2155 * The kernel enables the command parser by default, for systems with
2156 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2157 * hardware checker is still enabled, so Haswell and Baytrail cannot
2160 * Ivybridge goes from "everything is possible" to "only what the
2161 * command parser allows" (if the user boots with i915.cmd_parser=0,
2162 * then everything is possible again). We can only safely use features
2163 * allowed by the supported command parser version.
2165 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2166 * implemented by the kernel, even if it's turned off. So, checking
2167 * for version > 0 does not mean that you can write registers. We have
2168 * to try it and see. The version does, however, indicate the age of
2171 * Instead of matching the hardware checker's behavior of converting
2172 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2173 * -EINVAL, making it dangerous to try and use privileged features.
2175 * Effective command parser versions:
2176 * - Haswell: 0 (reporting 1, writes don't work)
2177 * - Baytrail: 0 (reporting 1, writes don't work)
2178 * - Ivybridge: 1 (enabled) or infinite (disabled)
2181 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2182 * effectively version 1 (enabled) or infinite (disabled).
2184 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2185 * Command parser v2 supports predicate writes.
2187 * - Haswell: 0 (reporting 1, writes don't work)
2188 * - Baytrail: 2 (enabled) or infinite (disabled)
2189 * - Ivybridge: 2 (enabled) or infinite (disabled)
2191 * So version >= 2 is enough to know that Ivybridge and Baytrail
2192 * will work. Haswell still can't do anything.
2194 * - v4.0: Version 3 happened. Largely not relevant.
2196 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2197 * L3 config registers are properly saved and restored as part
2198 * of the hardware context. We can approximately detect this point
2199 * in time by checking if I915_PARAM_REVISION is recognized - it
2200 * landed in a later commit, but in the same release cycle.
2202 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2203 * Command parser finally gains secure batch promotion. On Haswell,
2204 * the hardware checker gets disabled, which finally allows it to do
2205 * privileged commands.
2207 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2208 * - Haswell: 3 (enabled) or 0 (disabled)
2209 * - Baytrail: 3 (enabled) or infinite (disabled)
2210 * - Ivybridge: 3 (enabled) or infinite (disabled)
2212 * Unfortunately, detecting this point in time is tricky, because
2213 * no version bump happened when this important change occurred.
2214 * On Haswell, if we can write any register, then the kernel is at
2215 * least this new, and we can start trusting the version number.
2217 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2218 * Command parser reaches version 4, allowing access to Haswell
2219 * atomic scratch and chicken3 registers. If version >= 4, we know
2220 * the kernel is new enough to support privileged features on all
2221 * hardware. However, the user might have disabled it...and the
2222 * kernel will still report version 4. So we still have to guess
2225 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2226 * Command parser v5 whitelists indirect compute shader dispatch
2227 * registers, needed for OpenGL 4.3 and later.
2230 * Command parser v7 lets us use MI_MATH on Haswell.
2232 * Additionally, the kernel begins reporting version 0 when
2233 * the command parser is disabled, allowing us to skip the
2234 * guess-and-check step on Haswell. Unfortunately, this also
2235 * means that we can no longer use it as an indicator of the
2236 * age of the kernel.
2238 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2239 &screen
->cmd_parser_version
) < 0) {
2240 /* Command parser does not exist - getparam is unrecognized */
2241 screen
->cmd_parser_version
= 0;
2244 /* Kernel 4.13 retuired for exec object capture */
2245 #ifndef I915_PARAM_HAS_EXEC_CAPTURE
2246 #define I915_PARAM_HAS_EXEC_CAPTURE 45
2248 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2249 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2252 if (!intel_detect_pipelined_so(screen
)) {
2253 /* We can't do anything, so the effective version is 0. */
2254 screen
->cmd_parser_version
= 0;
2256 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2259 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2260 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2262 /* Haswell requires command parser version 4 in order to have L3
2263 * atomic scratch1 and chicken3 bits
2265 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2266 screen
->kernel_features
|=
2267 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2270 /* Haswell requires command parser version 6 in order to write to the
2271 * MI_MATH GPR registers, and version 7 in order to use
2272 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2274 if (devinfo
->gen
>= 8 ||
2275 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2276 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2279 /* Gen7 needs at least command parser version 5 to support compute */
2280 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2281 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2283 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2285 screen
->winsys_msaa_samples_override
=
2286 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2287 printf("Forcing winsys sample count to %d\n",
2288 screen
->winsys_msaa_samples_override
);
2290 screen
->winsys_msaa_samples_override
= -1;
2293 set_max_gl_versions(screen
);
2295 /* Notification of GPU resets requires hardware contexts and a kernel new
2296 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2297 * supported, calling it with a context of 0 will either generate EPERM or
2298 * no error. If the ioctl is not supported, it always generate EINVAL.
2299 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2300 * extension to the loader.
2302 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2304 if (devinfo
->gen
>= 6) {
2305 struct drm_i915_reset_stats stats
;
2306 memset(&stats
, 0, sizeof(stats
));
2308 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2310 screen
->has_context_reset_notification
=
2311 (ret
!= -1 || errno
!= EINVAL
);
2314 dri_screen
->extensions
= !screen
->has_context_reset_notification
2315 ? screenExtensions
: intelRobustScreenExtensions
;
2317 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2318 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2319 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2320 screen
->program_id
= 1;
2322 screen
->has_exec_fence
=
2323 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2325 intel_screen_init_surface_formats(screen
);
2327 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2330 struct intel_buffer
{
2335 static __DRIbuffer
*
2336 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2337 unsigned attachment
, unsigned format
,
2338 int width
, int height
)
2340 struct intel_buffer
*intelBuffer
;
2341 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2343 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2344 attachment
== __DRI_BUFFER_BACK_LEFT
);
2346 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2347 if (intelBuffer
== NULL
)
2350 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2351 * supports Y tiled and compressed buffers, but there is no way to plumb that
2352 * through to here. */
2354 int cpp
= format
/ 8;
2355 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2356 "intelAllocateBuffer",
2360 I915_TILING_X
, &pitch
,
2361 BO_ALLOC_FOR_RENDER
);
2363 if (intelBuffer
->bo
== NULL
) {
2368 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2370 intelBuffer
->base
.attachment
= attachment
;
2371 intelBuffer
->base
.cpp
= cpp
;
2372 intelBuffer
->base
.pitch
= pitch
;
2374 return &intelBuffer
->base
;
2378 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2380 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2382 brw_bo_unreference(intelBuffer
->bo
);
2386 static const struct __DriverAPIRec brw_driver_api
= {
2387 .InitScreen
= intelInitScreen2
,
2388 .DestroyScreen
= intelDestroyScreen
,
2389 .CreateContext
= brwCreateContext
,
2390 .DestroyContext
= intelDestroyContext
,
2391 .CreateBuffer
= intelCreateBuffer
,
2392 .DestroyBuffer
= intelDestroyBuffer
,
2393 .MakeCurrent
= intelMakeCurrent
,
2394 .UnbindContext
= intelUnbindContext
,
2395 .AllocateBuffer
= intelAllocateBuffer
,
2396 .ReleaseBuffer
= intelReleaseBuffer
2399 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2400 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2401 .vtable
= &brw_driver_api
,
2404 static const __DRIextension
*brw_driver_extensions
[] = {
2405 &driCoreExtension
.base
,
2406 &driImageDriverExtension
.base
,
2407 &driDRI2Extension
.base
,
2409 &brw_config_options
.base
,
2413 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2415 globalDriverAPI
= &brw_driver_api
;
2417 return brw_driver_extensions
;