2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
49 #include "common/gen_defines.h"
51 static const __DRIconfigOptionsExtension brw_config_options
= {
52 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
55 DRI_CONF_SECTION_PERFORMANCE
56 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
57 * DRI_CONF_BO_REUSE_ALL
59 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
60 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
61 DRI_CONF_ENUM(0, "Disable buffer object reuse")
62 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
65 DRI_CONF_MESA_NO_ERROR("false")
66 DRI_CONF_MESA_GLTHREAD("false")
69 DRI_CONF_SECTION_QUALITY
70 DRI_CONF_PRECISE_TRIG("false")
72 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
73 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
74 "given integer. If negative, then do not clamp.")
78 DRI_CONF_SECTION_DEBUG
79 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
80 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
81 DRI_CONF_DISABLE_THROTTLING("false")
82 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
83 DRI_CONF_FORCE_GLSL_VERSION(0)
84 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
85 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
86 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
88 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
89 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
90 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
91 DRI_CONF_FORCE_COMPAT_PROFILE("false")
92 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
94 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
95 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
99 DRI_CONF_SECTION_MISCELLANEOUS
100 DRI_CONF_GLSL_ZERO_INIT("false")
101 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
102 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
103 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
104 DRI_CONF_ALLOW_FP16_CONFIGS("false")
109 #include "intel_batchbuffer.h"
110 #include "intel_buffers.h"
111 #include "brw_bufmgr.h"
112 #include "intel_fbo.h"
113 #include "intel_mipmap_tree.h"
114 #include "intel_screen.h"
115 #include "intel_tex.h"
116 #include "intel_image.h"
118 #include "brw_context.h"
120 #include "drm-uapi/i915_drm.h"
123 * For debugging purposes, this returns a time in seconds.
130 clock_gettime(CLOCK_MONOTONIC
, &tp
);
132 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
135 static const __DRItexBufferExtension intelTexBufferExtension
= {
136 .base
= { __DRI_TEX_BUFFER
, 3 },
138 .setTexBuffer
= intelSetTexBuffer
,
139 .setTexBuffer2
= intelSetTexBuffer2
,
140 .releaseTexBuffer
= intelReleaseTexBuffer
,
144 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
145 __DRIdrawable
*dPriv
,
147 enum __DRI2throttleReason reason
)
149 struct brw_context
*brw
= cPriv
->driverPrivate
;
154 struct gl_context
*ctx
= &brw
->ctx
;
156 _mesa_glthread_finish(ctx
);
158 FLUSH_VERTICES(ctx
, 0);
160 if (flags
& __DRI2_FLUSH_DRAWABLE
)
161 intel_resolve_for_dri2_flush(brw
, dPriv
);
163 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
164 brw
->need_swap_throttle
= true;
165 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
166 brw
->need_flush_throttle
= true;
168 intel_batchbuffer_flush(brw
);
172 * Provides compatibility with loaders that only support the older (version
173 * 1-3) flush interface.
175 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
178 intel_dri2_flush(__DRIdrawable
*drawable
)
180 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
181 __DRI2_FLUSH_DRAWABLE
,
182 __DRI2_THROTTLE_SWAPBUFFER
);
185 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
186 .base
= { __DRI2_FLUSH
, 4 },
188 .flush
= intel_dri2_flush
,
189 .invalidate
= dri2InvalidateDrawable
,
190 .flush_with_flags
= intel_dri2_flush_with_flags
,
193 static const struct intel_image_format intel_image_formats
[] = {
194 { DRM_FORMAT_ABGR16161616F
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F
, 8 } } },
197 { DRM_FORMAT_XBGR16161616F
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F
, 8 } } },
200 { DRM_FORMAT_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
203 { DRM_FORMAT_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
206 { DRM_FORMAT_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
209 { DRM_FORMAT_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
212 { DRM_FORMAT_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { DRM_FORMAT_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { DRM_FORMAT_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
224 { DRM_FORMAT_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
227 { DRM_FORMAT_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
230 { DRM_FORMAT_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
233 { DRM_FORMAT_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
236 { DRM_FORMAT_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
239 { DRM_FORMAT_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
242 { DRM_FORMAT_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
245 { DRM_FORMAT_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
250 { DRM_FORMAT_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { DRM_FORMAT_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
260 { DRM_FORMAT_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
265 { DRM_FORMAT_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
270 { DRM_FORMAT_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
275 { DRM_FORMAT_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
276 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
280 { DRM_FORMAT_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
281 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
285 { DRM_FORMAT_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
286 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
287 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
290 { DRM_FORMAT_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
292 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
293 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
295 { DRM_FORMAT_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
296 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
297 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
299 { DRM_FORMAT_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
301 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
303 { DRM_FORMAT_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
304 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
305 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
307 { DRM_FORMAT_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
308 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
309 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
311 { DRM_FORMAT_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
312 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
313 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
315 { DRM_FORMAT_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
316 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
318 { DRM_FORMAT_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
319 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
321 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
322 * and treat them as planar buffers in the compositors.
323 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
324 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
325 * clusters and places pairs and places U into the G component and
326 * V into A. This lets the texture sampler interpolate the Y
327 * components correctly when sampling from plane 0, and interpolate
328 * U and V correctly when sampling from plane 1. */
329 { DRM_FORMAT_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
330 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
331 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
332 { DRM_FORMAT_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
333 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
334 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
337 static const struct {
340 } supported_modifiers
[] = {
341 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
342 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
343 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
344 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
348 modifier_is_supported(const struct gen_device_info
*devinfo
,
349 const struct intel_image_format
*fmt
, int dri_format
,
352 const struct isl_drm_modifier_info
*modinfo
=
353 isl_drm_modifier_get_info(modifier
);
356 /* ISL had better know about the modifier */
360 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
361 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
362 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
365 /* CCS_E is not supported for planar images */
366 if (fmt
&& fmt
->nplanes
> 1)
370 assert(dri_format
== 0);
371 dri_format
= fmt
->planes
[0].dri_format
;
374 mesa_format format
= driImageFormatToGLFormat(dri_format
);
375 /* Whether or not we support compression is based on the RGBA non-sRGB
376 * version of the format.
378 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
379 format
= _mesa_get_srgb_format_linear(format
);
380 if (!isl_format_supports_ccs_e(devinfo
,
381 brw_isl_format_for_mesa_format(format
)))
385 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
386 if (supported_modifiers
[i
].modifier
!= modifier
)
389 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
396 tiling_to_modifier(uint32_t tiling
)
398 static const uint64_t map
[] = {
399 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
400 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
401 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
404 assert(tiling
< ARRAY_SIZE(map
));
410 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
412 uint32_t tiling
, swizzle
;
413 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
415 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
416 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
417 func
, image
->offset
);
421 static const struct intel_image_format
*
422 intel_image_format_lookup(int fourcc
)
424 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
425 if (intel_image_formats
[i
].fourcc
== fourcc
)
426 return &intel_image_formats
[i
];
433 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
435 if (image
->planar_format
) {
436 *fourcc
= image
->planar_format
->fourcc
;
440 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
441 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
442 *fourcc
= intel_image_formats
[i
].fourcc
;
450 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
455 image
= calloc(1, sizeof *image
);
459 image
->screen
= screen
;
460 image
->dri_format
= dri_format
;
463 image
->format
= driImageFormatToGLFormat(dri_format
);
464 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
465 image
->format
== MESA_FORMAT_NONE
) {
470 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
471 image
->data
= loaderPrivate
;
477 * Sets up a DRIImage structure to point to a slice out of a miptree.
480 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
481 struct intel_mipmap_tree
*mt
, GLuint level
,
484 intel_miptree_make_shareable(brw
, mt
);
486 intel_miptree_check_level_layer(mt
, level
, zoffset
);
488 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
489 level
- mt
->first_level
);
490 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
491 level
- mt
->first_level
);
492 image
->pitch
= mt
->surf
.row_pitch_B
;
494 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
498 brw_bo_unreference(image
->bo
);
500 brw_bo_reference(mt
->bo
);
504 intel_create_image_from_name(__DRIscreen
*dri_screen
,
505 int width
, int height
, int format
,
506 int name
, int pitch
, void *loaderPrivate
)
508 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
512 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
516 if (image
->format
== MESA_FORMAT_NONE
)
519 cpp
= _mesa_get_format_bytes(image
->format
);
521 image
->width
= width
;
522 image
->height
= height
;
523 image
->pitch
= pitch
* cpp
;
524 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
530 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
536 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
537 int renderbuffer
, void *loaderPrivate
)
540 struct brw_context
*brw
= context
->driverPrivate
;
541 struct gl_context
*ctx
= &brw
->ctx
;
542 struct gl_renderbuffer
*rb
;
543 struct intel_renderbuffer
*irb
;
545 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
547 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
551 irb
= intel_renderbuffer(rb
);
552 intel_miptree_make_shareable(brw
, irb
->mt
);
553 image
= calloc(1, sizeof *image
);
557 image
->internal_format
= rb
->InternalFormat
;
558 image
->format
= rb
->Format
;
559 image
->modifier
= tiling_to_modifier(
560 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
562 image
->data
= loaderPrivate
;
563 brw_bo_unreference(image
->bo
);
564 image
->bo
= irb
->mt
->bo
;
565 brw_bo_reference(irb
->mt
->bo
);
566 image
->width
= rb
->Width
;
567 image
->height
= rb
->Height
;
568 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
569 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
570 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
572 rb
->NeedsFinishRenderTexture
= true;
577 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
578 unsigned texture
, int zoffset
,
584 struct brw_context
*brw
= context
->driverPrivate
;
585 struct gl_texture_object
*obj
;
586 struct intel_texture_object
*iobj
;
589 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
590 if (!obj
|| obj
->Target
!= target
) {
591 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
595 if (target
== GL_TEXTURE_CUBE_MAP
)
598 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
599 iobj
= intel_texture_object(obj
);
600 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
601 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
605 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
606 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
610 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
611 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
614 image
= calloc(1, sizeof *image
);
616 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
620 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
621 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
622 image
->modifier
= tiling_to_modifier(
623 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
624 image
->data
= loaderPrivate
;
625 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
626 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
627 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
628 image
->planar_format
= iobj
->planar_format
;
629 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
630 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
635 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
640 intel_destroy_image(__DRIimage
*image
)
642 brw_bo_unreference(image
->bo
);
646 enum modifier_priority
{
647 MODIFIER_PRIORITY_INVALID
= 0,
648 MODIFIER_PRIORITY_LINEAR
,
651 MODIFIER_PRIORITY_Y_CCS
,
654 const uint64_t priority_to_modifier
[] = {
655 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
656 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
657 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
658 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
659 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
663 select_best_modifier(struct gen_device_info
*devinfo
,
665 const uint64_t *modifiers
,
666 const unsigned count
)
668 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
670 for (int i
= 0; i
< count
; i
++) {
671 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
674 switch (modifiers
[i
]) {
675 case I915_FORMAT_MOD_Y_TILED_CCS
:
676 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
678 case I915_FORMAT_MOD_Y_TILED
:
679 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
681 case I915_FORMAT_MOD_X_TILED
:
682 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
684 case DRM_FORMAT_MOD_LINEAR
:
685 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
687 case DRM_FORMAT_MOD_INVALID
:
693 return priority_to_modifier
[prio
];
697 intel_create_image_common(__DRIscreen
*dri_screen
,
698 int width
, int height
, int format
,
700 const uint64_t *modifiers
,
705 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
706 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
709 /* Callers of this may specify a modifier, or a dri usage, but not both. The
710 * newer modifier interface deprecates the older usage flags newer modifier
711 * interface deprecates the older usage flags.
713 assert(!(use
&& count
));
715 if (use
& __DRI_IMAGE_USE_CURSOR
) {
716 if (width
!= 64 || height
!= 64)
718 modifier
= DRM_FORMAT_MOD_LINEAR
;
721 if (use
& __DRI_IMAGE_USE_LINEAR
)
722 modifier
= DRM_FORMAT_MOD_LINEAR
;
724 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
726 /* User requested specific modifiers */
727 modifier
= select_best_modifier(&screen
->devinfo
, format
,
729 if (modifier
== DRM_FORMAT_MOD_INVALID
)
732 /* Historically, X-tiled was the default, and so lack of modifier means
735 modifier
= I915_FORMAT_MOD_X_TILED
;
739 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
743 const struct isl_drm_modifier_info
*mod_info
=
744 isl_drm_modifier_get_info(modifier
);
746 struct isl_surf surf
;
747 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
748 .dim
= ISL_SURF_DIM_2D
,
749 .format
= brw_isl_format_for_mesa_format(image
->format
),
756 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
757 ISL_SURF_USAGE_TEXTURE_BIT
|
758 ISL_SURF_USAGE_STORAGE_BIT
|
759 ((use
& __DRI_IMAGE_USE_SCANOUT
) ?
760 ISL_SURF_USAGE_DISPLAY_BIT
: 0),
761 .tiling_flags
= (1 << mod_info
->tiling
));
768 struct isl_surf aux_surf
= {0,};
769 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
770 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
, 0);
776 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
780 /* We request that the bufmgr zero the buffer for us for two reasons:
782 * 1) If a buffer gets re-used from the pool, we don't want to leak random
783 * garbage from our process to some other.
785 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
786 * a valid state. A CCS value of 0 indicates that the given block is
787 * in the pass-through state which is what we want.
789 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
790 surf
.size_B
+ aux_surf
.size_B
,
792 isl_tiling_to_i915_tiling(mod_info
->tiling
),
793 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
794 if (image
->bo
== NULL
) {
798 image
->width
= width
;
799 image
->height
= height
;
800 image
->pitch
= surf
.row_pitch_B
;
801 image
->modifier
= modifier
;
803 if (aux_surf
.size_B
) {
804 image
->aux_offset
= surf
.size_B
;
805 image
->aux_pitch
= aux_surf
.row_pitch_B
;
806 image
->aux_size
= aux_surf
.size_B
;
813 intel_create_image(__DRIscreen
*dri_screen
,
814 int width
, int height
, int format
,
818 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
823 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
824 int x0
, int y0
, int width
, int height
,
825 unsigned int flags
, int *stride
, void **map_info
)
827 struct brw_context
*brw
= NULL
;
828 struct brw_bo
*bo
= NULL
;
829 void *raw_data
= NULL
;
834 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
837 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
840 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
843 if (flags
& MAP_INTERNAL_MASK
)
846 brw
= context
->driverPrivate
;
852 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
853 raw_data
= brw_bo_map(brw
, bo
, flags
);
857 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
858 pix_bytes
= _mesa_get_format_bytes(image
->format
);
862 assert(pix_bytes
> 0);
864 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
866 brw_bo_reference(bo
);
868 *stride
= image
->pitch
;
875 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
877 struct brw_bo
*bo
= map_info
;
880 brw_bo_unreference(bo
);
884 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
885 int width
, int height
, int format
,
886 const uint64_t *modifiers
,
887 const unsigned count
,
890 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
891 modifiers
, count
, loaderPrivate
);
895 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
898 case __DRI_IMAGE_ATTRIB_STRIDE
:
899 *value
= image
->pitch
;
901 case __DRI_IMAGE_ATTRIB_HANDLE
:
902 *value
= brw_bo_export_gem_handle(image
->bo
);
904 case __DRI_IMAGE_ATTRIB_NAME
:
905 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
906 case __DRI_IMAGE_ATTRIB_FORMAT
:
907 *value
= image
->dri_format
;
909 case __DRI_IMAGE_ATTRIB_WIDTH
:
910 *value
= image
->width
;
912 case __DRI_IMAGE_ATTRIB_HEIGHT
:
913 *value
= image
->height
;
915 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
916 if (image
->planar_format
== NULL
)
918 *value
= image
->planar_format
->components
;
920 case __DRI_IMAGE_ATTRIB_FD
:
921 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
922 case __DRI_IMAGE_ATTRIB_FOURCC
:
923 return intel_image_get_fourcc(image
, value
);
924 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
925 if (isl_drm_modifier_has_aux(image
->modifier
)) {
926 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
928 } else if (image
->planar_format
) {
929 *value
= image
->planar_format
->nplanes
;
934 case __DRI_IMAGE_ATTRIB_OFFSET
:
935 *value
= image
->offset
;
937 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
938 *value
= (image
->modifier
& 0xffffffff);
940 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
941 *value
= ((image
->modifier
>> 32) & 0xffffffff);
950 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
951 uint32_t fourcc
, uint64_t modifier
,
952 int attrib
, uint64_t *value
)
954 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
955 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
957 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
961 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
962 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
971 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
975 image
= calloc(1, sizeof *image
);
979 brw_bo_reference(orig_image
->bo
);
980 image
->bo
= orig_image
->bo
;
981 image
->internal_format
= orig_image
->internal_format
;
982 image
->planar_format
= orig_image
->planar_format
;
983 image
->dri_format
= orig_image
->dri_format
;
984 image
->format
= orig_image
->format
;
985 image
->modifier
= orig_image
->modifier
;
986 image
->offset
= orig_image
->offset
;
987 image
->width
= orig_image
->width
;
988 image
->height
= orig_image
->height
;
989 image
->pitch
= orig_image
->pitch
;
990 image
->tile_x
= orig_image
->tile_x
;
991 image
->tile_y
= orig_image
->tile_y
;
992 image
->has_depthstencil
= orig_image
->has_depthstencil
;
993 image
->data
= loaderPrivate
;
994 image
->aux_offset
= orig_image
->aux_offset
;
995 image
->aux_pitch
= orig_image
->aux_pitch
;
997 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
998 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
1004 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
1006 if (use
& __DRI_IMAGE_USE_CURSOR
) {
1007 if (image
->width
!= 64 || image
->height
!= 64)
1015 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1016 int width
, int height
, int fourcc
,
1017 int *names
, int num_names
,
1018 int *strides
, int *offsets
,
1019 void *loaderPrivate
)
1021 const struct intel_image_format
*f
= NULL
;
1025 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1028 f
= intel_image_format_lookup(fourcc
);
1032 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1033 __DRI_IMAGE_FORMAT_NONE
,
1034 names
[0], strides
[0],
1040 image
->planar_format
= f
;
1041 for (i
= 0; i
< f
->nplanes
; i
++) {
1042 index
= f
->planes
[i
].buffer_index
;
1043 image
->offsets
[index
] = offsets
[index
];
1044 image
->strides
[index
] = strides
[index
];
1051 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1052 int width
, int height
, int fourcc
,
1053 uint64_t modifier
, int *fds
, int num_fds
,
1054 int *strides
, int *offsets
,
1055 void *loaderPrivate
)
1057 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1058 const struct intel_image_format
*f
;
1063 if (fds
== NULL
|| num_fds
< 1)
1066 f
= intel_image_format_lookup(fourcc
);
1070 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1071 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1074 if (f
->nplanes
== 1)
1075 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1078 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1084 image
->width
= width
;
1085 image
->height
= height
;
1086 image
->pitch
= strides
[0];
1088 image
->planar_format
= f
;
1090 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1091 const struct isl_drm_modifier_info
*mod_info
=
1092 isl_drm_modifier_get_info(modifier
);
1093 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1094 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1095 tiling
, strides
[0]);
1097 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1100 if (image
->bo
== NULL
) {
1105 /* We only support all planes from the same bo.
1106 * brw_bo_gem_create_from_prime() should return the same pointer for all
1107 * fds received here */
1108 for (i
= 1; i
< num_fds
; i
++) {
1109 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1110 brw_bo_unreference(aux
);
1111 if (aux
!= image
->bo
) {
1112 brw_bo_unreference(image
->bo
);
1118 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1119 image
->modifier
= modifier
;
1121 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1123 const struct isl_drm_modifier_info
*mod_info
=
1124 isl_drm_modifier_get_info(image
->modifier
);
1127 struct isl_surf surf
;
1128 for (i
= 0; i
< f
->nplanes
; i
++) {
1129 index
= f
->planes
[i
].buffer_index
;
1130 image
->offsets
[index
] = offsets
[index
];
1131 image
->strides
[index
] = strides
[index
];
1133 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1134 /* The images we will create are actually based on the RGBA non-sRGB
1135 * version of the format.
1137 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1138 format
= _mesa_get_srgb_format_linear(format
);
1140 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1141 .dim
= ISL_SURF_DIM_2D
,
1142 .format
= brw_isl_format_for_mesa_format(format
),
1143 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1144 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1149 .row_pitch_B
= strides
[index
],
1150 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1151 ISL_SURF_USAGE_TEXTURE_BIT
|
1152 ISL_SURF_USAGE_STORAGE_BIT
,
1153 .tiling_flags
= (1 << mod_info
->tiling
));
1155 brw_bo_unreference(image
->bo
);
1160 const int end
= offsets
[index
] + surf
.size_B
;
1165 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1166 /* Even though we initialize surf in the loop above, we know that
1167 * anything with CCS_E will have exactly one plane so surf is properly
1168 * initialized when we get here.
1170 assert(f
->nplanes
== 1);
1172 image
->aux_offset
= offsets
[1];
1173 image
->aux_pitch
= strides
[1];
1175 /* Scanout hardware requires that the CCS be placed after the main
1176 * surface in memory. We consider any CCS that is placed any earlier in
1177 * memory to be invalid and reject it.
1179 * At some point in the future, this restriction may be relaxed if the
1180 * hardware becomes less strict but we may need a new modifier for that.
1183 if (image
->aux_offset
< size
) {
1184 brw_bo_unreference(image
->bo
);
1189 struct isl_surf aux_surf
= {0,};
1190 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
,
1193 brw_bo_unreference(image
->bo
);
1198 image
->aux_size
= aux_surf
.size_B
;
1200 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1204 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1207 /* Check that the requested image actually fits within the BO. 'size'
1208 * is already relative to the offsets, so we don't need to add that. */
1209 if (image
->bo
->size
== 0) {
1210 image
->bo
->size
= size
;
1211 } else if (size
> image
->bo
->size
) {
1212 brw_bo_unreference(image
->bo
);
1217 if (f
->nplanes
== 1) {
1218 image
->offset
= image
->offsets
[0];
1219 intel_image_warn_if_unaligned(image
, __func__
);
1226 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1227 int width
, int height
, int fourcc
,
1228 int *fds
, int num_fds
, int *strides
, int *offsets
,
1229 void *loaderPrivate
)
1231 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1232 DRM_FORMAT_MOD_INVALID
,
1233 fds
, num_fds
, strides
, offsets
,
1238 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1239 int width
, int height
,
1240 int fourcc
, uint64_t modifier
,
1241 int *fds
, int num_fds
,
1242 int *strides
, int *offsets
,
1243 enum __DRIYUVColorSpace yuv_color_space
,
1244 enum __DRISampleRange sample_range
,
1245 enum __DRIChromaSiting horizontal_siting
,
1246 enum __DRIChromaSiting vertical_siting
,
1248 void *loaderPrivate
)
1251 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1254 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1258 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1260 fds
, num_fds
, strides
, offsets
,
1264 * Invalid parameters and any inconsistencies between are assumed to be
1265 * checked by the caller. Therefore besides unsupported formats one can fail
1266 * only in allocation.
1269 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1273 image
->yuv_color_space
= yuv_color_space
;
1274 image
->sample_range
= sample_range
;
1275 image
->horizontal_siting
= horizontal_siting
;
1276 image
->vertical_siting
= vertical_siting
;
1278 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1283 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1284 int width
, int height
, int fourcc
,
1285 int *fds
, int num_fds
,
1286 int *strides
, int *offsets
,
1287 enum __DRIYUVColorSpace yuv_color_space
,
1288 enum __DRISampleRange sample_range
,
1289 enum __DRIChromaSiting horizontal_siting
,
1290 enum __DRIChromaSiting vertical_siting
,
1292 void *loaderPrivate
)
1294 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1295 fourcc
, DRM_FORMAT_MOD_INVALID
,
1296 fds
, num_fds
, strides
, offsets
,
1306 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1307 const struct intel_image_format
*fmt
)
1309 /* Currently, all formats with an intel_image_format are available on all
1310 * platforms so there's really nothing to check there.
1314 if (fmt
->nplanes
== 1) {
1315 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1316 /* The images we will create are actually based on the RGBA non-sRGB
1317 * version of the format.
1319 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1320 format
= _mesa_get_srgb_format_linear(format
);
1321 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1322 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1330 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1331 int *formats
, int *count
)
1333 struct intel_screen
*screen
= _screen
->driverPrivate
;
1334 int num_formats
= 0, i
;
1336 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1337 /* These two formats are valid DRI formats but do not exist in
1338 * drm_fourcc.h in the Linux kernel. We don't want to accidentally
1339 * advertise them through the EGL layer.
1341 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1342 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
)
1345 if (!intel_image_format_is_supported(&screen
->devinfo
,
1346 &intel_image_formats
[i
]))
1353 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1354 if (num_formats
>= max
)
1358 *count
= num_formats
;
1363 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1364 uint64_t *modifiers
,
1365 unsigned int *external_only
,
1368 struct intel_screen
*screen
= _screen
->driverPrivate
;
1369 const struct intel_image_format
*f
;
1370 int num_mods
= 0, i
;
1372 f
= intel_image_format_lookup(fourcc
);
1376 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1379 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1380 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1381 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1388 modifiers
[num_mods
- 1] = modifier
;
1389 if (num_mods
>= max
)
1393 if (external_only
!= NULL
) {
1394 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1395 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1396 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1397 f
->components
== __DRI_IMAGE_COMPONENTS_AYUV
||
1398 f
->components
== __DRI_IMAGE_COMPONENTS_XYUV
||
1399 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1400 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1401 external_only
[i
] = GL_TRUE
;
1404 external_only
[i
] = GL_FALSE
;
1414 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1416 int width
, height
, offset
, stride
, size
, dri_format
;
1422 width
= parent
->width
;
1423 height
= parent
->height
;
1425 const struct intel_image_format
*f
= parent
->planar_format
;
1427 if (f
&& plane
< f
->nplanes
) {
1428 /* Use the planar format definition. */
1429 width
>>= f
->planes
[plane
].width_shift
;
1430 height
>>= f
->planes
[plane
].height_shift
;
1431 dri_format
= f
->planes
[plane
].dri_format
;
1432 int index
= f
->planes
[plane
].buffer_index
;
1433 offset
= parent
->offsets
[index
];
1434 stride
= parent
->strides
[index
];
1435 size
= height
* stride
;
1436 } else if (plane
== 0) {
1437 /* The only plane of a non-planar image: copy the parent definition
1439 dri_format
= parent
->dri_format
;
1440 offset
= parent
->offset
;
1441 stride
= parent
->pitch
;
1442 size
= height
* stride
;
1443 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1444 isl_drm_modifier_has_aux(parent
->modifier
)) {
1445 /* Auxiliary plane */
1446 dri_format
= parent
->dri_format
;
1447 offset
= parent
->aux_offset
;
1448 stride
= parent
->aux_pitch
;
1449 size
= parent
->aux_size
;
1454 if (offset
+ size
> parent
->bo
->size
) {
1455 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1459 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1463 image
->bo
= parent
->bo
;
1464 brw_bo_reference(parent
->bo
);
1465 image
->modifier
= parent
->modifier
;
1467 image
->width
= width
;
1468 image
->height
= height
;
1469 image
->pitch
= stride
;
1470 image
->offset
= offset
;
1472 intel_image_warn_if_unaligned(image
, __func__
);
1477 static const __DRIimageExtension intelImageExtension
= {
1478 .base
= { __DRI_IMAGE
, 16 },
1480 .createImageFromName
= intel_create_image_from_name
,
1481 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1482 .destroyImage
= intel_destroy_image
,
1483 .createImage
= intel_create_image
,
1484 .queryImage
= intel_query_image
,
1485 .dupImage
= intel_dup_image
,
1486 .validateUsage
= intel_validate_usage
,
1487 .createImageFromNames
= intel_create_image_from_names
,
1488 .fromPlanar
= intel_from_planar
,
1489 .createImageFromTexture
= intel_create_image_from_texture
,
1490 .createImageFromFds
= intel_create_image_from_fds
,
1491 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1493 .getCapabilities
= NULL
,
1494 .mapImage
= intel_map_image
,
1495 .unmapImage
= intel_unmap_image
,
1496 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1497 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1498 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1499 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1500 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1504 get_aperture_size(int fd
)
1506 struct drm_i915_gem_get_aperture aperture
;
1508 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1511 return aperture
.aper_size
;
1515 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1516 int param
, unsigned int *value
)
1518 const struct intel_screen
*const screen
=
1519 (struct intel_screen
*) dri_screen
->driverPrivate
;
1522 case __DRI2_RENDERER_VENDOR_ID
:
1525 case __DRI2_RENDERER_DEVICE_ID
:
1526 value
[0] = screen
->deviceID
;
1528 case __DRI2_RENDERER_ACCELERATED
:
1531 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1532 /* Once a batch uses more than 75% of the maximum mappable size, we
1533 * assume that there's some fragmentation, and we start doing extra
1534 * flushing, etc. That's the big cliff apps will care about.
1536 const unsigned gpu_mappable_megabytes
=
1537 screen
->aperture_threshold
/ (1024 * 1024);
1539 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1540 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1542 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1545 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1546 * (uint64_t) system_page_size
;
1548 const unsigned system_memory_megabytes
=
1549 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1551 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1554 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1557 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1560 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1562 if (brw_hw_context_set_priority(screen
->bufmgr
,
1563 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1564 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1565 if (brw_hw_context_set_priority(screen
->bufmgr
,
1566 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1567 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1568 /* reset to default last, just in case */
1569 if (brw_hw_context_set_priority(screen
->bufmgr
,
1570 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1571 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1573 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1577 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1584 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1585 int param
, const char **value
)
1587 const struct intel_screen
*screen
=
1588 (struct intel_screen
*) dri_screen
->driverPrivate
;
1591 case __DRI2_RENDERER_VENDOR_ID
:
1592 value
[0] = brw_vendor_string
;
1594 case __DRI2_RENDERER_DEVICE_ID
:
1595 value
[0] = brw_get_renderer_string(screen
);
1605 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1606 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1608 const struct intel_screen
*const screen
=
1609 (struct intel_screen
*) dri_screen
->driverPrivate
;
1611 if (!screen
->disk_cache
)
1614 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1617 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1618 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1620 .queryInteger
= brw_query_renderer_integer
,
1621 .queryString
= brw_query_renderer_string
1624 static const __DRIrobustnessExtension dri2Robustness
= {
1625 .base
= { __DRI2_ROBUSTNESS
, 1 }
1628 static const __DRI2blobExtension intelBlobExtension
= {
1629 .base
= { __DRI2_BLOB
, 1 },
1630 .set_cache_funcs
= brw_set_cache_funcs
1633 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1634 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1637 static const __DRIextension
*screenExtensions
[] = {
1638 &intelTexBufferExtension
.base
,
1639 &intelFenceExtension
.base
,
1640 &intelFlushExtension
.base
,
1641 &intelImageExtension
.base
,
1642 &intelRendererQueryExtension
.base
,
1643 &intelMutableRenderBufferExtension
.base
,
1644 &dri2ConfigQueryExtension
.base
,
1645 &dri2NoErrorExtension
.base
,
1646 &intelBlobExtension
.base
,
1650 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1651 &intelTexBufferExtension
.base
,
1652 &intelFenceExtension
.base
,
1653 &intelFlushExtension
.base
,
1654 &intelImageExtension
.base
,
1655 &intelRendererQueryExtension
.base
,
1656 &intelMutableRenderBufferExtension
.base
,
1657 &dri2ConfigQueryExtension
.base
,
1658 &dri2Robustness
.base
,
1659 &dri2NoErrorExtension
.base
,
1660 &intelBlobExtension
.base
,
1665 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1668 struct drm_i915_getparam gp
;
1670 memset(&gp
, 0, sizeof(gp
));
1674 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1677 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1684 intel_get_boolean(struct intel_screen
*screen
, int param
)
1687 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1691 intel_get_integer(struct intel_screen
*screen
, int param
)
1695 if (intel_get_param(screen
, param
, &value
) == 0)
1702 intelDestroyScreen(__DRIscreen
* sPriv
)
1704 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1706 brw_bufmgr_destroy(screen
->bufmgr
);
1707 driDestroyOptionInfo(&screen
->optionCache
);
1709 disk_cache_destroy(screen
->disk_cache
);
1711 ralloc_free(screen
);
1712 sPriv
->driverPrivate
= NULL
;
1717 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1719 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1720 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1721 * this does not allocate GPU memory.
1724 intelCreateBuffer(__DRIscreen
*dri_screen
,
1725 __DRIdrawable
* driDrawPriv
,
1726 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1728 struct intel_renderbuffer
*rb
;
1729 struct intel_screen
*screen
= (struct intel_screen
*)
1730 dri_screen
->driverPrivate
;
1731 mesa_format rgbFormat
;
1732 unsigned num_samples
=
1733 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1738 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1742 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1744 if (screen
->winsys_msaa_samples_override
!= -1) {
1745 num_samples
= screen
->winsys_msaa_samples_override
;
1746 fb
->Visual
.samples
= num_samples
;
1749 if (mesaVis
->redBits
== 16 && mesaVis
->alphaBits
> 0 && mesaVis
->floatMode
) {
1750 rgbFormat
= MESA_FORMAT_RGBA_FLOAT16
;
1751 } else if (mesaVis
->redBits
== 16 && mesaVis
->floatMode
) {
1752 rgbFormat
= MESA_FORMAT_RGBX_FLOAT16
;
1753 } else if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1754 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1755 : MESA_FORMAT_R10G10B10A2_UNORM
;
1756 } else if (mesaVis
->redBits
== 10) {
1757 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1758 : MESA_FORMAT_R10G10B10X2_UNORM
;
1759 } else if (mesaVis
->redBits
== 5) {
1760 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1761 : MESA_FORMAT_B5G6R5_UNORM
;
1762 } else if (mesaVis
->sRGBCapable
) {
1763 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1764 : MESA_FORMAT_B8G8R8A8_SRGB
;
1765 } else if (mesaVis
->alphaBits
== 0) {
1766 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1767 : MESA_FORMAT_B8G8R8X8_UNORM
;
1769 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1770 : MESA_FORMAT_B8G8R8A8_SRGB
;
1771 fb
->Visual
.sRGBCapable
= true;
1774 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1775 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1777 /* setup the hardware-based renderbuffers */
1778 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1779 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1780 rb
->need_srgb
= srgb_cap_set
;
1782 if (mesaVis
->doubleBufferMode
) {
1783 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1784 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1785 rb
->need_srgb
= srgb_cap_set
;
1789 * Assert here that the gl_config has an expected depth/stencil bit
1790 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1791 * which constructs the advertised configs.)
1793 if (mesaVis
->depthBits
== 24) {
1794 assert(mesaVis
->stencilBits
== 8);
1796 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1797 rb
= intel_create_private_renderbuffer(screen
,
1798 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1800 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1801 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1803 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1806 * Use combined depth/stencil. Note that the renderbuffer is
1807 * attached to two attachment points.
1809 rb
= intel_create_private_renderbuffer(screen
,
1810 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1812 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1813 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1816 else if (mesaVis
->depthBits
== 16) {
1817 assert(mesaVis
->stencilBits
== 0);
1818 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1820 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1823 assert(mesaVis
->depthBits
== 0);
1824 assert(mesaVis
->stencilBits
== 0);
1827 /* now add any/all software-based renderbuffers we may need */
1828 _swrast_add_soft_renderbuffers(fb
,
1829 false, /* never sw color */
1830 false, /* never sw depth */
1831 false, /* never sw stencil */
1832 mesaVis
->accumRedBits
> 0,
1833 false, /* never sw alpha */
1834 false /* never sw aux */ );
1835 driDrawPriv
->driverPrivate
= fb
;
1841 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1843 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1845 _mesa_reference_framebuffer(&fb
, NULL
);
1849 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1851 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1852 * gen10, PCI-id is enough to figure it out.
1854 assert(screen
->devinfo
.gen
>= 10);
1858 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1862 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1866 screen
->devinfo
.timestamp_frequency
= freq
;
1870 intel_detect_sseu(struct intel_screen
*screen
)
1872 assert(screen
->devinfo
.gen
>= 8);
1875 screen
->subslice_total
= -1;
1876 screen
->eu_total
= -1;
1878 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1879 &screen
->subslice_total
);
1880 if (ret
< 0 && ret
!= -EINVAL
)
1883 ret
= intel_get_param(screen
,
1884 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1885 if (ret
< 0 && ret
!= -EINVAL
)
1888 /* Without this information, we cannot get the right Braswell brandstrings,
1889 * and we have to use conservative numbers for GPGPU on many platforms, but
1890 * otherwise, things will just work.
1892 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1894 "Kernel 4.1 required to properly query GPU properties.\n");
1899 screen
->subslice_total
= -1;
1900 screen
->eu_total
= -1;
1901 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1905 intel_init_bufmgr(struct intel_screen
*screen
)
1907 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1909 if (getenv("INTEL_NO_HW") != NULL
)
1910 screen
->no_hw
= true;
1912 bool bo_reuse
= false;
1913 int bo_reuse_mode
= driQueryOptioni(&screen
->optionCache
, "bo_reuse");
1914 switch (bo_reuse_mode
) {
1915 case DRI_CONF_BO_REUSE_DISABLED
:
1917 case DRI_CONF_BO_REUSE_ALL
:
1922 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, bo_reuse
);
1923 if (screen
->bufmgr
== NULL
) {
1924 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1925 __func__
, __LINE__
);
1929 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1930 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1938 intel_detect_swizzling(struct intel_screen
*screen
)
1940 /* Broadwell PRM says:
1942 * "Before Gen8, there was a historical configuration control field to
1943 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1944 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1945 * DISP_ARB_CTL[14:13].
1947 * For Gen8 and subsequent generations, the swizzle fields are all
1948 * reserved, and the CPU's memory controller performs all address
1949 * swizzling modifications."
1951 if (screen
->devinfo
.gen
>= 8)
1954 uint32_t tiling
= I915_TILING_X
;
1955 uint32_t swizzle_mode
= 0;
1956 struct brw_bo
*buffer
=
1957 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1958 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1962 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1963 brw_bo_unreference(buffer
);
1965 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1969 intel_detect_timestamp(struct intel_screen
*screen
)
1971 uint64_t dummy
= 0, last
= 0;
1972 int upper
, lower
, loops
;
1974 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1975 * TIMESTAMP register being shifted and the low 32bits always zero.
1977 * More recent kernels offer an interface to read the full 36bits
1980 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1983 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1984 * upper 32bits for a rapidly changing timestamp.
1986 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1990 for (loops
= 0; loops
< 10; loops
++) {
1991 /* The TIMESTAMP should change every 80ns, so several round trips
1992 * through the kernel should be enough to advance it.
1994 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1997 upper
+= (dummy
>> 32) != (last
>> 32);
1998 if (upper
> 1) /* beware 32bit counter overflow */
1999 return 2; /* upper dword holds the low 32bits of the timestamp */
2001 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
2003 return 1; /* timestamp is unshifted */
2008 /* No advancement? No timestamp! */
2013 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2015 * Some combinations of hardware and kernel versions allow this feature,
2016 * while others don't. Instead of trying to enumerate every case, just
2017 * try and write a register and see if works.
2020 intel_detect_pipelined_register(struct intel_screen
*screen
,
2021 int reg
, uint32_t expected_value
, bool reset
)
2026 struct brw_bo
*results
, *bo
;
2028 uint32_t offset
= 0;
2030 bool success
= false;
2032 /* Create a zero'ed temporary buffer for reading our results */
2033 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2034 if (results
== NULL
)
2037 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2041 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2047 /* Write the register. */
2048 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2050 *batch
++ = expected_value
;
2052 /* Save the register's value back to the buffer. */
2053 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2055 struct drm_i915_gem_relocation_entry reloc
= {
2056 .offset
= (char *) batch
- (char *) map
,
2057 .delta
= offset
* sizeof(uint32_t),
2058 .target_handle
= results
->gem_handle
,
2059 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2060 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2062 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2064 /* And afterwards clear the register */
2066 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2071 *batch
++ = MI_BATCH_BUFFER_END
;
2073 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2075 .handle
= results
->gem_handle
,
2078 .handle
= bo
->gem_handle
,
2079 .relocation_count
= 1,
2080 .relocs_ptr
= (uintptr_t) &reloc
,
2084 struct drm_i915_gem_execbuffer2 execbuf
= {
2085 .buffers_ptr
= (uintptr_t) exec_objects
,
2087 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2088 .flags
= I915_EXEC_RENDER
,
2091 /* Don't bother with error checking - if the execbuf fails, the
2092 * value won't be written and we'll just report that there's no access.
2094 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2095 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2097 /* Check whether the value got written. */
2098 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2100 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2101 brw_bo_unmap(results
);
2105 brw_bo_unreference(bo
);
2107 brw_bo_unreference(results
);
2113 intel_detect_pipelined_so(struct intel_screen
*screen
)
2115 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2117 /* Supposedly, Broadwell just works. */
2118 if (devinfo
->gen
>= 8)
2121 if (devinfo
->gen
<= 6)
2124 /* See the big explanation about command parser versions below */
2125 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2128 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2129 * statistics registers), and we already reset it to zero before using it.
2131 return intel_detect_pipelined_register(screen
,
2132 GEN7_SO_WRITE_OFFSET(0),
2138 * Return array of MSAA modes supported by the hardware. The array is
2139 * zero-terminated and sorted in decreasing order.
2142 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2144 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2145 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2146 static const int gen7_modes
[] = {8, 4, 0, -1};
2147 static const int gen6_modes
[] = {4, 0, -1};
2148 static const int gen4_modes
[] = {0, -1};
2150 if (screen
->devinfo
.gen
>= 9) {
2152 } else if (screen
->devinfo
.gen
>= 8) {
2154 } else if (screen
->devinfo
.gen
>= 7) {
2156 } else if (screen
->devinfo
.gen
== 6) {
2164 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2166 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2167 dri_screen
->dri2
.loader
->getCapability
)
2168 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2170 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2171 dri_screen
->image
.loader
->getCapability
)
2172 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2178 intel_allowed_format(__DRIscreen
*dri_screen
, mesa_format format
)
2180 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2182 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2183 bool allow_rgba_ordering
= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
);
2184 if (!allow_rgba_ordering
&&
2185 (format
== MESA_FORMAT_R8G8B8A8_UNORM
||
2186 format
== MESA_FORMAT_R8G8B8X8_UNORM
||
2187 format
== MESA_FORMAT_R8G8B8A8_SRGB
))
2190 /* Shall we expose 10 bpc formats? */
2191 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2192 "allow_rgb10_configs");
2193 if (!allow_rgb10_configs
&&
2194 (format
== MESA_FORMAT_B10G10R10A2_UNORM
||
2195 format
== MESA_FORMAT_B10G10R10X2_UNORM
))
2198 /* Shall we expose 565 formats? */
2199 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2200 "allow_rgb565_configs");
2201 if (!allow_rgb565_configs
&& format
== MESA_FORMAT_B5G6R5_UNORM
)
2204 /* Shall we expose fp16 formats? */
2205 bool allow_fp16_configs
= driQueryOptionb(&screen
->optionCache
,
2206 "allow_fp16_configs");
2207 allow_fp16_configs
&= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_FP16
);
2208 if (!allow_fp16_configs
&&
2209 (format
== MESA_FORMAT_RGBA_FLOAT16
||
2210 format
== MESA_FORMAT_RGBX_FLOAT16
))
2216 static __DRIconfig
**
2217 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2219 static const mesa_format formats
[] = {
2220 MESA_FORMAT_B5G6R5_UNORM
,
2221 MESA_FORMAT_B8G8R8A8_UNORM
,
2222 MESA_FORMAT_B8G8R8X8_UNORM
,
2224 MESA_FORMAT_B8G8R8A8_SRGB
,
2226 /* For 10 bpc, 30 bit depth framebuffers. */
2227 MESA_FORMAT_B10G10R10A2_UNORM
,
2228 MESA_FORMAT_B10G10R10X2_UNORM
,
2230 MESA_FORMAT_RGBA_FLOAT16
,
2231 MESA_FORMAT_RGBX_FLOAT16
,
2233 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2234 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2235 * server may disagree on which format the GLXFBConfig represents,
2236 * resulting in swapped color channels.
2238 * The problem, as of 2017-05-30:
2239 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2240 * order and chooses the first __DRIconfig with the expected channel
2241 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2242 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2244 * EGL does not suffer from this problem. It correctly compares the
2245 * channel masks when matching EGLConfig to __DRIconfig.
2248 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2249 MESA_FORMAT_R8G8B8A8_UNORM
,
2251 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2252 MESA_FORMAT_R8G8B8X8_UNORM
,
2254 MESA_FORMAT_R8G8B8A8_SRGB
,
2257 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2258 static const GLenum back_buffer_modes
[] = {
2259 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2262 static const uint8_t singlesample_samples
[1] = {0};
2264 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2265 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2266 uint8_t depth_bits
[4], stencil_bits
[4];
2267 __DRIconfig
**configs
= NULL
;
2269 unsigned num_formats
= ARRAY_SIZE(formats
);
2271 /* Generate singlesample configs, each without accumulation buffer
2272 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2274 for (unsigned i
= 0; i
< num_formats
; i
++) {
2275 __DRIconfig
**new_configs
;
2276 int num_depth_stencil_bits
= 2;
2278 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2281 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2282 * buffer that has a different number of bits per pixel than the color
2283 * buffer, gen >= 6 supports this.
2286 stencil_bits
[0] = 0;
2288 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2290 stencil_bits
[1] = 0;
2291 if (devinfo
->gen
>= 6) {
2293 stencil_bits
[2] = 8;
2294 num_depth_stencil_bits
= 3;
2298 stencil_bits
[1] = 8;
2301 new_configs
= driCreateConfigs(formats
[i
],
2304 num_depth_stencil_bits
,
2305 back_buffer_modes
, 2,
2306 singlesample_samples
, 1,
2308 /*mutable_render_buffer*/ true);
2309 configs
= driConcatConfigs(configs
, new_configs
);
2312 /* Generate the minimum possible set of configs that include an
2313 * accumulation buffer.
2315 for (unsigned i
= 0; i
< num_formats
; i
++) {
2316 __DRIconfig
**new_configs
;
2318 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2321 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2323 stencil_bits
[0] = 0;
2326 stencil_bits
[0] = 8;
2329 new_configs
= driCreateConfigs(formats
[i
],
2330 depth_bits
, stencil_bits
, 1,
2331 back_buffer_modes
, 1,
2332 singlesample_samples
, 1,
2333 true, false, false);
2334 configs
= driConcatConfigs(configs
, new_configs
);
2337 /* Generate multisample configs.
2339 * This loop breaks early, and hence is a no-op, on gen < 6.
2341 * Multisample configs must follow the singlesample configs in order to
2342 * work around an X server bug present in 1.12. The X server chooses to
2343 * associate the first listed RGBA888-Z24S8 config, regardless of its
2344 * sample count, with the 32-bit depth visual used for compositing.
2346 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2347 * supported. Singlebuffer configs are not supported because no one wants
2350 for (unsigned i
= 0; i
< num_formats
; i
++) {
2351 if (devinfo
->gen
< 6)
2354 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2357 __DRIconfig
**new_configs
;
2358 const int num_depth_stencil_bits
= 2;
2359 int num_msaa_modes
= 0;
2360 const uint8_t *multisample_samples
= NULL
;
2363 stencil_bits
[0] = 0;
2365 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2367 stencil_bits
[1] = 0;
2370 stencil_bits
[1] = 8;
2373 if (devinfo
->gen
>= 9) {
2374 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2375 multisample_samples
= multisample_samples_gen9
;
2376 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2377 } else if (devinfo
->gen
== 8) {
2378 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2379 multisample_samples
= multisample_samples_gen8
;
2380 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2381 } else if (devinfo
->gen
== 7) {
2382 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2383 multisample_samples
= multisample_samples_gen7
;
2384 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2385 } else if (devinfo
->gen
== 6) {
2386 static const uint8_t multisample_samples_gen6
[] = {4};
2387 multisample_samples
= multisample_samples_gen6
;
2388 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2391 new_configs
= driCreateConfigs(formats
[i
],
2394 num_depth_stencil_bits
,
2395 back_buffer_modes
, 1,
2396 multisample_samples
,
2398 false, false, false);
2399 configs
= driConcatConfigs(configs
, new_configs
);
2402 if (configs
== NULL
) {
2403 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2412 set_max_gl_versions(struct intel_screen
*screen
)
2414 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2415 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2417 switch (screen
->devinfo
.gen
) {
2422 dri_screen
->max_gl_core_version
= 46;
2423 dri_screen
->max_gl_compat_version
= 30;
2424 dri_screen
->max_gl_es1_version
= 11;
2425 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2428 dri_screen
->max_gl_core_version
= 33;
2429 if (can_do_pipelined_register_writes(screen
)) {
2430 dri_screen
->max_gl_core_version
= 42;
2431 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2432 dri_screen
->max_gl_core_version
= 43;
2433 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2434 dri_screen
->max_gl_core_version
= 45;
2436 dri_screen
->max_gl_compat_version
= 30;
2437 dri_screen
->max_gl_es1_version
= 11;
2438 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2441 dri_screen
->max_gl_core_version
= 33;
2442 dri_screen
->max_gl_compat_version
= 30;
2443 dri_screen
->max_gl_es1_version
= 11;
2444 dri_screen
->max_gl_es2_version
= 30;
2448 dri_screen
->max_gl_core_version
= 0;
2449 dri_screen
->max_gl_compat_version
= 21;
2450 dri_screen
->max_gl_es1_version
= 11;
2451 dri_screen
->max_gl_es2_version
= 20;
2454 unreachable("unrecognized intel_screen::gen");
2459 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2461 struct brw_context
*brw
= (struct brw_context
*)data
;
2464 va_start(args
, fmt
);
2466 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2467 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2468 MESA_DEBUG_TYPE_OTHER
,
2469 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2474 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2476 struct brw_context
*brw
= (struct brw_context
*)data
;
2479 va_start(args
, fmt
);
2481 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2483 va_copy(args_copy
, args
);
2484 vfprintf(stderr
, fmt
, args_copy
);
2488 if (brw
->perf_debug
) {
2490 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2491 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2492 MESA_DEBUG_TYPE_PERFORMANCE
,
2493 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2499 * This is the driver specific part of the createNewScreen entry point.
2500 * Called when using DRI2.
2502 * \return the struct gl_config supported by this driver
2505 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2507 struct intel_screen
*screen
;
2509 if (dri_screen
->image
.loader
) {
2510 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2511 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2513 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2514 "support required\n");
2518 /* Allocate the private area */
2519 screen
= rzalloc(NULL
, struct intel_screen
);
2521 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2524 /* parse information in __driConfigOptions */
2525 driOptionCache options
;
2526 memset(&options
, 0, sizeof(options
));
2528 driParseOptionInfo(&options
, brw_config_options
.xml
);
2529 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2530 "i965", NULL
, NULL
, 0);
2531 driDestroyOptionCache(&options
);
2533 screen
->driScrnPriv
= dri_screen
;
2534 dri_screen
->driverPrivate
= (void *) screen
;
2536 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2539 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2540 screen
->deviceID
= devinfo
->chipset_id
;
2541 screen
->no_hw
= devinfo
->no_hw
;
2543 if (devinfo
->gen
>= 12) {
2544 fprintf(stderr
, "gen12 and newer are not supported on i965\n");
2548 if (!intel_init_bufmgr(screen
))
2551 brw_process_intel_debug_variable();
2553 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2555 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2556 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2559 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2560 /* Theorectically unlimited! At least for individual objects...
2562 * Currently the entire (global) address space for all GTT maps is
2563 * limited to 64bits. That is all objects on the system that are
2564 * setup for GTT mmapping must fit within 64bits. An attempt to use
2565 * one that exceeds the limit with fail in brw_bo_map_gtt().
2567 * Long before we hit that limit, we will be practically limited by
2568 * that any single object must fit in physical memory (RAM). The upper
2569 * limit on the CPU's address space is currently 48bits (Skylake), of
2570 * which only 39bits can be physical memory. (The GPU itself also has
2571 * a 48bit addressable virtual space.) We can fit over 32 million
2572 * objects of the current maximum allocable size before running out
2575 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2577 /* Estimate the size of the mappable aperture into the GTT. There's an
2578 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2579 * It turns out it's basically always 256MB, though some ancient hardware
2582 uint32_t gtt_size
= 256 * 1024 * 1024;
2584 /* We don't want to map two objects such that a memcpy between them would
2585 * just fault one mapping in and then the other over and over forever. So
2586 * we would need to divide the GTT size by 2. Additionally, some GTT is
2587 * taken up by things like the framebuffer and the ringbuffer and such, so
2588 * be more conservative.
2590 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2593 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2595 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2596 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2598 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2599 screen
->hw_has_swizzling
);
2601 if (devinfo
->gen
>= 10)
2602 intel_cs_timestamp_frequency(screen
);
2604 /* GENs prior to 8 do not support EU/Subslice info */
2605 if (devinfo
->gen
>= 8) {
2606 intel_detect_sseu(screen
);
2607 } else if (devinfo
->gen
== 7) {
2608 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2611 /* Gen7-7.5 kernel requirements / command parser saga:
2614 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2616 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2617 * all batches secure, allowing them to use any feature with no checking.
2618 * This is effectively equivalent to a command parser version of
2619 * \infinity - everything is possible.
2621 * The command parser does not exist, and querying the version will
2625 * The kernel enables the command parser by default, for systems with
2626 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2627 * hardware checker is still enabled, so Haswell and Baytrail cannot
2630 * Ivybridge goes from "everything is possible" to "only what the
2631 * command parser allows" (if the user boots with i915.cmd_parser=0,
2632 * then everything is possible again). We can only safely use features
2633 * allowed by the supported command parser version.
2635 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2636 * implemented by the kernel, even if it's turned off. So, checking
2637 * for version > 0 does not mean that you can write registers. We have
2638 * to try it and see. The version does, however, indicate the age of
2641 * Instead of matching the hardware checker's behavior of converting
2642 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2643 * -EINVAL, making it dangerous to try and use privileged features.
2645 * Effective command parser versions:
2646 * - Haswell: 0 (reporting 1, writes don't work)
2647 * - Baytrail: 0 (reporting 1, writes don't work)
2648 * - Ivybridge: 1 (enabled) or infinite (disabled)
2651 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2652 * effectively version 1 (enabled) or infinite (disabled).
2654 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2655 * Command parser v2 supports predicate writes.
2657 * - Haswell: 0 (reporting 1, writes don't work)
2658 * - Baytrail: 2 (enabled) or infinite (disabled)
2659 * - Ivybridge: 2 (enabled) or infinite (disabled)
2661 * So version >= 2 is enough to know that Ivybridge and Baytrail
2662 * will work. Haswell still can't do anything.
2664 * - v4.0: Version 3 happened. Largely not relevant.
2666 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2667 * L3 config registers are properly saved and restored as part
2668 * of the hardware context. We can approximately detect this point
2669 * in time by checking if I915_PARAM_REVISION is recognized - it
2670 * landed in a later commit, but in the same release cycle.
2672 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2673 * Command parser finally gains secure batch promotion. On Haswell,
2674 * the hardware checker gets disabled, which finally allows it to do
2675 * privileged commands.
2677 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2678 * - Haswell: 3 (enabled) or 0 (disabled)
2679 * - Baytrail: 3 (enabled) or infinite (disabled)
2680 * - Ivybridge: 3 (enabled) or infinite (disabled)
2682 * Unfortunately, detecting this point in time is tricky, because
2683 * no version bump happened when this important change occurred.
2684 * On Haswell, if we can write any register, then the kernel is at
2685 * least this new, and we can start trusting the version number.
2687 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2688 * Command parser reaches version 4, allowing access to Haswell
2689 * atomic scratch and chicken3 registers. If version >= 4, we know
2690 * the kernel is new enough to support privileged features on all
2691 * hardware. However, the user might have disabled it...and the
2692 * kernel will still report version 4. So we still have to guess
2695 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2696 * Command parser v5 whitelists indirect compute shader dispatch
2697 * registers, needed for OpenGL 4.3 and later.
2700 * Command parser v7 lets us use MI_MATH on Haswell.
2702 * Additionally, the kernel begins reporting version 0 when
2703 * the command parser is disabled, allowing us to skip the
2704 * guess-and-check step on Haswell. Unfortunately, this also
2705 * means that we can no longer use it as an indicator of the
2706 * age of the kernel.
2708 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2709 &screen
->cmd_parser_version
) < 0) {
2710 /* Command parser does not exist - getparam is unrecognized */
2711 screen
->cmd_parser_version
= 0;
2714 /* Kernel 4.13 retuired for exec object capture */
2715 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2716 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2719 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2720 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2723 if (!intel_detect_pipelined_so(screen
)) {
2724 /* We can't do anything, so the effective version is 0. */
2725 screen
->cmd_parser_version
= 0;
2727 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2730 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2731 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2733 /* Haswell requires command parser version 4 in order to have L3
2734 * atomic scratch1 and chicken3 bits
2736 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2737 screen
->kernel_features
|=
2738 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2741 /* Haswell requires command parser version 6 in order to write to the
2742 * MI_MATH GPR registers, and version 7 in order to use
2743 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2745 if (devinfo
->gen
>= 8 ||
2746 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2747 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2750 /* Gen7 needs at least command parser version 5 to support compute */
2751 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2752 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2754 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2755 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2757 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2759 screen
->winsys_msaa_samples_override
=
2760 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2761 printf("Forcing winsys sample count to %d\n",
2762 screen
->winsys_msaa_samples_override
);
2764 screen
->winsys_msaa_samples_override
= -1;
2767 set_max_gl_versions(screen
);
2769 /* Notification of GPU resets requires hardware contexts and a kernel new
2770 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2771 * supported, calling it with a context of 0 will either generate EPERM or
2772 * no error. If the ioctl is not supported, it always generate EINVAL.
2773 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2774 * extension to the loader.
2776 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2778 if (devinfo
->gen
>= 6) {
2779 struct drm_i915_reset_stats stats
;
2780 memset(&stats
, 0, sizeof(stats
));
2782 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2784 screen
->has_context_reset_notification
=
2785 (ret
!= -1 || errno
!= EINVAL
);
2788 dri_screen
->extensions
= !screen
->has_context_reset_notification
2789 ? screenExtensions
: intelRobustScreenExtensions
;
2791 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2792 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2793 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2795 /* Changing the meaning of constant buffer pointers from a dynamic state
2796 * offset to an absolute address is only safe if the kernel isolates other
2797 * contexts from our changes.
2799 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2800 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2802 screen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].PositionAlwaysInvariant
= driQueryOptionb(&screen
->optionCache
, "vs_position_always_invariant");
2804 screen
->compiler
->supports_pull_constants
= true;
2805 screen
->compiler
->compact_params
= true;
2807 screen
->has_exec_fence
=
2808 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2810 intel_screen_init_surface_formats(screen
);
2812 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2813 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2815 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2816 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2817 fprintf(stderr
, " - User priority sorting enabled\n");
2818 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2819 fprintf(stderr
, " - Preemption enabled\n");
2823 brw_disk_cache_init(screen
);
2825 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2828 struct intel_buffer
{
2833 static __DRIbuffer
*
2834 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2835 unsigned attachment
, unsigned format
,
2836 int width
, int height
)
2838 struct intel_buffer
*intelBuffer
;
2839 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2841 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2842 attachment
== __DRI_BUFFER_BACK_LEFT
);
2844 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2845 if (intelBuffer
== NULL
)
2848 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2849 * supports Y tiled and compressed buffers, but there is no way to plumb that
2850 * through to here. */
2852 int cpp
= format
/ 8;
2853 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2854 "intelAllocateBuffer",
2859 I915_TILING_X
, &pitch
,
2862 if (intelBuffer
->bo
== NULL
) {
2867 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2869 intelBuffer
->base
.attachment
= attachment
;
2870 intelBuffer
->base
.cpp
= cpp
;
2871 intelBuffer
->base
.pitch
= pitch
;
2873 return &intelBuffer
->base
;
2877 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2879 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2881 brw_bo_unreference(intelBuffer
->bo
);
2885 static const struct __DriverAPIRec brw_driver_api
= {
2886 .InitScreen
= intelInitScreen2
,
2887 .DestroyScreen
= intelDestroyScreen
,
2888 .CreateContext
= brwCreateContext
,
2889 .DestroyContext
= intelDestroyContext
,
2890 .CreateBuffer
= intelCreateBuffer
,
2891 .DestroyBuffer
= intelDestroyBuffer
,
2892 .MakeCurrent
= intelMakeCurrent
,
2893 .UnbindContext
= intelUnbindContext
,
2894 .AllocateBuffer
= intelAllocateBuffer
,
2895 .ReleaseBuffer
= intelReleaseBuffer
2898 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2899 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2900 .vtable
= &brw_driver_api
,
2903 static const __DRIextension
*brw_driver_extensions
[] = {
2904 &driCoreExtension
.base
,
2905 &driImageDriverExtension
.base
,
2906 &driDRI2Extension
.base
,
2908 &brw_config_options
.base
,
2912 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2914 globalDriverAPI
= &brw_driver_api
;
2916 return brw_driver_extensions
;