2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
49 #include "common/gen_defines.h"
51 static const __DRIconfigOptionsExtension brw_config_options
= {
52 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
55 DRI_CONF_SECTION_PERFORMANCE
56 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
57 * DRI_CONF_BO_REUSE_ALL
59 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
60 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
61 DRI_CONF_ENUM(0, "Disable buffer object reuse")
62 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
65 DRI_CONF_MESA_NO_ERROR("false")
66 DRI_CONF_MESA_GLTHREAD("false")
69 DRI_CONF_SECTION_QUALITY
70 DRI_CONF_PRECISE_TRIG("false")
72 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
73 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
74 "given integer. If negative, then do not clamp.")
78 DRI_CONF_SECTION_DEBUG
79 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
80 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
81 DRI_CONF_DISABLE_THROTTLING("false")
82 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
83 DRI_CONF_FORCE_GLSL_VERSION(0)
84 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
85 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
86 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
88 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
89 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
90 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
91 DRI_CONF_FORCE_COMPAT_PROFILE("false")
92 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
94 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
95 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
99 DRI_CONF_SECTION_MISCELLANEOUS
100 DRI_CONF_GLSL_ZERO_INIT("false")
101 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
102 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
103 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
104 DRI_CONF_ALLOW_FP16_CONFIGS("false")
109 #include "intel_batchbuffer.h"
110 #include "intel_buffers.h"
111 #include "brw_bufmgr.h"
112 #include "intel_fbo.h"
113 #include "intel_mipmap_tree.h"
114 #include "intel_screen.h"
115 #include "intel_tex.h"
116 #include "intel_image.h"
118 #include "brw_context.h"
120 #include "drm-uapi/i915_drm.h"
123 * For debugging purposes, this returns a time in seconds.
130 clock_gettime(CLOCK_MONOTONIC
, &tp
);
132 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
135 static const __DRItexBufferExtension intelTexBufferExtension
= {
136 .base
= { __DRI_TEX_BUFFER
, 3 },
138 .setTexBuffer
= intelSetTexBuffer
,
139 .setTexBuffer2
= intelSetTexBuffer2
,
140 .releaseTexBuffer
= intelReleaseTexBuffer
,
144 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
145 __DRIdrawable
*dPriv
,
147 enum __DRI2throttleReason reason
)
149 struct brw_context
*brw
= cPriv
->driverPrivate
;
154 struct gl_context
*ctx
= &brw
->ctx
;
156 _mesa_glthread_finish(ctx
);
158 FLUSH_VERTICES(ctx
, 0);
160 if (flags
& __DRI2_FLUSH_DRAWABLE
)
161 intel_resolve_for_dri2_flush(brw
, dPriv
);
163 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
164 brw
->need_swap_throttle
= true;
165 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
166 brw
->need_flush_throttle
= true;
168 intel_batchbuffer_flush(brw
);
172 * Provides compatibility with loaders that only support the older (version
173 * 1-3) flush interface.
175 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
178 intel_dri2_flush(__DRIdrawable
*drawable
)
180 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
181 __DRI2_FLUSH_DRAWABLE
,
182 __DRI2_THROTTLE_SWAPBUFFER
);
185 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
186 .base
= { __DRI2_FLUSH
, 4 },
188 .flush
= intel_dri2_flush
,
189 .invalidate
= dri2InvalidateDrawable
,
190 .flush_with_flags
= intel_dri2_flush_with_flags
,
193 static const struct intel_image_format intel_image_formats
[] = {
194 { DRM_FORMAT_ABGR16161616F
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F
, 8 } } },
197 { DRM_FORMAT_XBGR16161616F
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F
, 8 } } },
200 { DRM_FORMAT_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
203 { DRM_FORMAT_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
206 { DRM_FORMAT_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
209 { DRM_FORMAT_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
212 { DRM_FORMAT_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { DRM_FORMAT_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { __DRI_IMAGE_FOURCC_SXRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8
, 4 } } },
224 { DRM_FORMAT_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
227 { DRM_FORMAT_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
230 { DRM_FORMAT_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
233 { DRM_FORMAT_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
236 { DRM_FORMAT_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
239 { DRM_FORMAT_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
242 { DRM_FORMAT_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
245 { DRM_FORMAT_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
248 { DRM_FORMAT_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
253 { DRM_FORMAT_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
254 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
258 { DRM_FORMAT_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
259 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
263 { DRM_FORMAT_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
264 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
268 { DRM_FORMAT_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
269 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
273 { DRM_FORMAT_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
274 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
278 { DRM_FORMAT_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
279 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
281 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
283 { DRM_FORMAT_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
284 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
286 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
288 { DRM_FORMAT_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
290 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
291 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
293 { DRM_FORMAT_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
294 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
295 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
296 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
298 { DRM_FORMAT_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
299 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
300 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
302 { DRM_FORMAT_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
303 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
304 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
306 { DRM_FORMAT_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
307 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
308 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
310 { DRM_FORMAT_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
311 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
312 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
314 { DRM_FORMAT_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
315 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
316 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
318 { DRM_FORMAT_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
319 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
321 { DRM_FORMAT_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
322 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
324 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
325 * and treat them as planar buffers in the compositors.
326 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
327 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
328 * clusters and places pairs and places U into the G component and
329 * V into A. This lets the texture sampler interpolate the Y
330 * components correctly when sampling from plane 0, and interpolate
331 * U and V correctly when sampling from plane 1. */
332 { DRM_FORMAT_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
333 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
334 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
335 { DRM_FORMAT_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
336 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
337 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
340 static const struct {
343 } supported_modifiers
[] = {
344 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
345 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
346 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
347 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
351 modifier_is_supported(const struct gen_device_info
*devinfo
,
352 const struct intel_image_format
*fmt
, int dri_format
,
355 const struct isl_drm_modifier_info
*modinfo
=
356 isl_drm_modifier_get_info(modifier
);
359 /* ISL had better know about the modifier */
363 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
364 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
365 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
368 /* CCS_E is not supported for planar images */
369 if (fmt
&& fmt
->nplanes
> 1)
373 assert(dri_format
== 0);
374 dri_format
= fmt
->planes
[0].dri_format
;
377 mesa_format format
= driImageFormatToGLFormat(dri_format
);
378 /* Whether or not we support compression is based on the RGBA non-sRGB
379 * version of the format.
381 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
382 format
= _mesa_get_srgb_format_linear(format
);
383 if (!isl_format_supports_ccs_e(devinfo
,
384 brw_isl_format_for_mesa_format(format
)))
388 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
389 if (supported_modifiers
[i
].modifier
!= modifier
)
392 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
399 tiling_to_modifier(uint32_t tiling
)
401 static const uint64_t map
[] = {
402 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
403 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
404 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
407 assert(tiling
< ARRAY_SIZE(map
));
413 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
415 uint32_t tiling
, swizzle
;
416 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
418 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
419 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
420 func
, image
->offset
);
424 static const struct intel_image_format
*
425 intel_image_format_lookup(int fourcc
)
427 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
428 if (intel_image_formats
[i
].fourcc
== fourcc
)
429 return &intel_image_formats
[i
];
436 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
438 if (image
->planar_format
) {
439 *fourcc
= image
->planar_format
->fourcc
;
443 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
444 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
445 *fourcc
= intel_image_formats
[i
].fourcc
;
453 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
458 image
= calloc(1, sizeof *image
);
462 image
->screen
= screen
;
463 image
->dri_format
= dri_format
;
466 image
->format
= driImageFormatToGLFormat(dri_format
);
467 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
468 image
->format
== MESA_FORMAT_NONE
) {
473 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
474 image
->data
= loaderPrivate
;
480 * Sets up a DRIImage structure to point to a slice out of a miptree.
483 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
484 struct intel_mipmap_tree
*mt
, GLuint level
,
487 intel_miptree_make_shareable(brw
, mt
);
489 intel_miptree_check_level_layer(mt
, level
, zoffset
);
491 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
492 level
- mt
->first_level
);
493 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
494 level
- mt
->first_level
);
495 image
->pitch
= mt
->surf
.row_pitch_B
;
497 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
501 brw_bo_unreference(image
->bo
);
503 brw_bo_reference(mt
->bo
);
507 intel_create_image_from_name(__DRIscreen
*dri_screen
,
508 int width
, int height
, int format
,
509 int name
, int pitch
, void *loaderPrivate
)
511 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
515 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
519 if (image
->format
== MESA_FORMAT_NONE
)
522 cpp
= _mesa_get_format_bytes(image
->format
);
524 image
->width
= width
;
525 image
->height
= height
;
526 image
->pitch
= pitch
* cpp
;
527 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
533 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
539 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
540 int renderbuffer
, void *loaderPrivate
)
543 struct brw_context
*brw
= context
->driverPrivate
;
544 struct gl_context
*ctx
= &brw
->ctx
;
545 struct gl_renderbuffer
*rb
;
546 struct intel_renderbuffer
*irb
;
548 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
550 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
554 irb
= intel_renderbuffer(rb
);
555 intel_miptree_make_shareable(brw
, irb
->mt
);
556 image
= calloc(1, sizeof *image
);
560 image
->internal_format
= rb
->InternalFormat
;
561 image
->format
= rb
->Format
;
562 image
->modifier
= tiling_to_modifier(
563 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
565 image
->data
= loaderPrivate
;
566 brw_bo_unreference(image
->bo
);
567 image
->bo
= irb
->mt
->bo
;
568 brw_bo_reference(irb
->mt
->bo
);
569 image
->width
= rb
->Width
;
570 image
->height
= rb
->Height
;
571 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
572 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
573 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
575 rb
->NeedsFinishRenderTexture
= true;
580 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
581 unsigned texture
, int zoffset
,
587 struct brw_context
*brw
= context
->driverPrivate
;
588 struct gl_texture_object
*obj
;
589 struct intel_texture_object
*iobj
;
592 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
593 if (!obj
|| obj
->Target
!= target
) {
594 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
598 if (target
== GL_TEXTURE_CUBE_MAP
)
601 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
602 iobj
= intel_texture_object(obj
);
603 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
604 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
608 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
609 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
613 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
614 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
617 image
= calloc(1, sizeof *image
);
619 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
623 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
624 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
625 image
->modifier
= tiling_to_modifier(
626 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
627 image
->data
= loaderPrivate
;
628 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
629 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
630 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
631 image
->planar_format
= iobj
->planar_format
;
632 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
633 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
638 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
643 intel_destroy_image(__DRIimage
*image
)
645 brw_bo_unreference(image
->bo
);
649 enum modifier_priority
{
650 MODIFIER_PRIORITY_INVALID
= 0,
651 MODIFIER_PRIORITY_LINEAR
,
654 MODIFIER_PRIORITY_Y_CCS
,
657 const uint64_t priority_to_modifier
[] = {
658 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
659 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
660 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
661 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
662 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
666 select_best_modifier(struct gen_device_info
*devinfo
,
668 const uint64_t *modifiers
,
669 const unsigned count
)
671 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
673 for (int i
= 0; i
< count
; i
++) {
674 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
677 switch (modifiers
[i
]) {
678 case I915_FORMAT_MOD_Y_TILED_CCS
:
679 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
681 case I915_FORMAT_MOD_Y_TILED
:
682 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
684 case I915_FORMAT_MOD_X_TILED
:
685 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
687 case DRM_FORMAT_MOD_LINEAR
:
688 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
690 case DRM_FORMAT_MOD_INVALID
:
696 return priority_to_modifier
[prio
];
700 intel_create_image_common(__DRIscreen
*dri_screen
,
701 int width
, int height
, int format
,
703 const uint64_t *modifiers
,
708 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
709 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
712 /* Callers of this may specify a modifier, or a dri usage, but not both. The
713 * newer modifier interface deprecates the older usage flags.
715 assert(!(use
&& count
));
717 if (use
& __DRI_IMAGE_USE_CURSOR
) {
718 if (width
!= 64 || height
!= 64)
720 modifier
= DRM_FORMAT_MOD_LINEAR
;
723 if (use
& __DRI_IMAGE_USE_LINEAR
)
724 modifier
= DRM_FORMAT_MOD_LINEAR
;
726 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
728 /* User requested specific modifiers */
729 modifier
= select_best_modifier(&screen
->devinfo
, format
,
731 if (modifier
== DRM_FORMAT_MOD_INVALID
)
734 /* Historically, X-tiled was the default, and so lack of modifier means
737 modifier
= I915_FORMAT_MOD_X_TILED
;
741 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
745 const struct isl_drm_modifier_info
*mod_info
=
746 isl_drm_modifier_get_info(modifier
);
748 struct isl_surf surf
;
749 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
750 .dim
= ISL_SURF_DIM_2D
,
751 .format
= brw_isl_format_for_mesa_format(image
->format
),
758 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
759 ISL_SURF_USAGE_TEXTURE_BIT
|
760 ISL_SURF_USAGE_STORAGE_BIT
|
761 ((use
& __DRI_IMAGE_USE_SCANOUT
) ?
762 ISL_SURF_USAGE_DISPLAY_BIT
: 0),
763 .tiling_flags
= (1 << mod_info
->tiling
));
770 struct isl_surf aux_surf
= {0,};
771 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
772 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
, 0);
778 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
782 /* We request that the bufmgr zero the buffer for us for two reasons:
784 * 1) If a buffer gets re-used from the pool, we don't want to leak random
785 * garbage from our process to some other.
787 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
788 * a valid state. A CCS value of 0 indicates that the given block is
789 * in the pass-through state which is what we want.
791 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
792 surf
.size_B
+ aux_surf
.size_B
,
794 isl_tiling_to_i915_tiling(mod_info
->tiling
),
795 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
796 if (image
->bo
== NULL
) {
800 image
->width
= width
;
801 image
->height
= height
;
802 image
->pitch
= surf
.row_pitch_B
;
803 image
->modifier
= modifier
;
805 if (aux_surf
.size_B
) {
806 image
->aux_offset
= surf
.size_B
;
807 image
->aux_pitch
= aux_surf
.row_pitch_B
;
808 image
->aux_size
= aux_surf
.size_B
;
815 intel_create_image(__DRIscreen
*dri_screen
,
816 int width
, int height
, int format
,
820 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
825 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
826 int x0
, int y0
, int width
, int height
,
827 unsigned int flags
, int *stride
, void **map_info
)
829 struct brw_context
*brw
= NULL
;
830 struct brw_bo
*bo
= NULL
;
831 void *raw_data
= NULL
;
836 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
839 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
842 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
845 if (flags
& MAP_INTERNAL_MASK
)
848 brw
= context
->driverPrivate
;
854 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
855 raw_data
= brw_bo_map(brw
, bo
, flags
);
859 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
860 pix_bytes
= _mesa_get_format_bytes(image
->format
);
864 assert(pix_bytes
> 0);
866 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
868 brw_bo_reference(bo
);
870 *stride
= image
->pitch
;
877 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
879 struct brw_bo
*bo
= map_info
;
882 brw_bo_unreference(bo
);
886 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
887 int width
, int height
, int format
,
888 const uint64_t *modifiers
,
889 const unsigned count
,
892 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
893 modifiers
, count
, loaderPrivate
);
897 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
900 case __DRI_IMAGE_ATTRIB_STRIDE
:
901 *value
= image
->pitch
;
903 case __DRI_IMAGE_ATTRIB_HANDLE
:
904 *value
= brw_bo_export_gem_handle(image
->bo
);
906 case __DRI_IMAGE_ATTRIB_NAME
:
907 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
908 case __DRI_IMAGE_ATTRIB_FORMAT
:
909 *value
= image
->dri_format
;
911 case __DRI_IMAGE_ATTRIB_WIDTH
:
912 *value
= image
->width
;
914 case __DRI_IMAGE_ATTRIB_HEIGHT
:
915 *value
= image
->height
;
917 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
918 if (image
->planar_format
== NULL
)
920 *value
= image
->planar_format
->components
;
922 case __DRI_IMAGE_ATTRIB_FD
:
923 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
924 case __DRI_IMAGE_ATTRIB_FOURCC
:
925 return intel_image_get_fourcc(image
, value
);
926 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
927 if (isl_drm_modifier_has_aux(image
->modifier
)) {
928 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
930 } else if (image
->planar_format
) {
931 *value
= image
->planar_format
->nplanes
;
936 case __DRI_IMAGE_ATTRIB_OFFSET
:
937 *value
= image
->offset
;
939 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
940 *value
= (image
->modifier
& 0xffffffff);
942 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
943 *value
= ((image
->modifier
>> 32) & 0xffffffff);
952 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
953 uint32_t fourcc
, uint64_t modifier
,
954 int attrib
, uint64_t *value
)
956 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
957 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
959 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
963 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
964 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
973 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
977 image
= calloc(1, sizeof *image
);
981 brw_bo_reference(orig_image
->bo
);
982 image
->bo
= orig_image
->bo
;
983 image
->internal_format
= orig_image
->internal_format
;
984 image
->planar_format
= orig_image
->planar_format
;
985 image
->dri_format
= orig_image
->dri_format
;
986 image
->format
= orig_image
->format
;
987 image
->modifier
= orig_image
->modifier
;
988 image
->offset
= orig_image
->offset
;
989 image
->width
= orig_image
->width
;
990 image
->height
= orig_image
->height
;
991 image
->pitch
= orig_image
->pitch
;
992 image
->tile_x
= orig_image
->tile_x
;
993 image
->tile_y
= orig_image
->tile_y
;
994 image
->has_depthstencil
= orig_image
->has_depthstencil
;
995 image
->data
= loaderPrivate
;
996 image
->aux_offset
= orig_image
->aux_offset
;
997 image
->aux_pitch
= orig_image
->aux_pitch
;
999 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
1000 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
1006 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
1008 if (use
& __DRI_IMAGE_USE_CURSOR
) {
1009 if (image
->width
!= 64 || image
->height
!= 64)
1017 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1018 int width
, int height
, int fourcc
,
1019 int *names
, int num_names
,
1020 int *strides
, int *offsets
,
1021 void *loaderPrivate
)
1023 const struct intel_image_format
*f
= NULL
;
1027 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1030 f
= intel_image_format_lookup(fourcc
);
1034 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1035 __DRI_IMAGE_FORMAT_NONE
,
1036 names
[0], strides
[0],
1042 image
->planar_format
= f
;
1043 for (i
= 0; i
< f
->nplanes
; i
++) {
1044 index
= f
->planes
[i
].buffer_index
;
1045 image
->offsets
[index
] = offsets
[index
];
1046 image
->strides
[index
] = strides
[index
];
1053 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1054 int width
, int height
, int fourcc
,
1055 uint64_t modifier
, int *fds
, int num_fds
,
1056 int *strides
, int *offsets
,
1057 void *loaderPrivate
)
1059 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1060 const struct intel_image_format
*f
;
1065 if (fds
== NULL
|| num_fds
< 1)
1068 f
= intel_image_format_lookup(fourcc
);
1072 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1073 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1076 if (f
->nplanes
== 1)
1077 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1080 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1086 image
->width
= width
;
1087 image
->height
= height
;
1088 image
->pitch
= strides
[0];
1090 image
->planar_format
= f
;
1092 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1093 const struct isl_drm_modifier_info
*mod_info
=
1094 isl_drm_modifier_get_info(modifier
);
1095 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1096 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1097 tiling
, strides
[0]);
1099 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1102 if (image
->bo
== NULL
) {
1107 /* We only support all planes from the same bo.
1108 * brw_bo_gem_create_from_prime() should return the same pointer for all
1109 * fds received here */
1110 for (i
= 1; i
< num_fds
; i
++) {
1111 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1112 brw_bo_unreference(aux
);
1113 if (aux
!= image
->bo
) {
1114 brw_bo_unreference(image
->bo
);
1120 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1121 image
->modifier
= modifier
;
1123 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1125 const struct isl_drm_modifier_info
*mod_info
=
1126 isl_drm_modifier_get_info(image
->modifier
);
1129 struct isl_surf surf
;
1130 for (i
= 0; i
< f
->nplanes
; i
++) {
1131 index
= f
->planes
[i
].buffer_index
;
1132 image
->offsets
[index
] = offsets
[index
];
1133 image
->strides
[index
] = strides
[index
];
1135 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1136 /* The images we will create are actually based on the RGBA non-sRGB
1137 * version of the format.
1139 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1140 format
= _mesa_get_srgb_format_linear(format
);
1142 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1143 .dim
= ISL_SURF_DIM_2D
,
1144 .format
= brw_isl_format_for_mesa_format(format
),
1145 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1146 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1151 .row_pitch_B
= strides
[index
],
1152 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1153 ISL_SURF_USAGE_TEXTURE_BIT
|
1154 ISL_SURF_USAGE_STORAGE_BIT
,
1155 .tiling_flags
= (1 << mod_info
->tiling
));
1157 brw_bo_unreference(image
->bo
);
1162 const int end
= offsets
[index
] + surf
.size_B
;
1167 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1168 /* Even though we initialize surf in the loop above, we know that
1169 * anything with CCS_E will have exactly one plane so surf is properly
1170 * initialized when we get here.
1172 assert(f
->nplanes
== 1);
1174 image
->aux_offset
= offsets
[1];
1175 image
->aux_pitch
= strides
[1];
1177 /* Scanout hardware requires that the CCS be placed after the main
1178 * surface in memory. We consider any CCS that is placed any earlier in
1179 * memory to be invalid and reject it.
1181 * At some point in the future, this restriction may be relaxed if the
1182 * hardware becomes less strict but we may need a new modifier for that.
1185 if (image
->aux_offset
< size
) {
1186 brw_bo_unreference(image
->bo
);
1191 struct isl_surf aux_surf
= {0,};
1192 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
,
1195 brw_bo_unreference(image
->bo
);
1200 image
->aux_size
= aux_surf
.size_B
;
1202 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1206 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1209 /* Check that the requested image actually fits within the BO. 'size'
1210 * is already relative to the offsets, so we don't need to add that. */
1211 if (image
->bo
->size
== 0) {
1212 image
->bo
->size
= size
;
1213 } else if (size
> image
->bo
->size
) {
1214 brw_bo_unreference(image
->bo
);
1219 if (f
->nplanes
== 1) {
1220 image
->offset
= image
->offsets
[0];
1221 intel_image_warn_if_unaligned(image
, __func__
);
1228 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1229 int width
, int height
, int fourcc
,
1230 int *fds
, int num_fds
, int *strides
, int *offsets
,
1231 void *loaderPrivate
)
1233 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1234 DRM_FORMAT_MOD_INVALID
,
1235 fds
, num_fds
, strides
, offsets
,
1240 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1241 int width
, int height
,
1242 int fourcc
, uint64_t modifier
,
1243 int *fds
, int num_fds
,
1244 int *strides
, int *offsets
,
1245 enum __DRIYUVColorSpace yuv_color_space
,
1246 enum __DRISampleRange sample_range
,
1247 enum __DRIChromaSiting horizontal_siting
,
1248 enum __DRIChromaSiting vertical_siting
,
1250 void *loaderPrivate
)
1253 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1256 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1260 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1262 fds
, num_fds
, strides
, offsets
,
1266 * Invalid parameters and any inconsistencies between are assumed to be
1267 * checked by the caller. Therefore besides unsupported formats one can fail
1268 * only in allocation.
1271 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1275 image
->yuv_color_space
= yuv_color_space
;
1276 image
->sample_range
= sample_range
;
1277 image
->horizontal_siting
= horizontal_siting
;
1278 image
->vertical_siting
= vertical_siting
;
1279 image
->imported_dmabuf
= true;
1281 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1286 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1287 int width
, int height
, int fourcc
,
1288 int *fds
, int num_fds
,
1289 int *strides
, int *offsets
,
1290 enum __DRIYUVColorSpace yuv_color_space
,
1291 enum __DRISampleRange sample_range
,
1292 enum __DRIChromaSiting horizontal_siting
,
1293 enum __DRIChromaSiting vertical_siting
,
1295 void *loaderPrivate
)
1297 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1298 fourcc
, DRM_FORMAT_MOD_INVALID
,
1299 fds
, num_fds
, strides
, offsets
,
1309 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1310 const struct intel_image_format
*fmt
)
1312 /* Currently, all formats with an intel_image_format are available on all
1313 * platforms so there's really nothing to check there.
1317 if (fmt
->nplanes
== 1) {
1318 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1319 /* The images we will create are actually based on the RGBA non-sRGB
1320 * version of the format.
1322 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1323 format
= _mesa_get_srgb_format_linear(format
);
1324 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1325 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1333 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1334 int *formats
, int *count
)
1336 struct intel_screen
*screen
= _screen
->driverPrivate
;
1337 int num_formats
= 0, i
;
1339 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1340 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1341 * in the Linux kernel. We don't want to accidentally advertise them
1342 * them through the EGL layer.
1344 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1345 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
||
1346 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SXRGB8888
)
1349 if (!intel_image_format_is_supported(&screen
->devinfo
,
1350 &intel_image_formats
[i
]))
1357 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1358 if (num_formats
>= max
)
1362 *count
= num_formats
;
1367 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1368 uint64_t *modifiers
,
1369 unsigned int *external_only
,
1372 struct intel_screen
*screen
= _screen
->driverPrivate
;
1373 const struct intel_image_format
*f
;
1374 int num_mods
= 0, i
;
1376 f
= intel_image_format_lookup(fourcc
);
1380 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1383 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1384 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1385 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1392 modifiers
[num_mods
- 1] = modifier
;
1393 if (num_mods
>= max
)
1397 if (external_only
!= NULL
) {
1398 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1399 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1400 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1401 f
->components
== __DRI_IMAGE_COMPONENTS_AYUV
||
1402 f
->components
== __DRI_IMAGE_COMPONENTS_XYUV
||
1403 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1404 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1405 external_only
[i
] = GL_TRUE
;
1408 external_only
[i
] = GL_FALSE
;
1418 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1420 int width
, height
, offset
, stride
, size
, dri_format
;
1426 width
= parent
->width
;
1427 height
= parent
->height
;
1429 const struct intel_image_format
*f
= parent
->planar_format
;
1431 if (f
&& plane
< f
->nplanes
) {
1432 /* Use the planar format definition. */
1433 width
>>= f
->planes
[plane
].width_shift
;
1434 height
>>= f
->planes
[plane
].height_shift
;
1435 dri_format
= f
->planes
[plane
].dri_format
;
1436 int index
= f
->planes
[plane
].buffer_index
;
1437 offset
= parent
->offsets
[index
];
1438 stride
= parent
->strides
[index
];
1439 size
= height
* stride
;
1440 } else if (plane
== 0) {
1441 /* The only plane of a non-planar image: copy the parent definition
1443 dri_format
= parent
->dri_format
;
1444 offset
= parent
->offset
;
1445 stride
= parent
->pitch
;
1446 size
= height
* stride
;
1447 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1448 isl_drm_modifier_has_aux(parent
->modifier
)) {
1449 /* Auxiliary plane */
1450 dri_format
= parent
->dri_format
;
1451 offset
= parent
->aux_offset
;
1452 stride
= parent
->aux_pitch
;
1453 size
= parent
->aux_size
;
1458 if (offset
+ size
> parent
->bo
->size
) {
1459 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1463 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1467 image
->bo
= parent
->bo
;
1468 brw_bo_reference(parent
->bo
);
1469 image
->modifier
= parent
->modifier
;
1471 image
->width
= width
;
1472 image
->height
= height
;
1473 image
->pitch
= stride
;
1474 image
->offset
= offset
;
1476 intel_image_warn_if_unaligned(image
, __func__
);
1481 static const __DRIimageExtension intelImageExtension
= {
1482 .base
= { __DRI_IMAGE
, 16 },
1484 .createImageFromName
= intel_create_image_from_name
,
1485 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1486 .destroyImage
= intel_destroy_image
,
1487 .createImage
= intel_create_image
,
1488 .queryImage
= intel_query_image
,
1489 .dupImage
= intel_dup_image
,
1490 .validateUsage
= intel_validate_usage
,
1491 .createImageFromNames
= intel_create_image_from_names
,
1492 .fromPlanar
= intel_from_planar
,
1493 .createImageFromTexture
= intel_create_image_from_texture
,
1494 .createImageFromFds
= intel_create_image_from_fds
,
1495 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1497 .getCapabilities
= NULL
,
1498 .mapImage
= intel_map_image
,
1499 .unmapImage
= intel_unmap_image
,
1500 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1501 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1502 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1503 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1504 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1508 get_aperture_size(int fd
)
1510 struct drm_i915_gem_get_aperture aperture
;
1512 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1515 return aperture
.aper_size
;
1519 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1520 int param
, unsigned int *value
)
1522 const struct intel_screen
*const screen
=
1523 (struct intel_screen
*) dri_screen
->driverPrivate
;
1526 case __DRI2_RENDERER_VENDOR_ID
:
1529 case __DRI2_RENDERER_DEVICE_ID
:
1530 value
[0] = screen
->deviceID
;
1532 case __DRI2_RENDERER_ACCELERATED
:
1535 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1536 /* Once a batch uses more than 75% of the maximum mappable size, we
1537 * assume that there's some fragmentation, and we start doing extra
1538 * flushing, etc. That's the big cliff apps will care about.
1540 const unsigned gpu_mappable_megabytes
=
1541 screen
->aperture_threshold
/ (1024 * 1024);
1543 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1544 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1546 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1549 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1550 * (uint64_t) system_page_size
;
1552 const unsigned system_memory_megabytes
=
1553 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1555 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1558 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1561 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1564 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1566 if (brw_hw_context_set_priority(screen
->bufmgr
,
1567 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1568 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1569 if (brw_hw_context_set_priority(screen
->bufmgr
,
1570 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1571 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1572 /* reset to default last, just in case */
1573 if (brw_hw_context_set_priority(screen
->bufmgr
,
1574 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1575 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1577 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1581 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1588 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1589 int param
, const char **value
)
1591 const struct intel_screen
*screen
=
1592 (struct intel_screen
*) dri_screen
->driverPrivate
;
1595 case __DRI2_RENDERER_VENDOR_ID
:
1596 value
[0] = brw_vendor_string
;
1598 case __DRI2_RENDERER_DEVICE_ID
:
1599 value
[0] = brw_get_renderer_string(screen
);
1609 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1610 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1612 const struct intel_screen
*const screen
=
1613 (struct intel_screen
*) dri_screen
->driverPrivate
;
1615 if (!screen
->disk_cache
)
1618 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1621 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1622 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1624 .queryInteger
= brw_query_renderer_integer
,
1625 .queryString
= brw_query_renderer_string
1628 static const __DRIrobustnessExtension dri2Robustness
= {
1629 .base
= { __DRI2_ROBUSTNESS
, 1 }
1632 static const __DRI2blobExtension intelBlobExtension
= {
1633 .base
= { __DRI2_BLOB
, 1 },
1634 .set_cache_funcs
= brw_set_cache_funcs
1637 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1638 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1641 static const __DRIextension
*screenExtensions
[] = {
1642 &intelTexBufferExtension
.base
,
1643 &intelFenceExtension
.base
,
1644 &intelFlushExtension
.base
,
1645 &intelImageExtension
.base
,
1646 &intelRendererQueryExtension
.base
,
1647 &intelMutableRenderBufferExtension
.base
,
1648 &dri2ConfigQueryExtension
.base
,
1649 &dri2NoErrorExtension
.base
,
1650 &intelBlobExtension
.base
,
1654 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1655 &intelTexBufferExtension
.base
,
1656 &intelFenceExtension
.base
,
1657 &intelFlushExtension
.base
,
1658 &intelImageExtension
.base
,
1659 &intelRendererQueryExtension
.base
,
1660 &intelMutableRenderBufferExtension
.base
,
1661 &dri2ConfigQueryExtension
.base
,
1662 &dri2Robustness
.base
,
1663 &dri2NoErrorExtension
.base
,
1664 &intelBlobExtension
.base
,
1669 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1672 struct drm_i915_getparam gp
;
1674 memset(&gp
, 0, sizeof(gp
));
1678 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1681 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1688 intel_get_boolean(struct intel_screen
*screen
, int param
)
1691 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1695 intel_get_integer(struct intel_screen
*screen
, int param
)
1699 if (intel_get_param(screen
, param
, &value
) == 0)
1706 intelDestroyScreen(__DRIscreen
* sPriv
)
1708 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1710 brw_bufmgr_destroy(screen
->bufmgr
);
1711 driDestroyOptionInfo(&screen
->optionCache
);
1713 disk_cache_destroy(screen
->disk_cache
);
1715 ralloc_free(screen
);
1716 sPriv
->driverPrivate
= NULL
;
1721 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1723 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1724 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1725 * this does not allocate GPU memory.
1728 intelCreateBuffer(__DRIscreen
*dri_screen
,
1729 __DRIdrawable
* driDrawPriv
,
1730 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1732 struct intel_renderbuffer
*rb
;
1733 struct intel_screen
*screen
= (struct intel_screen
*)
1734 dri_screen
->driverPrivate
;
1735 mesa_format rgbFormat
;
1736 unsigned num_samples
=
1737 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1742 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1746 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1748 if (screen
->winsys_msaa_samples_override
!= -1) {
1749 num_samples
= screen
->winsys_msaa_samples_override
;
1750 fb
->Visual
.samples
= num_samples
;
1753 if (mesaVis
->redBits
== 16 && mesaVis
->alphaBits
> 0 && mesaVis
->floatMode
) {
1754 rgbFormat
= MESA_FORMAT_RGBA_FLOAT16
;
1755 } else if (mesaVis
->redBits
== 16 && mesaVis
->floatMode
) {
1756 rgbFormat
= MESA_FORMAT_RGBX_FLOAT16
;
1757 } else if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1758 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1759 : MESA_FORMAT_R10G10B10A2_UNORM
;
1760 } else if (mesaVis
->redBits
== 10) {
1761 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1762 : MESA_FORMAT_R10G10B10X2_UNORM
;
1763 } else if (mesaVis
->redBits
== 5) {
1764 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1765 : MESA_FORMAT_B5G6R5_UNORM
;
1766 } else if (mesaVis
->alphaBits
== 0) {
1767 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1768 : MESA_FORMAT_B8G8R8X8_SRGB
;
1769 fb
->Visual
.sRGBCapable
= true;
1770 } else if (mesaVis
->sRGBCapable
) {
1771 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1772 : MESA_FORMAT_B8G8R8A8_SRGB
;
1773 fb
->Visual
.sRGBCapable
= true;
1775 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1776 : MESA_FORMAT_B8G8R8A8_SRGB
;
1777 fb
->Visual
.sRGBCapable
= true;
1780 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1781 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1783 /* setup the hardware-based renderbuffers */
1784 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1785 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1786 rb
->need_srgb
= srgb_cap_set
;
1788 if (mesaVis
->doubleBufferMode
) {
1789 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1790 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1791 rb
->need_srgb
= srgb_cap_set
;
1795 * Assert here that the gl_config has an expected depth/stencil bit
1796 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1797 * which constructs the advertised configs.)
1799 if (mesaVis
->depthBits
== 24) {
1800 assert(mesaVis
->stencilBits
== 8);
1802 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1803 rb
= intel_create_private_renderbuffer(screen
,
1804 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1806 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1807 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1809 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1812 * Use combined depth/stencil. Note that the renderbuffer is
1813 * attached to two attachment points.
1815 rb
= intel_create_private_renderbuffer(screen
,
1816 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1818 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1819 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1822 else if (mesaVis
->depthBits
== 16) {
1823 assert(mesaVis
->stencilBits
== 0);
1824 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1826 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1829 assert(mesaVis
->depthBits
== 0);
1830 assert(mesaVis
->stencilBits
== 0);
1833 /* now add any/all software-based renderbuffers we may need */
1834 _swrast_add_soft_renderbuffers(fb
,
1835 false, /* never sw color */
1836 false, /* never sw depth */
1837 false, /* never sw stencil */
1838 mesaVis
->accumRedBits
> 0,
1839 false, /* never sw alpha */
1840 false /* never sw aux */ );
1841 driDrawPriv
->driverPrivate
= fb
;
1847 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1849 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1851 _mesa_reference_framebuffer(&fb
, NULL
);
1855 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1857 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1858 * gen10, PCI-id is enough to figure it out.
1860 assert(screen
->devinfo
.gen
>= 10);
1864 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1868 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1872 screen
->devinfo
.timestamp_frequency
= freq
;
1876 intel_detect_sseu(struct intel_screen
*screen
)
1878 assert(screen
->devinfo
.gen
>= 8);
1881 screen
->subslice_total
= -1;
1882 screen
->eu_total
= -1;
1884 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1885 &screen
->subslice_total
);
1886 if (ret
< 0 && ret
!= -EINVAL
)
1889 ret
= intel_get_param(screen
,
1890 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1891 if (ret
< 0 && ret
!= -EINVAL
)
1894 /* Without this information, we cannot get the right Braswell brandstrings,
1895 * and we have to use conservative numbers for GPGPU on many platforms, but
1896 * otherwise, things will just work.
1898 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1900 "Kernel 4.1 required to properly query GPU properties.\n");
1905 screen
->subslice_total
= -1;
1906 screen
->eu_total
= -1;
1907 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1911 intel_init_bufmgr(struct intel_screen
*screen
)
1913 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1915 if (getenv("INTEL_NO_HW") != NULL
)
1916 screen
->no_hw
= true;
1918 bool bo_reuse
= false;
1919 int bo_reuse_mode
= driQueryOptioni(&screen
->optionCache
, "bo_reuse");
1920 switch (bo_reuse_mode
) {
1921 case DRI_CONF_BO_REUSE_DISABLED
:
1923 case DRI_CONF_BO_REUSE_ALL
:
1928 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, bo_reuse
);
1929 if (screen
->bufmgr
== NULL
) {
1930 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1931 __func__
, __LINE__
);
1935 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1936 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1944 intel_detect_swizzling(struct intel_screen
*screen
)
1946 /* Broadwell PRM says:
1948 * "Before Gen8, there was a historical configuration control field to
1949 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1950 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1951 * DISP_ARB_CTL[14:13].
1953 * For Gen8 and subsequent generations, the swizzle fields are all
1954 * reserved, and the CPU's memory controller performs all address
1955 * swizzling modifications."
1957 if (screen
->devinfo
.gen
>= 8)
1960 uint32_t tiling
= I915_TILING_X
;
1961 uint32_t swizzle_mode
= 0;
1962 struct brw_bo
*buffer
=
1963 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1964 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1968 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1969 brw_bo_unreference(buffer
);
1971 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1975 intel_detect_timestamp(struct intel_screen
*screen
)
1977 uint64_t dummy
= 0, last
= 0;
1978 int upper
, lower
, loops
;
1980 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1981 * TIMESTAMP register being shifted and the low 32bits always zero.
1983 * More recent kernels offer an interface to read the full 36bits
1986 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1989 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1990 * upper 32bits for a rapidly changing timestamp.
1992 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1996 for (loops
= 0; loops
< 10; loops
++) {
1997 /* The TIMESTAMP should change every 80ns, so several round trips
1998 * through the kernel should be enough to advance it.
2000 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
2003 upper
+= (dummy
>> 32) != (last
>> 32);
2004 if (upper
> 1) /* beware 32bit counter overflow */
2005 return 2; /* upper dword holds the low 32bits of the timestamp */
2007 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
2009 return 1; /* timestamp is unshifted */
2014 /* No advancement? No timestamp! */
2019 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2021 * Some combinations of hardware and kernel versions allow this feature,
2022 * while others don't. Instead of trying to enumerate every case, just
2023 * try and write a register and see if works.
2026 intel_detect_pipelined_register(struct intel_screen
*screen
,
2027 int reg
, uint32_t expected_value
, bool reset
)
2032 struct brw_bo
*results
, *bo
;
2034 uint32_t offset
= 0;
2036 bool success
= false;
2038 /* Create a zero'ed temporary buffer for reading our results */
2039 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2040 if (results
== NULL
)
2043 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2047 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2053 /* Write the register. */
2054 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2056 *batch
++ = expected_value
;
2058 /* Save the register's value back to the buffer. */
2059 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2061 struct drm_i915_gem_relocation_entry reloc
= {
2062 .offset
= (char *) batch
- (char *) map
,
2063 .delta
= offset
* sizeof(uint32_t),
2064 .target_handle
= results
->gem_handle
,
2065 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2066 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2068 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2070 /* And afterwards clear the register */
2072 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2077 *batch
++ = MI_BATCH_BUFFER_END
;
2079 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2081 .handle
= results
->gem_handle
,
2084 .handle
= bo
->gem_handle
,
2085 .relocation_count
= 1,
2086 .relocs_ptr
= (uintptr_t) &reloc
,
2090 struct drm_i915_gem_execbuffer2 execbuf
= {
2091 .buffers_ptr
= (uintptr_t) exec_objects
,
2093 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2094 .flags
= I915_EXEC_RENDER
,
2097 /* Don't bother with error checking - if the execbuf fails, the
2098 * value won't be written and we'll just report that there's no access.
2100 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2101 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2103 /* Check whether the value got written. */
2104 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2106 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2107 brw_bo_unmap(results
);
2111 brw_bo_unreference(bo
);
2113 brw_bo_unreference(results
);
2119 intel_detect_pipelined_so(struct intel_screen
*screen
)
2121 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2123 /* Supposedly, Broadwell just works. */
2124 if (devinfo
->gen
>= 8)
2127 if (devinfo
->gen
<= 6)
2130 /* See the big explanation about command parser versions below */
2131 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2134 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2135 * statistics registers), and we already reset it to zero before using it.
2137 return intel_detect_pipelined_register(screen
,
2138 GEN7_SO_WRITE_OFFSET(0),
2144 * Return array of MSAA modes supported by the hardware. The array is
2145 * zero-terminated and sorted in decreasing order.
2148 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2150 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2151 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2152 static const int gen7_modes
[] = {8, 4, 0, -1};
2153 static const int gen6_modes
[] = {4, 0, -1};
2154 static const int gen4_modes
[] = {0, -1};
2156 if (screen
->devinfo
.gen
>= 9) {
2158 } else if (screen
->devinfo
.gen
>= 8) {
2160 } else if (screen
->devinfo
.gen
>= 7) {
2162 } else if (screen
->devinfo
.gen
== 6) {
2170 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2172 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2173 dri_screen
->dri2
.loader
->getCapability
)
2174 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2176 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2177 dri_screen
->image
.loader
->getCapability
)
2178 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2184 intel_allowed_format(__DRIscreen
*dri_screen
, mesa_format format
)
2186 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2188 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2189 bool allow_rgba_ordering
= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
);
2190 if (!allow_rgba_ordering
&&
2191 (format
== MESA_FORMAT_R8G8B8A8_UNORM
||
2192 format
== MESA_FORMAT_R8G8B8X8_UNORM
||
2193 format
== MESA_FORMAT_R8G8B8A8_SRGB
))
2196 /* Shall we expose 10 bpc formats? */
2197 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2198 "allow_rgb10_configs");
2199 if (!allow_rgb10_configs
&&
2200 (format
== MESA_FORMAT_B10G10R10A2_UNORM
||
2201 format
== MESA_FORMAT_B10G10R10X2_UNORM
))
2204 /* Shall we expose 565 formats? */
2205 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2206 "allow_rgb565_configs");
2207 if (!allow_rgb565_configs
&& format
== MESA_FORMAT_B5G6R5_UNORM
)
2210 /* Shall we expose fp16 formats? */
2211 bool allow_fp16_configs
= driQueryOptionb(&screen
->optionCache
,
2212 "allow_fp16_configs");
2213 allow_fp16_configs
&= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_FP16
);
2214 if (!allow_fp16_configs
&&
2215 (format
== MESA_FORMAT_RGBA_FLOAT16
||
2216 format
== MESA_FORMAT_RGBX_FLOAT16
))
2222 static __DRIconfig
**
2223 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2225 static const mesa_format formats
[] = {
2226 MESA_FORMAT_B5G6R5_UNORM
,
2227 MESA_FORMAT_B8G8R8A8_UNORM
,
2228 MESA_FORMAT_B8G8R8X8_UNORM
,
2230 MESA_FORMAT_B8G8R8A8_SRGB
,
2231 MESA_FORMAT_B8G8R8X8_SRGB
,
2233 /* For 10 bpc, 30 bit depth framebuffers. */
2234 MESA_FORMAT_B10G10R10A2_UNORM
,
2235 MESA_FORMAT_B10G10R10X2_UNORM
,
2237 MESA_FORMAT_RGBA_FLOAT16
,
2238 MESA_FORMAT_RGBX_FLOAT16
,
2240 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2241 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2242 * server may disagree on which format the GLXFBConfig represents,
2243 * resulting in swapped color channels.
2245 * The problem, as of 2017-05-30:
2246 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2247 * order and chooses the first __DRIconfig with the expected channel
2248 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2249 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2251 * EGL does not suffer from this problem. It correctly compares the
2252 * channel masks when matching EGLConfig to __DRIconfig.
2255 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2256 MESA_FORMAT_R8G8B8A8_UNORM
,
2258 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2259 MESA_FORMAT_R8G8B8X8_UNORM
,
2261 MESA_FORMAT_R8G8B8A8_SRGB
,
2264 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2265 static const GLenum back_buffer_modes
[] = {
2266 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2269 static const uint8_t singlesample_samples
[1] = {0};
2271 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2272 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2273 uint8_t depth_bits
[4], stencil_bits
[4];
2274 __DRIconfig
**configs
= NULL
;
2276 unsigned num_formats
= ARRAY_SIZE(formats
);
2278 /* Generate singlesample configs, each without accumulation buffer
2279 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2281 for (unsigned i
= 0; i
< num_formats
; i
++) {
2282 __DRIconfig
**new_configs
;
2283 int num_depth_stencil_bits
= 2;
2285 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2288 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2289 * buffer that has a different number of bits per pixel than the color
2290 * buffer, gen >= 6 supports this.
2293 stencil_bits
[0] = 0;
2295 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2297 stencil_bits
[1] = 0;
2298 if (devinfo
->gen
>= 6) {
2300 stencil_bits
[2] = 8;
2301 num_depth_stencil_bits
= 3;
2305 stencil_bits
[1] = 8;
2308 new_configs
= driCreateConfigs(formats
[i
],
2311 num_depth_stencil_bits
,
2312 back_buffer_modes
, 2,
2313 singlesample_samples
, 1,
2315 /*mutable_render_buffer*/ true);
2316 configs
= driConcatConfigs(configs
, new_configs
);
2319 /* Generate the minimum possible set of configs that include an
2320 * accumulation buffer.
2322 for (unsigned i
= 0; i
< num_formats
; i
++) {
2323 __DRIconfig
**new_configs
;
2325 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2328 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2330 stencil_bits
[0] = 0;
2333 stencil_bits
[0] = 8;
2336 new_configs
= driCreateConfigs(formats
[i
],
2337 depth_bits
, stencil_bits
, 1,
2338 back_buffer_modes
, 1,
2339 singlesample_samples
, 1,
2340 true, false, false);
2341 configs
= driConcatConfigs(configs
, new_configs
);
2344 /* Generate multisample configs.
2346 * This loop breaks early, and hence is a no-op, on gen < 6.
2348 * Multisample configs must follow the singlesample configs in order to
2349 * work around an X server bug present in 1.12. The X server chooses to
2350 * associate the first listed RGBA888-Z24S8 config, regardless of its
2351 * sample count, with the 32-bit depth visual used for compositing.
2353 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2354 * supported. Singlebuffer configs are not supported because no one wants
2357 for (unsigned i
= 0; i
< num_formats
; i
++) {
2358 if (devinfo
->gen
< 6)
2361 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2364 __DRIconfig
**new_configs
;
2365 const int num_depth_stencil_bits
= 2;
2366 int num_msaa_modes
= 0;
2367 const uint8_t *multisample_samples
= NULL
;
2370 stencil_bits
[0] = 0;
2372 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2374 stencil_bits
[1] = 0;
2377 stencil_bits
[1] = 8;
2380 if (devinfo
->gen
>= 9) {
2381 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2382 multisample_samples
= multisample_samples_gen9
;
2383 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2384 } else if (devinfo
->gen
== 8) {
2385 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2386 multisample_samples
= multisample_samples_gen8
;
2387 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2388 } else if (devinfo
->gen
== 7) {
2389 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2390 multisample_samples
= multisample_samples_gen7
;
2391 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2392 } else if (devinfo
->gen
== 6) {
2393 static const uint8_t multisample_samples_gen6
[] = {4};
2394 multisample_samples
= multisample_samples_gen6
;
2395 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2398 new_configs
= driCreateConfigs(formats
[i
],
2401 num_depth_stencil_bits
,
2402 back_buffer_modes
, 1,
2403 multisample_samples
,
2405 false, false, false);
2406 configs
= driConcatConfigs(configs
, new_configs
);
2409 if (configs
== NULL
) {
2410 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2419 set_max_gl_versions(struct intel_screen
*screen
)
2421 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2422 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2424 switch (screen
->devinfo
.gen
) {
2429 dri_screen
->max_gl_core_version
= 46;
2430 dri_screen
->max_gl_compat_version
= 30;
2431 dri_screen
->max_gl_es1_version
= 11;
2432 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2435 dri_screen
->max_gl_core_version
= 33;
2436 if (can_do_pipelined_register_writes(screen
)) {
2437 dri_screen
->max_gl_core_version
= 42;
2438 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2439 dri_screen
->max_gl_core_version
= 43;
2440 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2441 dri_screen
->max_gl_core_version
= 45;
2443 dri_screen
->max_gl_compat_version
= 30;
2444 dri_screen
->max_gl_es1_version
= 11;
2445 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2448 dri_screen
->max_gl_core_version
= 33;
2449 dri_screen
->max_gl_compat_version
= 30;
2450 dri_screen
->max_gl_es1_version
= 11;
2451 dri_screen
->max_gl_es2_version
= 30;
2455 dri_screen
->max_gl_core_version
= 0;
2456 dri_screen
->max_gl_compat_version
= 21;
2457 dri_screen
->max_gl_es1_version
= 11;
2458 dri_screen
->max_gl_es2_version
= 20;
2461 unreachable("unrecognized intel_screen::gen");
2466 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2468 struct brw_context
*brw
= (struct brw_context
*)data
;
2471 va_start(args
, fmt
);
2473 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2474 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2475 MESA_DEBUG_TYPE_OTHER
,
2476 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2481 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2483 struct brw_context
*brw
= (struct brw_context
*)data
;
2486 va_start(args
, fmt
);
2488 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2490 va_copy(args_copy
, args
);
2491 vfprintf(stderr
, fmt
, args_copy
);
2495 if (brw
->perf_debug
) {
2497 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2498 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2499 MESA_DEBUG_TYPE_PERFORMANCE
,
2500 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2506 * This is the driver specific part of the createNewScreen entry point.
2507 * Called when using DRI2.
2509 * \return the struct gl_config supported by this driver
2512 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2514 struct intel_screen
*screen
;
2516 if (dri_screen
->image
.loader
) {
2517 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2518 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2520 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2521 "support required\n");
2525 /* Allocate the private area */
2526 screen
= rzalloc(NULL
, struct intel_screen
);
2528 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2531 /* parse information in __driConfigOptions */
2532 driOptionCache options
;
2533 memset(&options
, 0, sizeof(options
));
2535 driParseOptionInfo(&options
, brw_config_options
.xml
);
2536 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2537 "i965", NULL
, NULL
, 0);
2538 driDestroyOptionCache(&options
);
2540 screen
->driScrnPriv
= dri_screen
;
2541 dri_screen
->driverPrivate
= (void *) screen
;
2543 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2546 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2547 screen
->deviceID
= devinfo
->chipset_id
;
2548 screen
->no_hw
= devinfo
->no_hw
;
2550 if (devinfo
->gen
>= 12) {
2551 fprintf(stderr
, "gen12 and newer are not supported on i965\n");
2555 if (!intel_init_bufmgr(screen
))
2558 brw_process_intel_debug_variable();
2560 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2562 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2563 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2566 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2567 /* Theorectically unlimited! At least for individual objects...
2569 * Currently the entire (global) address space for all GTT maps is
2570 * limited to 64bits. That is all objects on the system that are
2571 * setup for GTT mmapping must fit within 64bits. An attempt to use
2572 * one that exceeds the limit with fail in brw_bo_map_gtt().
2574 * Long before we hit that limit, we will be practically limited by
2575 * that any single object must fit in physical memory (RAM). The upper
2576 * limit on the CPU's address space is currently 48bits (Skylake), of
2577 * which only 39bits can be physical memory. (The GPU itself also has
2578 * a 48bit addressable virtual space.) We can fit over 32 million
2579 * objects of the current maximum allocable size before running out
2582 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2584 /* Estimate the size of the mappable aperture into the GTT. There's an
2585 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2586 * It turns out it's basically always 256MB, though some ancient hardware
2589 uint32_t gtt_size
= 256 * 1024 * 1024;
2591 /* We don't want to map two objects such that a memcpy between them would
2592 * just fault one mapping in and then the other over and over forever. So
2593 * we would need to divide the GTT size by 2. Additionally, some GTT is
2594 * taken up by things like the framebuffer and the ringbuffer and such, so
2595 * be more conservative.
2597 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2600 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2602 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2603 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2605 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2606 screen
->hw_has_swizzling
);
2608 if (devinfo
->gen
>= 10)
2609 intel_cs_timestamp_frequency(screen
);
2611 /* GENs prior to 8 do not support EU/Subslice info */
2612 if (devinfo
->gen
>= 8) {
2613 intel_detect_sseu(screen
);
2614 } else if (devinfo
->gen
== 7) {
2615 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2618 /* Gen7-7.5 kernel requirements / command parser saga:
2621 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2623 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2624 * all batches secure, allowing them to use any feature with no checking.
2625 * This is effectively equivalent to a command parser version of
2626 * \infinity - everything is possible.
2628 * The command parser does not exist, and querying the version will
2632 * The kernel enables the command parser by default, for systems with
2633 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2634 * hardware checker is still enabled, so Haswell and Baytrail cannot
2637 * Ivybridge goes from "everything is possible" to "only what the
2638 * command parser allows" (if the user boots with i915.cmd_parser=0,
2639 * then everything is possible again). We can only safely use features
2640 * allowed by the supported command parser version.
2642 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2643 * implemented by the kernel, even if it's turned off. So, checking
2644 * for version > 0 does not mean that you can write registers. We have
2645 * to try it and see. The version does, however, indicate the age of
2648 * Instead of matching the hardware checker's behavior of converting
2649 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2650 * -EINVAL, making it dangerous to try and use privileged features.
2652 * Effective command parser versions:
2653 * - Haswell: 0 (reporting 1, writes don't work)
2654 * - Baytrail: 0 (reporting 1, writes don't work)
2655 * - Ivybridge: 1 (enabled) or infinite (disabled)
2658 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2659 * effectively version 1 (enabled) or infinite (disabled).
2661 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2662 * Command parser v2 supports predicate writes.
2664 * - Haswell: 0 (reporting 1, writes don't work)
2665 * - Baytrail: 2 (enabled) or infinite (disabled)
2666 * - Ivybridge: 2 (enabled) or infinite (disabled)
2668 * So version >= 2 is enough to know that Ivybridge and Baytrail
2669 * will work. Haswell still can't do anything.
2671 * - v4.0: Version 3 happened. Largely not relevant.
2673 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2674 * L3 config registers are properly saved and restored as part
2675 * of the hardware context. We can approximately detect this point
2676 * in time by checking if I915_PARAM_REVISION is recognized - it
2677 * landed in a later commit, but in the same release cycle.
2679 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2680 * Command parser finally gains secure batch promotion. On Haswell,
2681 * the hardware checker gets disabled, which finally allows it to do
2682 * privileged commands.
2684 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2685 * - Haswell: 3 (enabled) or 0 (disabled)
2686 * - Baytrail: 3 (enabled) or infinite (disabled)
2687 * - Ivybridge: 3 (enabled) or infinite (disabled)
2689 * Unfortunately, detecting this point in time is tricky, because
2690 * no version bump happened when this important change occurred.
2691 * On Haswell, if we can write any register, then the kernel is at
2692 * least this new, and we can start trusting the version number.
2694 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2695 * Command parser reaches version 4, allowing access to Haswell
2696 * atomic scratch and chicken3 registers. If version >= 4, we know
2697 * the kernel is new enough to support privileged features on all
2698 * hardware. However, the user might have disabled it...and the
2699 * kernel will still report version 4. So we still have to guess
2702 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2703 * Command parser v5 whitelists indirect compute shader dispatch
2704 * registers, needed for OpenGL 4.3 and later.
2707 * Command parser v7 lets us use MI_MATH on Haswell.
2709 * Additionally, the kernel begins reporting version 0 when
2710 * the command parser is disabled, allowing us to skip the
2711 * guess-and-check step on Haswell. Unfortunately, this also
2712 * means that we can no longer use it as an indicator of the
2713 * age of the kernel.
2715 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2716 &screen
->cmd_parser_version
) < 0) {
2717 /* Command parser does not exist - getparam is unrecognized */
2718 screen
->cmd_parser_version
= 0;
2721 /* Kernel 4.13 retuired for exec object capture */
2722 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2723 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2726 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2727 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2730 if (!intel_detect_pipelined_so(screen
)) {
2731 /* We can't do anything, so the effective version is 0. */
2732 screen
->cmd_parser_version
= 0;
2734 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2737 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2738 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2740 /* Haswell requires command parser version 4 in order to have L3
2741 * atomic scratch1 and chicken3 bits
2743 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2744 screen
->kernel_features
|=
2745 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2748 /* Haswell requires command parser version 6 in order to write to the
2749 * MI_MATH GPR registers, and version 7 in order to use
2750 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2752 if (devinfo
->gen
>= 8 ||
2753 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2754 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2757 /* Gen7 needs at least command parser version 5 to support compute */
2758 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2759 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2761 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2762 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2764 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2766 screen
->winsys_msaa_samples_override
=
2767 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2768 printf("Forcing winsys sample count to %d\n",
2769 screen
->winsys_msaa_samples_override
);
2771 screen
->winsys_msaa_samples_override
= -1;
2774 set_max_gl_versions(screen
);
2776 /* Notification of GPU resets requires hardware contexts and a kernel new
2777 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2778 * supported, calling it with a context of 0 will either generate EPERM or
2779 * no error. If the ioctl is not supported, it always generate EINVAL.
2780 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2781 * extension to the loader.
2783 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2785 if (devinfo
->gen
>= 6) {
2786 struct drm_i915_reset_stats stats
;
2787 memset(&stats
, 0, sizeof(stats
));
2789 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2791 screen
->has_context_reset_notification
=
2792 (ret
!= -1 || errno
!= EINVAL
);
2795 dri_screen
->extensions
= !screen
->has_context_reset_notification
2796 ? screenExtensions
: intelRobustScreenExtensions
;
2798 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2799 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2800 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2802 /* Changing the meaning of constant buffer pointers from a dynamic state
2803 * offset to an absolute address is only safe if the kernel isolates other
2804 * contexts from our changes.
2806 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2807 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2809 screen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].PositionAlwaysInvariant
= driQueryOptionb(&screen
->optionCache
, "vs_position_always_invariant");
2811 screen
->compiler
->supports_pull_constants
= true;
2812 screen
->compiler
->compact_params
= true;
2814 screen
->has_exec_fence
=
2815 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2817 intel_screen_init_surface_formats(screen
);
2819 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2820 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2822 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2823 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2824 fprintf(stderr
, " - User priority sorting enabled\n");
2825 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2826 fprintf(stderr
, " - Preemption enabled\n");
2830 brw_disk_cache_init(screen
);
2832 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2835 struct intel_buffer
{
2840 static __DRIbuffer
*
2841 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2842 unsigned attachment
, unsigned format
,
2843 int width
, int height
)
2845 struct intel_buffer
*intelBuffer
;
2846 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2848 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2849 attachment
== __DRI_BUFFER_BACK_LEFT
);
2851 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2852 if (intelBuffer
== NULL
)
2855 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2856 * supports Y tiled and compressed buffers, but there is no way to plumb that
2857 * through to here. */
2859 int cpp
= format
/ 8;
2860 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2861 "intelAllocateBuffer",
2866 I915_TILING_X
, &pitch
,
2869 if (intelBuffer
->bo
== NULL
) {
2874 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2876 intelBuffer
->base
.attachment
= attachment
;
2877 intelBuffer
->base
.cpp
= cpp
;
2878 intelBuffer
->base
.pitch
= pitch
;
2880 return &intelBuffer
->base
;
2884 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2886 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2888 brw_bo_unreference(intelBuffer
->bo
);
2892 static const struct __DriverAPIRec brw_driver_api
= {
2893 .InitScreen
= intelInitScreen2
,
2894 .DestroyScreen
= intelDestroyScreen
,
2895 .CreateContext
= brwCreateContext
,
2896 .DestroyContext
= intelDestroyContext
,
2897 .CreateBuffer
= intelCreateBuffer
,
2898 .DestroyBuffer
= intelDestroyBuffer
,
2899 .MakeCurrent
= intelMakeCurrent
,
2900 .UnbindContext
= intelUnbindContext
,
2901 .AllocateBuffer
= intelAllocateBuffer
,
2902 .ReleaseBuffer
= intelReleaseBuffer
2905 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2906 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2907 .vtable
= &brw_driver_api
,
2910 static const __DRIextension
*brw_driver_extensions
[] = {
2911 &driCoreExtension
.base
,
2912 &driImageDriverExtension
.base
,
2913 &driDRI2Extension
.base
,
2915 &brw_config_options
.base
,
2919 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2921 globalDriverAPI
= &brw_driver_api
;
2923 return brw_driver_extensions
;