2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
46 #ifndef DRM_FORMAT_MOD_INVALID
47 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
50 #ifndef DRM_FORMAT_MOD_LINEAR
51 #define DRM_FORMAT_MOD_LINEAR 0
54 static const __DRIconfigOptionsExtension brw_config_options
= {
55 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
58 DRI_CONF_SECTION_PERFORMANCE
59 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
60 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
61 * DRI_CONF_BO_REUSE_ALL
63 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
64 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
65 DRI_CONF_ENUM(0, "Disable buffer object reuse")
66 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
71 DRI_CONF_SECTION_QUALITY
72 DRI_CONF_FORCE_S3TC_ENABLE("false")
74 DRI_CONF_PRECISE_TRIG("false")
76 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
77 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
78 "given integer. If negative, then do not clamp.")
82 DRI_CONF_SECTION_DEBUG
83 DRI_CONF_NO_RAST("false")
84 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
85 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
86 DRI_CONF_DISABLE_THROTTLING("false")
87 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
88 DRI_CONF_FORCE_GLSL_VERSION(0)
89 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
90 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
91 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
92 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
93 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
94 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
95 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
97 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
98 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
102 DRI_CONF_SECTION_MISCELLANEOUS
103 DRI_CONF_GLSL_ZERO_INIT("false")
108 #include "intel_batchbuffer.h"
109 #include "intel_buffers.h"
110 #include "brw_bufmgr.h"
111 #include "intel_fbo.h"
112 #include "intel_mipmap_tree.h"
113 #include "intel_screen.h"
114 #include "intel_tex.h"
115 #include "intel_image.h"
117 #include "brw_context.h"
119 #include "i915_drm.h"
122 * For debugging purposes, this returns a time in seconds.
129 clock_gettime(CLOCK_MONOTONIC
, &tp
);
131 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
134 static const __DRItexBufferExtension intelTexBufferExtension
= {
135 .base
= { __DRI_TEX_BUFFER
, 3 },
137 .setTexBuffer
= intelSetTexBuffer
,
138 .setTexBuffer2
= intelSetTexBuffer2
,
139 .releaseTexBuffer
= NULL
,
143 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
144 __DRIdrawable
*dPriv
,
146 enum __DRI2throttleReason reason
)
148 struct brw_context
*brw
= cPriv
->driverPrivate
;
153 struct gl_context
*ctx
= &brw
->ctx
;
155 FLUSH_VERTICES(ctx
, 0);
157 if (flags
& __DRI2_FLUSH_DRAWABLE
)
158 intel_resolve_for_dri2_flush(brw
, dPriv
);
160 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
161 brw
->need_swap_throttle
= true;
162 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
163 brw
->need_flush_throttle
= true;
165 intel_batchbuffer_flush(brw
);
169 * Provides compatibility with loaders that only support the older (version
170 * 1-3) flush interface.
172 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
175 intel_dri2_flush(__DRIdrawable
*drawable
)
177 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
178 __DRI2_FLUSH_DRAWABLE
,
179 __DRI2_THROTTLE_SWAPBUFFER
);
182 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
183 .base
= { __DRI2_FLUSH
, 4 },
185 .flush
= intel_dri2_flush
,
186 .invalidate
= dri2InvalidateDrawable
,
187 .flush_with_flags
= intel_dri2_flush_with_flags
,
190 static struct intel_image_format intel_image_formats
[] = {
191 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
194 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
197 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
200 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
203 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
206 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
209 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
212 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
215 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
218 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
221 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
224 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
227 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
229 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
234 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
239 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
244 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
249 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
269 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
274 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
278 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
279 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
282 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
283 * and treat them as planar buffers in the compositors.
284 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
285 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
286 * clusters and places pairs and places U into the G component and
287 * V into A. This lets the texture sampler interpolate the Y
288 * components correctly when sampling from plane 0, and interpolate
289 * U and V correctly when sampling from plane 1. */
290 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
292 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
293 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
294 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
295 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
298 static const struct {
301 } supported_modifiers
[] = {
302 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
303 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
304 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
308 modifier_is_supported(const struct gen_device_info
*devinfo
,
313 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
314 if (supported_modifiers
[i
].modifier
!= modifier
)
317 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
324 tiling_to_modifier(uint32_t tiling
)
326 static const uint64_t map
[] = {
327 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
328 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
329 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
332 assert(tiling
< ARRAY_SIZE(map
));
338 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
340 uint32_t tiling
, swizzle
;
341 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
343 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
344 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
345 func
, image
->offset
);
349 static struct intel_image_format
*
350 intel_image_format_lookup(int fourcc
)
352 struct intel_image_format
*f
= NULL
;
354 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
355 if (intel_image_formats
[i
].fourcc
== fourcc
) {
356 f
= &intel_image_formats
[i
];
364 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
366 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
367 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
368 *fourcc
= intel_image_formats
[i
].fourcc
;
376 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
381 image
= calloc(1, sizeof *image
);
385 image
->screen
= screen
;
386 image
->dri_format
= dri_format
;
389 image
->format
= driImageFormatToGLFormat(dri_format
);
390 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
391 image
->format
== MESA_FORMAT_NONE
) {
396 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
397 image
->data
= loaderPrivate
;
403 * Sets up a DRIImage structure to point to a slice out of a miptree.
406 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
407 struct intel_mipmap_tree
*mt
, GLuint level
,
410 intel_miptree_make_shareable(brw
, mt
);
412 intel_miptree_check_level_layer(mt
, level
, zoffset
);
414 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
415 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
416 image
->pitch
= mt
->pitch
;
418 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
422 brw_bo_unreference(image
->bo
);
424 brw_bo_reference(mt
->bo
);
428 intel_create_image_from_name(__DRIscreen
*dri_screen
,
429 int width
, int height
, int format
,
430 int name
, int pitch
, void *loaderPrivate
)
432 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
436 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
440 if (image
->format
== MESA_FORMAT_NONE
)
443 cpp
= _mesa_get_format_bytes(image
->format
);
445 image
->width
= width
;
446 image
->height
= height
;
447 image
->pitch
= pitch
* cpp
;
448 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
454 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
460 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
461 int renderbuffer
, void *loaderPrivate
)
464 struct brw_context
*brw
= context
->driverPrivate
;
465 struct gl_context
*ctx
= &brw
->ctx
;
466 struct gl_renderbuffer
*rb
;
467 struct intel_renderbuffer
*irb
;
469 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
471 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
475 irb
= intel_renderbuffer(rb
);
476 intel_miptree_make_shareable(brw
, irb
->mt
);
477 image
= calloc(1, sizeof *image
);
481 image
->internal_format
= rb
->InternalFormat
;
482 image
->format
= rb
->Format
;
483 image
->modifier
= tiling_to_modifier(irb
->mt
->tiling
);
485 image
->data
= loaderPrivate
;
486 brw_bo_unreference(image
->bo
);
487 image
->bo
= irb
->mt
->bo
;
488 brw_bo_reference(irb
->mt
->bo
);
489 image
->width
= rb
->Width
;
490 image
->height
= rb
->Height
;
491 image
->pitch
= irb
->mt
->pitch
;
492 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
493 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
495 rb
->NeedsFinishRenderTexture
= true;
500 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
501 unsigned texture
, int zoffset
,
507 struct brw_context
*brw
= context
->driverPrivate
;
508 struct gl_texture_object
*obj
;
509 struct intel_texture_object
*iobj
;
512 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
513 if (!obj
|| obj
->Target
!= target
) {
514 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
518 if (target
== GL_TEXTURE_CUBE_MAP
)
521 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
522 iobj
= intel_texture_object(obj
);
523 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
524 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
528 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
529 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
533 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
534 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
537 image
= calloc(1, sizeof *image
);
539 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
543 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
544 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
545 image
->modifier
= tiling_to_modifier(iobj
->mt
->tiling
);
546 image
->data
= loaderPrivate
;
547 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
548 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
549 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
550 if (image
->dri_format
== MESA_FORMAT_NONE
) {
551 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
556 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
561 intel_destroy_image(__DRIimage
*image
)
563 brw_bo_unreference(image
->bo
);
567 enum modifier_priority
{
568 MODIFIER_PRIORITY_INVALID
= 0,
569 MODIFIER_PRIORITY_LINEAR
,
574 const uint64_t priority_to_modifier
[] = {
575 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
576 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
577 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
578 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
582 select_best_modifier(struct gen_device_info
*devinfo
,
583 const uint64_t *modifiers
,
584 const unsigned count
)
586 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
588 for (int i
= 0; i
< count
; i
++) {
589 switch (modifiers
[i
]) {
590 case I915_FORMAT_MOD_Y_TILED
:
591 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
593 case I915_FORMAT_MOD_X_TILED
:
594 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
596 case DRM_FORMAT_MOD_LINEAR
:
597 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
599 case DRM_FORMAT_MOD_INVALID
:
605 return priority_to_modifier
[prio
];
609 intel_create_image_common(__DRIscreen
*dri_screen
,
610 int width
, int height
, int format
,
612 const uint64_t *modifiers
,
617 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
618 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
621 /* Callers of this may specify a modifier, or a dri usage, but not both. The
622 * newer modifier interface deprecates the older usage flags newer modifier
623 * interface deprecates the older usage flags.
625 assert(!(use
&& count
));
627 if (use
& __DRI_IMAGE_USE_CURSOR
) {
628 if (width
!= 64 || height
!= 64)
630 modifier
= DRM_FORMAT_MOD_LINEAR
;
633 if (use
& __DRI_IMAGE_USE_LINEAR
)
634 modifier
= DRM_FORMAT_MOD_LINEAR
;
636 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
638 /* User requested specific modifiers */
639 modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
640 if (modifier
== DRM_FORMAT_MOD_INVALID
)
643 /* Historically, X-tiled was the default, and so lack of modifier means
646 modifier
= I915_FORMAT_MOD_X_TILED
;
650 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
654 const struct isl_drm_modifier_info
*mod_info
=
655 isl_drm_modifier_get_info(modifier
);
657 struct isl_surf surf
;
658 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
659 .dim
= ISL_SURF_DIM_2D
,
660 .format
= brw_isl_format_for_mesa_format(image
->format
),
667 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
668 ISL_SURF_USAGE_TEXTURE_BIT
|
669 ISL_SURF_USAGE_STORAGE_BIT
,
670 .tiling_flags
= (1 << mod_info
->tiling
));
677 /* We request that the bufmgr zero because, if a buffer gets re-used from
678 * the pool, we don't want to leak random garbage from our process to some
681 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image", surf
.size
,
682 isl_tiling_to_i915_tiling(mod_info
->tiling
),
683 surf
.row_pitch
, BO_ALLOC_ZEROED
);
684 if (image
->bo
== NULL
) {
688 image
->width
= width
;
689 image
->height
= height
;
690 image
->pitch
= surf
.row_pitch
;
691 image
->modifier
= modifier
;
697 intel_create_image(__DRIscreen
*dri_screen
,
698 int width
, int height
, int format
,
702 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
707 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
708 int width
, int height
, int format
,
709 const uint64_t *modifiers
,
710 const unsigned count
,
713 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
714 modifiers
, count
, loaderPrivate
);
718 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
721 case __DRI_IMAGE_ATTRIB_STRIDE
:
722 *value
= image
->pitch
;
724 case __DRI_IMAGE_ATTRIB_HANDLE
:
725 *value
= image
->bo
->gem_handle
;
727 case __DRI_IMAGE_ATTRIB_NAME
:
728 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
729 case __DRI_IMAGE_ATTRIB_FORMAT
:
730 *value
= image
->dri_format
;
732 case __DRI_IMAGE_ATTRIB_WIDTH
:
733 *value
= image
->width
;
735 case __DRI_IMAGE_ATTRIB_HEIGHT
:
736 *value
= image
->height
;
738 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
739 if (image
->planar_format
== NULL
)
741 *value
= image
->planar_format
->components
;
743 case __DRI_IMAGE_ATTRIB_FD
:
744 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
745 case __DRI_IMAGE_ATTRIB_FOURCC
:
746 return intel_lookup_fourcc(image
->dri_format
, value
);
747 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
750 case __DRI_IMAGE_ATTRIB_OFFSET
:
751 *value
= image
->offset
;
753 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
754 *value
= (image
->modifier
& 0xffffffff);
756 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
757 *value
= ((image
->modifier
>> 32) & 0xffffffff);
766 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
770 image
= calloc(1, sizeof *image
);
774 brw_bo_reference(orig_image
->bo
);
775 image
->bo
= orig_image
->bo
;
776 image
->internal_format
= orig_image
->internal_format
;
777 image
->planar_format
= orig_image
->planar_format
;
778 image
->dri_format
= orig_image
->dri_format
;
779 image
->format
= orig_image
->format
;
780 image
->modifier
= orig_image
->modifier
;
781 image
->offset
= orig_image
->offset
;
782 image
->width
= orig_image
->width
;
783 image
->height
= orig_image
->height
;
784 image
->pitch
= orig_image
->pitch
;
785 image
->tile_x
= orig_image
->tile_x
;
786 image
->tile_y
= orig_image
->tile_y
;
787 image
->has_depthstencil
= orig_image
->has_depthstencil
;
788 image
->data
= loaderPrivate
;
790 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
791 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
797 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
799 if (use
& __DRI_IMAGE_USE_CURSOR
) {
800 if (image
->width
!= 64 || image
->height
!= 64)
808 intel_create_image_from_names(__DRIscreen
*dri_screen
,
809 int width
, int height
, int fourcc
,
810 int *names
, int num_names
,
811 int *strides
, int *offsets
,
814 struct intel_image_format
*f
= NULL
;
818 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
821 f
= intel_image_format_lookup(fourcc
);
825 image
= intel_create_image_from_name(dri_screen
, width
, height
,
826 __DRI_IMAGE_FORMAT_NONE
,
827 names
[0], strides
[0],
833 image
->planar_format
= f
;
834 for (i
= 0; i
< f
->nplanes
; i
++) {
835 index
= f
->planes
[i
].buffer_index
;
836 image
->offsets
[index
] = offsets
[index
];
837 image
->strides
[index
] = strides
[index
];
844 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
845 int width
, int height
, int fourcc
,
846 uint64_t modifier
, int *fds
, int num_fds
,
847 int *strides
, int *offsets
,
850 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
851 struct intel_image_format
*f
;
856 if (fds
== NULL
|| num_fds
< 1)
859 f
= intel_image_format_lookup(fourcc
);
863 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
864 !modifier_is_supported(&screen
->devinfo
, modifier
))
868 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
871 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
877 image
->width
= width
;
878 image
->height
= height
;
879 image
->pitch
= strides
[0];
881 image
->planar_format
= f
;
883 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
884 if (image
->bo
== NULL
) {
889 /* We only support all planes from the same bo.
890 * brw_bo_gem_create_from_prime() should return the same pointer for all
891 * fds received here */
892 for (i
= 1; i
< num_fds
; i
++) {
893 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
894 brw_bo_unreference(aux
);
895 if (aux
!= image
->bo
) {
896 brw_bo_unreference(image
->bo
);
902 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
903 image
->modifier
= modifier
;
905 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
908 for (i
= 0; i
< f
->nplanes
; i
++) {
909 index
= f
->planes
[i
].buffer_index
;
910 image
->offsets
[index
] = offsets
[index
];
911 image
->strides
[index
] = strides
[index
];
913 const struct isl_drm_modifier_info
*mod_info
=
914 isl_drm_modifier_get_info(image
->modifier
);
916 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
918 struct isl_surf surf
;
919 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
920 .dim
= ISL_SURF_DIM_2D
,
921 .format
= brw_isl_format_for_mesa_format(format
),
922 .width
= image
->width
>> f
->planes
[i
].width_shift
,
923 .height
= image
->height
>> f
->planes
[i
].height_shift
,
928 .row_pitch
= strides
[index
],
929 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
930 ISL_SURF_USAGE_TEXTURE_BIT
|
931 ISL_SURF_USAGE_STORAGE_BIT
,
932 .tiling_flags
= (1 << mod_info
->tiling
));
934 brw_bo_unreference(image
->bo
);
939 const int end
= offsets
[index
] + surf
.size
;
944 /* Check that the requested image actually fits within the BO. 'size'
945 * is already relative to the offsets, so we don't need to add that. */
946 if (image
->bo
->size
== 0) {
947 image
->bo
->size
= size
;
948 } else if (size
> image
->bo
->size
) {
949 brw_bo_unreference(image
->bo
);
954 if (f
->nplanes
== 1) {
955 image
->offset
= image
->offsets
[0];
956 intel_image_warn_if_unaligned(image
, __func__
);
963 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
964 int width
, int height
, int fourcc
,
965 int *fds
, int num_fds
, int *strides
, int *offsets
,
968 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
969 DRM_FORMAT_MOD_INVALID
,
970 fds
, num_fds
, strides
, offsets
,
975 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
976 int width
, int height
,
977 int fourcc
, uint64_t modifier
,
978 int *fds
, int num_fds
,
979 int *strides
, int *offsets
,
980 enum __DRIYUVColorSpace yuv_color_space
,
981 enum __DRISampleRange sample_range
,
982 enum __DRIChromaSiting horizontal_siting
,
983 enum __DRIChromaSiting vertical_siting
,
988 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
991 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
995 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
997 fds
, num_fds
, strides
, offsets
,
1001 * Invalid parameters and any inconsistencies between are assumed to be
1002 * checked by the caller. Therefore besides unsupported formats one can fail
1003 * only in allocation.
1006 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1010 image
->dma_buf_imported
= true;
1011 image
->yuv_color_space
= yuv_color_space
;
1012 image
->sample_range
= sample_range
;
1013 image
->horizontal_siting
= horizontal_siting
;
1014 image
->vertical_siting
= vertical_siting
;
1016 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1021 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1022 int width
, int height
, int fourcc
,
1023 int *fds
, int num_fds
,
1024 int *strides
, int *offsets
,
1025 enum __DRIYUVColorSpace yuv_color_space
,
1026 enum __DRISampleRange sample_range
,
1027 enum __DRIChromaSiting horizontal_siting
,
1028 enum __DRIChromaSiting vertical_siting
,
1030 void *loaderPrivate
)
1032 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1033 fourcc
, DRM_FORMAT_MOD_INVALID
,
1034 fds
, num_fds
, strides
, offsets
,
1044 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1045 int *formats
, int *count
)
1050 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1054 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1055 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1057 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1065 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1066 uint64_t *modifiers
,
1067 unsigned int *external_only
,
1070 struct intel_screen
*screen
= _screen
->driverPrivate
;
1071 struct intel_image_format
*f
;
1072 int num_mods
= 0, i
;
1074 f
= intel_image_format_lookup(fourcc
);
1078 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1079 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1080 if (!modifier_is_supported(&screen
->devinfo
, modifier
))
1087 modifiers
[num_mods
- 1] = modifier
;
1088 if (num_mods
>= max
)
1092 if (external_only
!= NULL
) {
1093 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1094 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1095 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1096 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1097 external_only
[i
] = GL_TRUE
;
1100 external_only
[i
] = GL_FALSE
;
1110 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1112 int width
, height
, offset
, stride
, dri_format
, index
;
1113 struct intel_image_format
*f
;
1116 if (parent
== NULL
|| parent
->planar_format
== NULL
)
1119 f
= parent
->planar_format
;
1121 if (plane
>= f
->nplanes
)
1124 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1125 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1126 dri_format
= f
->planes
[plane
].dri_format
;
1127 index
= f
->planes
[plane
].buffer_index
;
1128 offset
= parent
->offsets
[index
];
1129 stride
= parent
->strides
[index
];
1131 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1135 if (offset
+ height
* stride
> parent
->bo
->size
) {
1136 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1141 image
->bo
= parent
->bo
;
1142 brw_bo_reference(parent
->bo
);
1143 image
->modifier
= parent
->modifier
;
1145 image
->width
= width
;
1146 image
->height
= height
;
1147 image
->pitch
= stride
;
1148 image
->offset
= offset
;
1150 intel_image_warn_if_unaligned(image
, __func__
);
1155 static const __DRIimageExtension intelImageExtension
= {
1156 .base
= { __DRI_IMAGE
, 15 },
1158 .createImageFromName
= intel_create_image_from_name
,
1159 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1160 .destroyImage
= intel_destroy_image
,
1161 .createImage
= intel_create_image
,
1162 .queryImage
= intel_query_image
,
1163 .dupImage
= intel_dup_image
,
1164 .validateUsage
= intel_validate_usage
,
1165 .createImageFromNames
= intel_create_image_from_names
,
1166 .fromPlanar
= intel_from_planar
,
1167 .createImageFromTexture
= intel_create_image_from_texture
,
1168 .createImageFromFds
= intel_create_image_from_fds
,
1169 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1171 .getCapabilities
= NULL
,
1174 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1175 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1176 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1177 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1181 get_aperture_size(int fd
)
1183 struct drm_i915_gem_get_aperture aperture
;
1185 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1188 return aperture
.aper_size
;
1192 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1193 int param
, unsigned int *value
)
1195 const struct intel_screen
*const screen
=
1196 (struct intel_screen
*) dri_screen
->driverPrivate
;
1199 case __DRI2_RENDERER_VENDOR_ID
:
1202 case __DRI2_RENDERER_DEVICE_ID
:
1203 value
[0] = screen
->deviceID
;
1205 case __DRI2_RENDERER_ACCELERATED
:
1208 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1209 /* Once a batch uses more than 75% of the maximum mappable size, we
1210 * assume that there's some fragmentation, and we start doing extra
1211 * flushing, etc. That's the big cliff apps will care about.
1213 const unsigned gpu_mappable_megabytes
=
1214 screen
->aperture_threshold
/ (1024 * 1024);
1216 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1217 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1219 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1222 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1223 * (uint64_t) system_page_size
;
1225 const unsigned system_memory_megabytes
=
1226 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1228 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1231 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1234 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1238 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1245 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1246 int param
, const char **value
)
1248 const struct intel_screen
*screen
=
1249 (struct intel_screen
*) dri_screen
->driverPrivate
;
1252 case __DRI2_RENDERER_VENDOR_ID
:
1253 value
[0] = brw_vendor_string
;
1255 case __DRI2_RENDERER_DEVICE_ID
:
1256 value
[0] = brw_get_renderer_string(screen
);
1265 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1266 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1268 .queryInteger
= brw_query_renderer_integer
,
1269 .queryString
= brw_query_renderer_string
1272 static const __DRIrobustnessExtension dri2Robustness
= {
1273 .base
= { __DRI2_ROBUSTNESS
, 1 }
1276 static const __DRIextension
*screenExtensions
[] = {
1277 &intelTexBufferExtension
.base
,
1278 &intelFenceExtension
.base
,
1279 &intelFlushExtension
.base
,
1280 &intelImageExtension
.base
,
1281 &intelRendererQueryExtension
.base
,
1282 &dri2ConfigQueryExtension
.base
,
1283 &dri2NoErrorExtension
.base
,
1287 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1288 &intelTexBufferExtension
.base
,
1289 &intelFenceExtension
.base
,
1290 &intelFlushExtension
.base
,
1291 &intelImageExtension
.base
,
1292 &intelRendererQueryExtension
.base
,
1293 &dri2ConfigQueryExtension
.base
,
1294 &dri2Robustness
.base
,
1295 &dri2NoErrorExtension
.base
,
1300 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1303 struct drm_i915_getparam gp
;
1305 memset(&gp
, 0, sizeof(gp
));
1309 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1312 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1319 intel_get_boolean(struct intel_screen
*screen
, int param
)
1322 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1326 intel_get_integer(struct intel_screen
*screen
, int param
)
1330 if (intel_get_param(screen
, param
, &value
) == 0)
1337 intelDestroyScreen(__DRIscreen
* sPriv
)
1339 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1341 brw_bufmgr_destroy(screen
->bufmgr
);
1342 driDestroyOptionInfo(&screen
->optionCache
);
1344 ralloc_free(screen
);
1345 sPriv
->driverPrivate
= NULL
;
1350 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1352 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1353 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1354 * this does not allocate GPU memory.
1357 intelCreateBuffer(__DRIscreen
*dri_screen
,
1358 __DRIdrawable
* driDrawPriv
,
1359 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1361 struct intel_renderbuffer
*rb
;
1362 struct intel_screen
*screen
= (struct intel_screen
*)
1363 dri_screen
->driverPrivate
;
1364 mesa_format rgbFormat
;
1365 unsigned num_samples
=
1366 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1371 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1375 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1377 if (screen
->winsys_msaa_samples_override
!= -1) {
1378 num_samples
= screen
->winsys_msaa_samples_override
;
1379 fb
->Visual
.samples
= num_samples
;
1382 if (mesaVis
->redBits
== 5) {
1383 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1384 : MESA_FORMAT_B5G6R5_UNORM
;
1385 } else if (mesaVis
->sRGBCapable
) {
1386 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1387 : MESA_FORMAT_B8G8R8A8_SRGB
;
1388 } else if (mesaVis
->alphaBits
== 0) {
1389 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1390 : MESA_FORMAT_B8G8R8X8_UNORM
;
1392 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1393 : MESA_FORMAT_B8G8R8A8_SRGB
;
1394 fb
->Visual
.sRGBCapable
= true;
1397 /* setup the hardware-based renderbuffers */
1398 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1399 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1401 if (mesaVis
->doubleBufferMode
) {
1402 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1403 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1407 * Assert here that the gl_config has an expected depth/stencil bit
1408 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1409 * which constructs the advertised configs.)
1411 if (mesaVis
->depthBits
== 24) {
1412 assert(mesaVis
->stencilBits
== 8);
1414 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1415 rb
= intel_create_private_renderbuffer(screen
,
1416 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1418 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1419 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1421 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1424 * Use combined depth/stencil. Note that the renderbuffer is
1425 * attached to two attachment points.
1427 rb
= intel_create_private_renderbuffer(screen
,
1428 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1430 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1431 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1434 else if (mesaVis
->depthBits
== 16) {
1435 assert(mesaVis
->stencilBits
== 0);
1436 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1438 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1441 assert(mesaVis
->depthBits
== 0);
1442 assert(mesaVis
->stencilBits
== 0);
1445 /* now add any/all software-based renderbuffers we may need */
1446 _swrast_add_soft_renderbuffers(fb
,
1447 false, /* never sw color */
1448 false, /* never sw depth */
1449 false, /* never sw stencil */
1450 mesaVis
->accumRedBits
> 0,
1451 false, /* never sw alpha */
1452 false /* never sw aux */ );
1453 driDrawPriv
->driverPrivate
= fb
;
1459 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1461 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1463 _mesa_reference_framebuffer(&fb
, NULL
);
1467 intel_detect_sseu(struct intel_screen
*screen
)
1469 assert(screen
->devinfo
.gen
>= 8);
1472 screen
->subslice_total
= -1;
1473 screen
->eu_total
= -1;
1475 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1476 &screen
->subslice_total
);
1477 if (ret
< 0 && ret
!= -EINVAL
)
1480 ret
= intel_get_param(screen
,
1481 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1482 if (ret
< 0 && ret
!= -EINVAL
)
1485 /* Without this information, we cannot get the right Braswell brandstrings,
1486 * and we have to use conservative numbers for GPGPU on many platforms, but
1487 * otherwise, things will just work.
1489 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1491 "Kernel 4.1 required to properly query GPU properties.\n");
1496 screen
->subslice_total
= -1;
1497 screen
->eu_total
= -1;
1498 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1502 intel_init_bufmgr(struct intel_screen
*screen
)
1504 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1506 if (getenv("INTEL_NO_HW") != NULL
)
1507 screen
->no_hw
= true;
1509 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1510 if (screen
->bufmgr
== NULL
) {
1511 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1512 __func__
, __LINE__
);
1516 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1517 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1525 intel_detect_swizzling(struct intel_screen
*screen
)
1527 struct brw_bo
*buffer
;
1529 uint32_t aligned_pitch
;
1530 uint32_t tiling
= I915_TILING_X
;
1531 uint32_t swizzle_mode
= 0;
1533 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1534 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1538 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1539 brw_bo_unreference(buffer
);
1541 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1548 intel_detect_timestamp(struct intel_screen
*screen
)
1550 uint64_t dummy
= 0, last
= 0;
1551 int upper
, lower
, loops
;
1553 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1554 * TIMESTAMP register being shifted and the low 32bits always zero.
1556 * More recent kernels offer an interface to read the full 36bits
1559 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1562 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1563 * upper 32bits for a rapidly changing timestamp.
1565 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1569 for (loops
= 0; loops
< 10; loops
++) {
1570 /* The TIMESTAMP should change every 80ns, so several round trips
1571 * through the kernel should be enough to advance it.
1573 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1576 upper
+= (dummy
>> 32) != (last
>> 32);
1577 if (upper
> 1) /* beware 32bit counter overflow */
1578 return 2; /* upper dword holds the low 32bits of the timestamp */
1580 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1582 return 1; /* timestamp is unshifted */
1587 /* No advancement? No timestamp! */
1592 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1594 * Some combinations of hardware and kernel versions allow this feature,
1595 * while others don't. Instead of trying to enumerate every case, just
1596 * try and write a register and see if works.
1599 intel_detect_pipelined_register(struct intel_screen
*screen
,
1600 int reg
, uint32_t expected_value
, bool reset
)
1605 struct brw_bo
*results
, *bo
;
1607 uint32_t offset
= 0;
1609 bool success
= false;
1611 /* Create a zero'ed temporary buffer for reading our results */
1612 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1613 if (results
== NULL
)
1616 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1620 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1626 /* Write the register. */
1627 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1629 *batch
++ = expected_value
;
1631 /* Save the register's value back to the buffer. */
1632 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1634 struct drm_i915_gem_relocation_entry reloc
= {
1635 .offset
= (char *) batch
- (char *) map
,
1636 .delta
= offset
* sizeof(uint32_t),
1637 .target_handle
= results
->gem_handle
,
1638 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1639 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1641 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1643 /* And afterwards clear the register */
1645 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1650 *batch
++ = MI_BATCH_BUFFER_END
;
1652 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1654 .handle
= results
->gem_handle
,
1657 .handle
= bo
->gem_handle
,
1658 .relocation_count
= 1,
1659 .relocs_ptr
= (uintptr_t) &reloc
,
1663 struct drm_i915_gem_execbuffer2 execbuf
= {
1664 .buffers_ptr
= (uintptr_t) exec_objects
,
1666 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1667 .flags
= I915_EXEC_RENDER
,
1670 /* Don't bother with error checking - if the execbuf fails, the
1671 * value won't be written and we'll just report that there's no access.
1673 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1674 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1676 /* Check whether the value got written. */
1677 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1679 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1680 brw_bo_unmap(results
);
1684 brw_bo_unreference(bo
);
1686 brw_bo_unreference(results
);
1692 intel_detect_pipelined_so(struct intel_screen
*screen
)
1694 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1696 /* Supposedly, Broadwell just works. */
1697 if (devinfo
->gen
>= 8)
1700 if (devinfo
->gen
<= 6)
1703 /* See the big explanation about command parser versions below */
1704 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1707 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1708 * statistics registers), and we already reset it to zero before using it.
1710 return intel_detect_pipelined_register(screen
,
1711 GEN7_SO_WRITE_OFFSET(0),
1717 * Return array of MSAA modes supported by the hardware. The array is
1718 * zero-terminated and sorted in decreasing order.
1721 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1723 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1724 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1725 static const int gen7_modes
[] = {8, 4, 0, -1};
1726 static const int gen6_modes
[] = {4, 0, -1};
1727 static const int gen4_modes
[] = {0, -1};
1729 if (screen
->devinfo
.gen
>= 9) {
1731 } else if (screen
->devinfo
.gen
>= 8) {
1733 } else if (screen
->devinfo
.gen
>= 7) {
1735 } else if (screen
->devinfo
.gen
== 6) {
1742 static __DRIconfig
**
1743 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1745 static const mesa_format formats
[] = {
1746 MESA_FORMAT_B5G6R5_UNORM
,
1747 MESA_FORMAT_B8G8R8A8_UNORM
,
1748 MESA_FORMAT_B8G8R8X8_UNORM
,
1750 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1751 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1752 * server may disagree on which format the GLXFBConfig represents,
1753 * resulting in swapped color channels.
1755 * The problem, as of 2017-05-30:
1756 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1757 * order and chooses the first __DRIconfig with the expected channel
1758 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1759 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1761 * EGL does not suffer from this problem. It correctly compares the
1762 * channel masks when matching EGLConfig to __DRIconfig.
1765 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
1766 MESA_FORMAT_R8G8B8A8_UNORM
,
1768 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
1769 MESA_FORMAT_R8G8B8X8_UNORM
,
1772 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1773 static const GLenum back_buffer_modes
[] = {
1774 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1777 static const uint8_t singlesample_samples
[1] = {0};
1778 static const uint8_t multisample_samples
[2] = {4, 8};
1780 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1781 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1782 uint8_t depth_bits
[4], stencil_bits
[4];
1783 __DRIconfig
**configs
= NULL
;
1785 /* Generate singlesample configs without accumulation buffer. */
1786 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1787 __DRIconfig
**new_configs
;
1788 int num_depth_stencil_bits
= 2;
1790 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1791 * buffer that has a different number of bits per pixel than the color
1792 * buffer, gen >= 6 supports this.
1795 stencil_bits
[0] = 0;
1797 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1799 stencil_bits
[1] = 0;
1800 if (devinfo
->gen
>= 6) {
1802 stencil_bits
[2] = 8;
1803 num_depth_stencil_bits
= 3;
1807 stencil_bits
[1] = 8;
1810 new_configs
= driCreateConfigs(formats
[i
],
1813 num_depth_stencil_bits
,
1814 back_buffer_modes
, 2,
1815 singlesample_samples
, 1,
1817 configs
= driConcatConfigs(configs
, new_configs
);
1820 /* Generate the minimum possible set of configs that include an
1821 * accumulation buffer.
1823 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1824 __DRIconfig
**new_configs
;
1826 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1828 stencil_bits
[0] = 0;
1831 stencil_bits
[0] = 8;
1834 new_configs
= driCreateConfigs(formats
[i
],
1835 depth_bits
, stencil_bits
, 1,
1836 back_buffer_modes
, 1,
1837 singlesample_samples
, 1,
1839 configs
= driConcatConfigs(configs
, new_configs
);
1842 /* Generate multisample configs.
1844 * This loop breaks early, and hence is a no-op, on gen < 6.
1846 * Multisample configs must follow the singlesample configs in order to
1847 * work around an X server bug present in 1.12. The X server chooses to
1848 * associate the first listed RGBA888-Z24S8 config, regardless of its
1849 * sample count, with the 32-bit depth visual used for compositing.
1851 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1852 * supported. Singlebuffer configs are not supported because no one wants
1855 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1856 if (devinfo
->gen
< 6)
1859 __DRIconfig
**new_configs
;
1860 const int num_depth_stencil_bits
= 2;
1861 int num_msaa_modes
= 0;
1864 stencil_bits
[0] = 0;
1866 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1868 stencil_bits
[1] = 0;
1871 stencil_bits
[1] = 8;
1874 if (devinfo
->gen
>= 7)
1876 else if (devinfo
->gen
== 6)
1879 new_configs
= driCreateConfigs(formats
[i
],
1882 num_depth_stencil_bits
,
1883 back_buffer_modes
, 1,
1884 multisample_samples
,
1887 configs
= driConcatConfigs(configs
, new_configs
);
1890 if (configs
== NULL
) {
1891 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1900 set_max_gl_versions(struct intel_screen
*screen
)
1902 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1903 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1905 switch (screen
->devinfo
.gen
) {
1909 dri_screen
->max_gl_core_version
= 45;
1910 dri_screen
->max_gl_compat_version
= 30;
1911 dri_screen
->max_gl_es1_version
= 11;
1912 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1915 dri_screen
->max_gl_core_version
= 33;
1916 if (can_do_pipelined_register_writes(screen
)) {
1917 dri_screen
->max_gl_core_version
= 42;
1918 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1919 dri_screen
->max_gl_core_version
= 43;
1920 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1921 dri_screen
->max_gl_core_version
= 45;
1923 dri_screen
->max_gl_compat_version
= 30;
1924 dri_screen
->max_gl_es1_version
= 11;
1925 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1928 dri_screen
->max_gl_core_version
= 33;
1929 dri_screen
->max_gl_compat_version
= 30;
1930 dri_screen
->max_gl_es1_version
= 11;
1931 dri_screen
->max_gl_es2_version
= 30;
1935 dri_screen
->max_gl_core_version
= 0;
1936 dri_screen
->max_gl_compat_version
= 21;
1937 dri_screen
->max_gl_es1_version
= 11;
1938 dri_screen
->max_gl_es2_version
= 20;
1941 unreachable("unrecognized intel_screen::gen");
1946 * Return the revision (generally the revid field of the PCI header) of the
1949 * XXX: This function is useful to keep around even if it is not currently in
1950 * use. It is necessary for new platforms and revision specific workarounds or
1951 * features. Please don't remove it so that we know it at least continues to
1954 static __attribute__((__unused__
)) int
1955 brw_get_revision(int fd
)
1957 struct drm_i915_getparam gp
;
1961 memset(&gp
, 0, sizeof(gp
));
1962 gp
.param
= I915_PARAM_REVISION
;
1963 gp
.value
= &revision
;
1965 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1973 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1975 struct brw_context
*brw
= (struct brw_context
*)data
;
1978 va_start(args
, fmt
);
1980 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1981 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1982 MESA_DEBUG_TYPE_OTHER
,
1983 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1988 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1990 struct brw_context
*brw
= (struct brw_context
*)data
;
1993 va_start(args
, fmt
);
1995 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1997 va_copy(args_copy
, args
);
1998 vfprintf(stderr
, fmt
, args_copy
);
2002 if (brw
->perf_debug
) {
2004 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2005 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2006 MESA_DEBUG_TYPE_PERFORMANCE
,
2007 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2013 parse_devid_override(const char *devid_override
)
2015 static const struct {
2032 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2033 if (!strcmp(name_map
[i
].name
, devid_override
))
2034 return name_map
[i
].pci_id
;
2037 return strtol(devid_override
, NULL
, 0);
2041 * Get the PCI ID for the device. This can be overridden by setting the
2042 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2044 * Returns -1 on ioctl failure.
2047 get_pci_device_id(struct intel_screen
*screen
)
2049 if (geteuid() == getuid()) {
2050 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2051 if (devid_override
) {
2052 screen
->no_hw
= true;
2053 return parse_devid_override(devid_override
);
2057 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2061 * This is the driver specific part of the createNewScreen entry point.
2062 * Called when using DRI2.
2064 * \return the struct gl_config supported by this driver
2067 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2069 struct intel_screen
*screen
;
2071 if (dri_screen
->image
.loader
) {
2072 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2073 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2075 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2076 "support required\n");
2080 /* Allocate the private area */
2081 screen
= rzalloc(NULL
, struct intel_screen
);
2083 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2086 /* parse information in __driConfigOptions */
2087 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2089 screen
->driScrnPriv
= dri_screen
;
2090 dri_screen
->driverPrivate
= (void *) screen
;
2092 screen
->deviceID
= get_pci_device_id(screen
);
2094 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2097 if (!intel_init_bufmgr(screen
))
2100 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2102 brw_process_intel_debug_variable();
2104 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2106 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2107 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2110 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2111 /* Theorectically unlimited! At least for individual objects...
2113 * Currently the entire (global) address space for all GTT maps is
2114 * limited to 64bits. That is all objects on the system that are
2115 * setup for GTT mmapping must fit within 64bits. An attempt to use
2116 * one that exceeds the limit with fail in brw_bo_map_gtt().
2118 * Long before we hit that limit, we will be practically limited by
2119 * that any single object must fit in physical memory (RAM). The upper
2120 * limit on the CPU's address space is currently 48bits (Skylake), of
2121 * which only 39bits can be physical memory. (The GPU itself also has
2122 * a 48bit addressable virtual space.) We can fit over 32 million
2123 * objects of the current maximum allocable size before running out
2126 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2128 /* Estimate the size of the mappable aperture into the GTT. There's an
2129 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2130 * It turns out it's basically always 256MB, though some ancient hardware
2133 uint32_t gtt_size
= 256 * 1024 * 1024;
2135 /* We don't want to map two objects such that a memcpy between them would
2136 * just fault one mapping in and then the other over and over forever. So
2137 * we would need to divide the GTT size by 2. Additionally, some GTT is
2138 * taken up by things like the framebuffer and the ringbuffer and such, so
2139 * be more conservative.
2141 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2144 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2146 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2147 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2149 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2150 screen
->hw_has_swizzling
);
2152 /* GENs prior to 8 do not support EU/Subslice info */
2153 if (devinfo
->gen
>= 8) {
2154 intel_detect_sseu(screen
);
2155 } else if (devinfo
->gen
== 7) {
2156 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2159 /* Gen7-7.5 kernel requirements / command parser saga:
2162 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2164 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2165 * all batches secure, allowing them to use any feature with no checking.
2166 * This is effectively equivalent to a command parser version of
2167 * \infinity - everything is possible.
2169 * The command parser does not exist, and querying the version will
2173 * The kernel enables the command parser by default, for systems with
2174 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2175 * hardware checker is still enabled, so Haswell and Baytrail cannot
2178 * Ivybridge goes from "everything is possible" to "only what the
2179 * command parser allows" (if the user boots with i915.cmd_parser=0,
2180 * then everything is possible again). We can only safely use features
2181 * allowed by the supported command parser version.
2183 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2184 * implemented by the kernel, even if it's turned off. So, checking
2185 * for version > 0 does not mean that you can write registers. We have
2186 * to try it and see. The version does, however, indicate the age of
2189 * Instead of matching the hardware checker's behavior of converting
2190 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2191 * -EINVAL, making it dangerous to try and use privileged features.
2193 * Effective command parser versions:
2194 * - Haswell: 0 (reporting 1, writes don't work)
2195 * - Baytrail: 0 (reporting 1, writes don't work)
2196 * - Ivybridge: 1 (enabled) or infinite (disabled)
2199 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2200 * effectively version 1 (enabled) or infinite (disabled).
2202 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2203 * Command parser v2 supports predicate writes.
2205 * - Haswell: 0 (reporting 1, writes don't work)
2206 * - Baytrail: 2 (enabled) or infinite (disabled)
2207 * - Ivybridge: 2 (enabled) or infinite (disabled)
2209 * So version >= 2 is enough to know that Ivybridge and Baytrail
2210 * will work. Haswell still can't do anything.
2212 * - v4.0: Version 3 happened. Largely not relevant.
2214 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2215 * L3 config registers are properly saved and restored as part
2216 * of the hardware context. We can approximately detect this point
2217 * in time by checking if I915_PARAM_REVISION is recognized - it
2218 * landed in a later commit, but in the same release cycle.
2220 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2221 * Command parser finally gains secure batch promotion. On Haswell,
2222 * the hardware checker gets disabled, which finally allows it to do
2223 * privileged commands.
2225 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2226 * - Haswell: 3 (enabled) or 0 (disabled)
2227 * - Baytrail: 3 (enabled) or infinite (disabled)
2228 * - Ivybridge: 3 (enabled) or infinite (disabled)
2230 * Unfortunately, detecting this point in time is tricky, because
2231 * no version bump happened when this important change occurred.
2232 * On Haswell, if we can write any register, then the kernel is at
2233 * least this new, and we can start trusting the version number.
2235 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2236 * Command parser reaches version 4, allowing access to Haswell
2237 * atomic scratch and chicken3 registers. If version >= 4, we know
2238 * the kernel is new enough to support privileged features on all
2239 * hardware. However, the user might have disabled it...and the
2240 * kernel will still report version 4. So we still have to guess
2243 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2244 * Command parser v5 whitelists indirect compute shader dispatch
2245 * registers, needed for OpenGL 4.3 and later.
2248 * Command parser v7 lets us use MI_MATH on Haswell.
2250 * Additionally, the kernel begins reporting version 0 when
2251 * the command parser is disabled, allowing us to skip the
2252 * guess-and-check step on Haswell. Unfortunately, this also
2253 * means that we can no longer use it as an indicator of the
2254 * age of the kernel.
2256 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2257 &screen
->cmd_parser_version
) < 0) {
2258 /* Command parser does not exist - getparam is unrecognized */
2259 screen
->cmd_parser_version
= 0;
2262 /* Kernel 4.13 retuired for exec object capture */
2263 #ifndef I915_PARAM_HAS_EXEC_CAPTURE
2264 #define I915_PARAM_HAS_EXEC_CAPTURE 45
2266 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2267 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2270 if (!intel_detect_pipelined_so(screen
)) {
2271 /* We can't do anything, so the effective version is 0. */
2272 screen
->cmd_parser_version
= 0;
2274 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2277 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2278 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2280 /* Haswell requires command parser version 4 in order to have L3
2281 * atomic scratch1 and chicken3 bits
2283 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2284 screen
->kernel_features
|=
2285 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2288 /* Haswell requires command parser version 6 in order to write to the
2289 * MI_MATH GPR registers, and version 7 in order to use
2290 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2292 if (devinfo
->gen
>= 8 ||
2293 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2294 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2297 /* Gen7 needs at least command parser version 5 to support compute */
2298 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2299 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2301 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2303 screen
->winsys_msaa_samples_override
=
2304 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2305 printf("Forcing winsys sample count to %d\n",
2306 screen
->winsys_msaa_samples_override
);
2308 screen
->winsys_msaa_samples_override
= -1;
2311 set_max_gl_versions(screen
);
2313 /* Notification of GPU resets requires hardware contexts and a kernel new
2314 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2315 * supported, calling it with a context of 0 will either generate EPERM or
2316 * no error. If the ioctl is not supported, it always generate EINVAL.
2317 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2318 * extension to the loader.
2320 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2322 if (devinfo
->gen
>= 6) {
2323 struct drm_i915_reset_stats stats
;
2324 memset(&stats
, 0, sizeof(stats
));
2326 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2328 screen
->has_context_reset_notification
=
2329 (ret
!= -1 || errno
!= EINVAL
);
2332 dri_screen
->extensions
= !screen
->has_context_reset_notification
2333 ? screenExtensions
: intelRobustScreenExtensions
;
2335 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2336 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2337 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2338 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8;
2339 screen
->program_id
= 1;
2341 screen
->has_exec_fence
=
2342 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2344 intel_screen_init_surface_formats(screen
);
2346 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2349 struct intel_buffer
{
2354 static __DRIbuffer
*
2355 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2356 unsigned attachment
, unsigned format
,
2357 int width
, int height
)
2359 struct intel_buffer
*intelBuffer
;
2360 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2362 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2363 attachment
== __DRI_BUFFER_BACK_LEFT
);
2365 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2366 if (intelBuffer
== NULL
)
2369 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2370 * supports Y tiled and compressed buffers, but there is no way to plumb that
2371 * through to here. */
2373 int cpp
= format
/ 8;
2374 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2375 "intelAllocateBuffer",
2379 I915_TILING_X
, &pitch
,
2380 BO_ALLOC_FOR_RENDER
);
2382 if (intelBuffer
->bo
== NULL
) {
2387 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2389 intelBuffer
->base
.attachment
= attachment
;
2390 intelBuffer
->base
.cpp
= cpp
;
2391 intelBuffer
->base
.pitch
= pitch
;
2393 return &intelBuffer
->base
;
2397 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2399 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2401 brw_bo_unreference(intelBuffer
->bo
);
2405 static const struct __DriverAPIRec brw_driver_api
= {
2406 .InitScreen
= intelInitScreen2
,
2407 .DestroyScreen
= intelDestroyScreen
,
2408 .CreateContext
= brwCreateContext
,
2409 .DestroyContext
= intelDestroyContext
,
2410 .CreateBuffer
= intelCreateBuffer
,
2411 .DestroyBuffer
= intelDestroyBuffer
,
2412 .MakeCurrent
= intelMakeCurrent
,
2413 .UnbindContext
= intelUnbindContext
,
2414 .AllocateBuffer
= intelAllocateBuffer
,
2415 .ReleaseBuffer
= intelReleaseBuffer
2418 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2419 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2420 .vtable
= &brw_driver_api
,
2423 static const __DRIextension
*brw_driver_extensions
[] = {
2424 &driCoreExtension
.base
,
2425 &driImageDriverExtension
.base
,
2426 &driDRI2Extension
.base
,
2428 &brw_config_options
.base
,
2432 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2434 globalDriverAPI
= &brw_driver_api
;
2436 return brw_driver_extensions
;