src/mesa/drivers/dri/nouveau/nv20_context.c

   1 /*
   2  * Copyright (C) 2009-2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nouveau_driver.h"
  28 #include "nouveau_context.h"
  29 #include "nouveau_class.h"
  30 #include "nv04_driver.h"
  31 #include "nv10_driver.h"
  32 #include "nv20_driver.h"
  33
  34 static void
  35 nv20_hwctx_init(GLcontext *ctx)
  36 {
  37         struct nouveau_channel *chan = context_chan(ctx);
  38         struct nouveau_grobj *kelvin = context_eng3d(ctx);
  39         struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw;
  40         int i;
  41
  42         BEGIN_RING(chan, kelvin, NV20TCL_DMA_NOTIFY, 1);
  43         OUT_RING  (chan, hw->ntfy->handle);
  44         BEGIN_RING(chan, kelvin, NV20TCL_DMA_TEXTURE0, 2);
  45         OUT_RING  (chan, chan->vram->handle);
  46         OUT_RING  (chan, chan->gart->handle);
  47         BEGIN_RING(chan, kelvin, NV20TCL_DMA_COLOR, 2);
  48         OUT_RING  (chan, chan->vram->handle);
  49         OUT_RING  (chan, chan->vram->handle);
  50         BEGIN_RING(chan, kelvin, NV20TCL_DMA_VTXBUF0, 2);
  51         OUT_RING(chan, chan->vram->handle);
  52         OUT_RING(chan, chan->gart->handle);
  53
  54         BEGIN_RING(chan, kelvin, NV20TCL_DMA_QUERY, 1);
  55         OUT_RING  (chan, 0);
  56
  57         BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
  58         OUT_RING  (chan, 0);
  59         OUT_RING  (chan, 0);
  60
  61         BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
  62         OUT_RING  (chan, 0xfff << 16 | 0x0);
  63         BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
  64         OUT_RING  (chan, 0xfff << 16 | 0x0);
  65
  66         for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) {
  67                 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1);
  68                 OUT_RING  (chan, 0);
  69                 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1);
  70                 OUT_RING  (chan, 0);
  71         }
  72
  73         BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1);
  74         OUT_RING  (chan, 0);
  75
  76         BEGIN_RING(chan, kelvin, 0x17e0, 3);
  77         OUT_RINGf (chan, 0.0);
  78         OUT_RINGf (chan, 0.0);
  79         OUT_RINGf (chan, 1.0);
  80
  81         if (context_chipset(ctx) >= 0x25) {
  82                 BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
  83                 OUT_RING  (chan, NV20TCL_TX_RCOMP_LEQUAL | 0xdb0);
  84         } else {
  85                 BEGIN_RING(chan, kelvin, 0x1e68, 1);
  86                 OUT_RING  (chan, 0x4b800000); /* 16777216.000000 */
  87                 BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
  88                 OUT_RING  (chan, NV20TCL_TX_RCOMP_LEQUAL);
  89         }
  90
  91         BEGIN_RING(chan, kelvin, 0x290, 1);
  92         OUT_RING  (chan, 0x10 << 16 | 1);
  93         BEGIN_RING(chan, kelvin, 0x9fc, 1);
  94         OUT_RING  (chan, 0);
  95         BEGIN_RING(chan, kelvin, 0x1d80, 1);
  96         OUT_RING  (chan, 1);
  97         BEGIN_RING(chan, kelvin, 0x9f8, 1);
  98         OUT_RING  (chan, 4);
  99         BEGIN_RING(chan, kelvin, 0x17ec, 3);
 100         OUT_RINGf (chan, 0.0);
 101         OUT_RINGf (chan, 1.0);
 102         OUT_RINGf (chan, 0.0);
 103
 104         if (context_chipset(ctx) >= 0x25) {
 105                 BEGIN_RING(chan, kelvin, 0x1d88, 1);
 106                 OUT_RING  (chan, 3);
 107
 108                 BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY9, 1);
 109                 OUT_RING  (chan, chan->vram->handle);
 110                 BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY8, 1);
 111                 OUT_RING  (chan, chan->vram->handle);
 112         }
 113
 114         BEGIN_RING(chan, kelvin, NV20TCL_DMA_FENCE, 1);
 115         OUT_RING  (chan, 0);
 116
 117         BEGIN_RING(chan, kelvin, 0x1e98, 1);
 118         OUT_RING  (chan, 0);
 119
 120         BEGIN_RING(chan, kelvin, NV20TCL_NOTIFY, 1);
 121         OUT_RING  (chan, 0);
 122
 123         BEGIN_RING(chan, kelvin, 0x120, 3);
 124         OUT_RING  (chan, 0);
 125         OUT_RING  (chan, 1);
 126         OUT_RING  (chan, 2);
 127
 128         if (context_chipset(ctx) >= 0x25) {
 129                 BEGIN_RING(chan, kelvin, 0x022c, 2);
 130                 OUT_RING  (chan, 0x280);
 131                 OUT_RING  (chan, 0x07d28000);
 132
 133                 BEGIN_RING(chan, kelvin, 0x1da4, 1);
 134                 OUT_RING  (chan, 0);
 135         }
 136
 137         BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
 138         OUT_RING  (chan, 0 << 16 | 0);
 139         OUT_RING  (chan, 0 << 16 | 0);
 140
 141         BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
 142         OUT_RING  (chan, 0);
 143         BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2);
 144         OUT_RING  (chan, NV20TCL_ALPHA_FUNC_FUNC_ALWAYS);
 145         OUT_RING  (chan, 0);
 146
 147         for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; i++) {
 148                 BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
 149                 OUT_RING  (chan, 0);
 150         }
 151
 152         BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_OP, 1);
 153         OUT_RING  (chan, 0);
 154         BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1);
 155         OUT_RING  (chan, 0);
 156
 157         BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_ALPHA(0), 4);
 158         OUT_RING  (chan, 0x30d410d0);
 159         OUT_RING  (chan, 0);
 160         OUT_RING  (chan, 0);
 161         OUT_RING  (chan, 0);
 162         BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_RGB(0), 4);
 163         OUT_RING  (chan, 0x00000c00);
 164         OUT_RING  (chan, 0);
 165         OUT_RING  (chan, 0);
 166         OUT_RING  (chan, 0);
 167         BEGIN_RING(chan, kelvin, NV20TCL_RC_ENABLE, 1);
 168         OUT_RING  (chan, 0x00011101);
 169         BEGIN_RING(chan, kelvin, NV20TCL_RC_FINAL0, 2);
 170         OUT_RING  (chan, 0x130e0300);
 171         OUT_RING  (chan, 0x0c091c80);
 172         BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_ALPHA(0), 4);
 173         OUT_RING  (chan, 0x00000c00);
 174         OUT_RING  (chan, 0);
 175         OUT_RING  (chan, 0);
 176         OUT_RING  (chan, 0);
 177         BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_RGB(0), 4);
 178         OUT_RING  (chan, 0x20c400c0);
 179         OUT_RING  (chan, 0);
 180         OUT_RING  (chan, 0);
 181         OUT_RING  (chan, 0);
 182         BEGIN_RING(chan, kelvin, NV20TCL_RC_COLOR0, 2);
 183         OUT_RING  (chan, 0);
 184         OUT_RING  (chan, 0);
 185         BEGIN_RING(chan, kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4);
 186         OUT_RING  (chan, 0x035125a0);
 187         OUT_RING  (chan, 0);
 188         OUT_RING  (chan, 0x40002000);
 189         OUT_RING  (chan, 0);
 190
 191         BEGIN_RING(chan, kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1);
 192         OUT_RING  (chan, 0xffff0000);
 193         BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
 194         OUT_RING  (chan, 0);
 195         BEGIN_RING(chan, kelvin, NV20TCL_DITHER_ENABLE, 1);
 196         OUT_RING  (chan, 0);
 197         BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_ENABLE, 1);
 198         OUT_RING  (chan, 0);
 199         BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_SRC, 4);
 200         OUT_RING  (chan, NV20TCL_BLEND_FUNC_SRC_ONE);
 201         OUT_RING  (chan, NV20TCL_BLEND_FUNC_DST_ZERO);
 202         OUT_RING  (chan, 0);
 203         OUT_RING  (chan, NV20TCL_BLEND_EQUATION_FUNC_ADD);
 204         BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_MASK, 7);
 205         OUT_RING  (chan, 0xff);
 206         OUT_RING  (chan, NV20TCL_STENCIL_FUNC_FUNC_ALWAYS);
 207         OUT_RING  (chan, 0);
 208         OUT_RING  (chan, 0xff);
 209         OUT_RING  (chan, NV20TCL_STENCIL_OP_FAIL_KEEP);
 210         OUT_RING  (chan, NV20TCL_STENCIL_OP_ZFAIL_KEEP);
 211         OUT_RING  (chan, NV20TCL_STENCIL_OP_ZPASS_KEEP);
 212
 213         BEGIN_RING(chan, kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
 214         OUT_RING  (chan, 0);
 215         OUT_RING  (chan, NV20TCL_COLOR_LOGIC_OP_OP_COPY);
 216         BEGIN_RING(chan, kelvin, 0x17cc, 1);
 217         OUT_RING  (chan, 0);
 218         if (context_chipset(ctx) >= 0x25) {
 219                 BEGIN_RING(chan, kelvin, 0x1d84, 1);
 220                 OUT_RING  (chan, 1);
 221         }
 222         BEGIN_RING(chan, kelvin, NV20TCL_LIGHTING_ENABLE, 1);
 223         OUT_RING  (chan, 0);
 224         BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL, 1);
 225         OUT_RING  (chan, NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL);
 226         BEGIN_RING(chan, kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
 227         OUT_RING  (chan, 0);
 228         BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
 229         OUT_RING  (chan, 0);
 230         BEGIN_RING(chan, kelvin, NV20TCL_ENABLED_LIGHTS, 1);
 231         OUT_RING  (chan, 0);
 232         BEGIN_RING(chan, kelvin, NV20TCL_NORMALIZE_ENABLE, 1);
 233         OUT_RING  (chan, 0);
 234         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0),
 235                    NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE);
 236         for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; i++) {
 237                 OUT_RING(chan, 0xffffffff);
 238         }
 239
 240         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
 241         OUT_RING  (chan, 0);
 242         OUT_RING  (chan, 0);
 243         OUT_RING  (chan, 0);
 244         BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_FUNC, 1);
 245         OUT_RING  (chan, NV20TCL_DEPTH_FUNC_LESS);
 246         BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
 247         OUT_RING  (chan, 0);
 248         BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
 249         OUT_RING  (chan, 0);
 250         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2);
 251         OUT_RINGf (chan, 0.0);
 252         OUT_RINGf (chan, 0.0);
 253         BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_UNK17D8, 1);
 254         OUT_RING  (chan, 1);
 255         if (context_chipset(ctx) < 0x25) {
 256                 BEGIN_RING(chan, kelvin, 0x1d84, 1);
 257                 OUT_RING  (chan, 3);
 258         }
 259         BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
 260         if (context_chipset(ctx) >= 0x25)
 261                 OUT_RINGf (chan, 1.0);
 262         else
 263                 OUT_RING  (chan, 8);
 264
 265         if (context_chipset(ctx) >= 0x25) {
 266                 BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1);
 267                 OUT_RING  (chan, 0);
 268                 BEGIN_RING(chan, kelvin, 0x0a1c, 1);
 269                 OUT_RING  (chan, 0x800);
 270         } else {
 271                 BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2);
 272                 OUT_RING  (chan, 0);
 273                 OUT_RING  (chan, 0);
 274         }
 275
 276         BEGIN_RING(chan, kelvin, NV20TCL_LINE_WIDTH, 1);
 277         OUT_RING  (chan, 8);
 278         BEGIN_RING(chan, kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1);
 279         OUT_RING  (chan, 0);
 280         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
 281         OUT_RING  (chan, NV20TCL_POLYGON_MODE_FRONT_FILL);
 282         OUT_RING  (chan, NV20TCL_POLYGON_MODE_BACK_FILL);
 283         BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE, 2);
 284         OUT_RING  (chan, NV20TCL_CULL_FACE_BACK);
 285         OUT_RING  (chan, NV20TCL_FRONT_FACE_CCW);
 286         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1);
 287         OUT_RING  (chan, 0);
 288         BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
 289         OUT_RING  (chan, 0);
 290         BEGIN_RING(chan, kelvin, NV20TCL_SHADE_MODEL, 1);
 291         OUT_RING  (chan, NV20TCL_SHADE_MODEL_SMOOTH);
 292         BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1);
 293         OUT_RING  (chan, 0);
 294
 295         BEGIN_RING(chan, kelvin, NV20TCL_TX_GEN_S(0),
 296                    4 * NV20TCL_TX_GEN_S__SIZE);
 297         for (i=0; i < 4 * NV20TCL_TX_GEN_S__SIZE; i++)
 298                 OUT_RING(chan, 0);
 299
 300         BEGIN_RING(chan, kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
 301         OUT_RINGf (chan, 1.5);
 302         OUT_RINGf (chan, -0.090168);
 303         OUT_RINGf (chan, 0.0);
 304         BEGIN_RING(chan, kelvin, NV20TCL_FOG_MODE, 2);
 305         OUT_RING  (chan, NV20TCL_FOG_MODE_EXP_SIGNED);
 306         OUT_RING  (chan, NV20TCL_FOG_COORD_FOG);
 307         BEGIN_RING(chan, kelvin, NV20TCL_FOG_ENABLE, 2);
 308         OUT_RING  (chan, 0);
 309         OUT_RING  (chan, 0);
 310
 311         BEGIN_RING(chan, kelvin, NV20TCL_ENGINE, 1);
 312         OUT_RING  (chan, NV20TCL_ENGINE_FIXED);
 313
 314         for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; i++) {
 315                 BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
 316                 OUT_RING  (chan, 0);
 317         }
 318
 319         BEGIN_RING(chan, kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15);
 320         OUT_RINGf(chan, 1.0);
 321         OUT_RINGf(chan, 0.0);
 322         OUT_RINGf(chan, 0.0);
 323         OUT_RINGf(chan, 1.0);
 324         OUT_RINGf(chan, 0.0);
 325         OUT_RINGf(chan, 0.0);
 326         OUT_RINGf(chan, 1.0);
 327         OUT_RINGf(chan, 1.0);
 328         OUT_RINGf(chan, 1.0);
 329         OUT_RINGf(chan, 1.0);
 330         OUT_RINGf(chan, 1.0);
 331         OUT_RINGf(chan, 1.0);
 332         for (i = 0; i < 12; i++) {
 333                 OUT_RINGf(chan, 0.0);
 334                 OUT_RINGf(chan, 0.0);
 335                 OUT_RINGf(chan, 0.0);
 336                 OUT_RINGf(chan, 1.0);
 337         }
 338
 339         BEGIN_RING(chan, kelvin, NV20TCL_EDGEFLAG_ENABLE, 1);
 340         OUT_RING  (chan, 1);
 341         BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MASK, 1);
 342         OUT_RING (chan, 0x00010101);
 343         BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_VALUE, 1);
 344         OUT_RING (chan, 0);
 345
 346         BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2);
 347         OUT_RINGf (chan, 0.0);
 348         OUT_RINGf (chan, 16777216.0);
 349
 350         BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
 351         OUT_RINGf (chan, 0.0);
 352         OUT_RINGf (chan, 0.0);
 353         OUT_RINGf (chan, 0.0);
 354         OUT_RINGf (chan, 16777215.0);
 355
 356         BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_SCALE_X, 4);
 357         OUT_RINGf (chan, 0.0);
 358         OUT_RINGf (chan, 0.0);
 359         OUT_RINGf (chan, 16777215.0 * 0.5);
 360         OUT_RINGf (chan, 65535.0);
 361
 362         FIRE_RING(chan);
 363 }
 364
 365 static void
 366 nv20_context_destroy(GLcontext *ctx)
 367 {
 368         struct nouveau_context *nctx = to_nouveau_context(ctx);
 369
 370         nv04_surface_takedown(ctx);
 371         nv20_render_destroy(ctx);
 372
 373         nouveau_grobj_free(&nctx->hw.eng3d);
 374
 375         nouveau_context_deinit(ctx);
 376         FREE(ctx);
 377 }
 378
 379 static GLcontext *
 380 nv20_context_create(struct nouveau_screen *screen, const GLvisual *visual,
 381                     GLcontext *share_ctx)
 382 {
 383         struct nouveau_context *nctx;
 384         GLcontext *ctx;
 385         unsigned kelvin_class;
 386         int ret;
 387
 388         nctx = CALLOC_STRUCT(nouveau_context);
 389         if (!nctx)
 390                 return NULL;
 391
 392         ctx = &nctx->base;
 393
 394         if (!nouveau_context_init(ctx, screen, visual, share_ctx))
 395                 goto fail;
 396
 397         /* GL constants. */
 398         ctx->Const.MaxTextureCoordUnits = NV20_TEXTURE_UNITS;
 399         ctx->Const.MaxTextureImageUnits = NV20_TEXTURE_UNITS;
 400         ctx->Const.MaxTextureUnits = NV20_TEXTURE_UNITS;
 401         ctx->Const.MaxTextureMaxAnisotropy = 8;
 402         ctx->Const.MaxTextureLodBias = 15;
 403
 404         /* 2D engine. */
 405         ret = nv04_surface_init(ctx);
 406         if (!ret)
 407                 goto fail;
 408
 409         /* 3D engine. */
 410         if (context_chipset(ctx) >= 0x25)
 411                 kelvin_class = NV25TCL;
 412         else
 413                 kelvin_class = NV20TCL;
 414
 415         ret = nouveau_grobj_alloc(context_chan(ctx), 0xbeef0001, kelvin_class,
 416                                   &nctx->hw.eng3d);
 417         if (ret)
 418                 goto fail;
 419
 420         nv20_hwctx_init(ctx);
 421         nv20_render_init(ctx);
 422
 423         return ctx;
 424
 425 fail:
 426         nv20_context_destroy(ctx);
 427         return NULL;
 428 }
 429
 430 const struct nouveau_driver nv20_driver = {
 431         .context_create = nv20_context_create,
 432         .context_destroy = nv20_context_destroy,
 433         .surface_copy = nv04_surface_copy,
 434         .surface_fill = nv04_surface_fill,
 435         .emit = (nouveau_state_func[]) {
 436                 nv10_emit_alpha_func,
 437                 nv10_emit_blend_color,
 438                 nv10_emit_blend_equation,
 439                 nv10_emit_blend_func,
 440                 nv20_emit_clip_plane,
 441                 nv20_emit_clip_plane,
 442                 nv20_emit_clip_plane,
 443                 nv20_emit_clip_plane,
 444                 nv20_emit_clip_plane,
 445                 nv20_emit_clip_plane,
 446                 nv10_emit_color_mask,
 447                 nv20_emit_color_material,
 448                 nv10_emit_cull_face,
 449                 nv10_emit_front_face,
 450                 nv10_emit_depth,
 451                 nv10_emit_dither,
 452                 nv20_emit_frag,
 453                 nv20_emit_framebuffer,
 454                 nv20_emit_fog,
 455                 nv10_emit_index_mask,
 456                 nv10_emit_light_enable,
 457                 nv20_emit_light_model,
 458                 nv20_emit_light_source,
 459                 nv20_emit_light_source,
 460                 nv20_emit_light_source,
 461                 nv20_emit_light_source,
 462                 nv20_emit_light_source,
 463                 nv20_emit_light_source,
 464                 nv20_emit_light_source,
 465                 nv20_emit_light_source,
 466                 nv10_emit_line_stipple,
 467                 nv10_emit_line_mode,
 468                 nv20_emit_logic_opcode,
 469                 nv20_emit_material_ambient,
 470                 nv20_emit_material_ambient,
 471                 nv20_emit_material_diffuse,
 472                 nv20_emit_material_diffuse,
 473                 nv20_emit_material_specular,
 474                 nv20_emit_material_specular,
 475                 nv20_emit_material_shininess,
 476                 nv20_emit_material_shininess,
 477                 nv20_emit_modelview,
 478                 nv20_emit_point_mode,
 479                 nv10_emit_point_parameter,
 480                 nv10_emit_polygon_mode,
 481                 nv10_emit_polygon_offset,
 482                 nv10_emit_polygon_stipple,
 483                 nv20_emit_projection,
 484                 nv10_emit_render_mode,
 485                 nv10_emit_scissor,
 486                 nv10_emit_shade_model,
 487                 nv10_emit_stencil_func,
 488                 nv10_emit_stencil_mask,
 489                 nv10_emit_stencil_op,
 490                 nv20_emit_tex_env,
 491                 nv20_emit_tex_env,
 492                 nv20_emit_tex_env,
 493                 nv20_emit_tex_env,
 494                 nv10_emit_tex_gen,
 495                 nv10_emit_tex_gen,
 496                 nv10_emit_tex_gen,
 497                 nv10_emit_tex_gen,
 498                 nv20_emit_tex_obj,
 499                 nv20_emit_tex_obj,
 500                 nv20_emit_tex_obj,
 501                 nv20_emit_tex_obj,
 502                 nv20_emit_viewport,
 503                 nv20_emit_tex_shader
 504         },
 505         .num_emit = NUM_NV20_STATE,
 506 };