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radeon/r600: Fix remaining warnings when building 64 bit binary.
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 /**
230 * Check functions are used to check if state is active.
231 * If it is active check function returns maximum emit size.
232 */
233 #define CHECK( NM, FLAG, ADD ) \
234 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
235 { \
236 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
237 (void) rmesa; \
238 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
239 }
240
241 #define TCL_CHECK( NM, FLAG, ADD ) \
242 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
243 { \
244 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
245 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
246 }
247
248 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
249 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
250 { \
251 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
252 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
253 }
254
255 #define VP_CHECK( NM, FLAG, ADD ) \
256 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
257 { \
258 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
259 (void) atom; \
260 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
261 }
262
263 CHECK( always, GL_TRUE, 0 )
264 CHECK( always_add4, GL_TRUE, 4 )
265 CHECK( never, GL_FALSE, 0 )
266 CHECK( tex_any, ctx->Texture._EnabledUnits, 0 )
267 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 );
268 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
269 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
270 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
271 CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
272 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
273 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 2*5 - CUBE_STATE_SIZE )
274 TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
275 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
276 TCL_CHECK( tcl, GL_TRUE, 0 )
277 TCL_CHECK( tcl_add8, GL_TRUE, 8 )
278 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
279 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 )
280 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
281 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 )
282 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 )
283 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
284 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 )
285 TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 )
286 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 )
287 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 )
288 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
289 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
290 VP_CHECK( tcl_vp, GL_TRUE, 0 )
291 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
292 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 )
293 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 )
294 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 )
295 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start, _sz; \
311 h.i = hdr; \
312 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
313 _sz = h.veclinear.count * 4; \
314 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
315 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
316 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
317 OUT_BATCH(0); \
318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
319 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
320 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
321 OUT_BATCH_TABLE((data), _sz); \
322 END_BATCH(); \
323 } \
324 } while(0)
325
326 #define OUT_SCL(hdr, data) do { \
327 drm_radeon_cmd_header_t h; \
328 h.i = hdr; \
329 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
330 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
331 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
332 OUT_BATCH_TABLE((data), h.scalars.count); \
333 } while(0)
334
335 #define OUT_SCL2(hdr, data) do { \
336 drm_radeon_cmd_header_t h; \
337 h.i = hdr; \
338 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
339 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
340 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
341 OUT_BATCH_TABLE((data), h.scalars.count); \
342 } while(0)
343
344 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
345 {
346 r200ContextPtr r200 = R200_CONTEXT(ctx);
347 BATCH_LOCALS(&r200->radeon);
348 uint32_t dwords = atom->check(ctx, atom);
349
350 BEGIN_BATCH_NO_AUTOSTATE(dwords);
351 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
352 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
353 END_BATCH();
354 }
355
356 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
357 {
358 r200ContextPtr r200 = R200_CONTEXT(ctx);
359 BATCH_LOCALS(&r200->radeon);
360 uint32_t dwords = atom->check(ctx, atom);
361
362 BEGIN_BATCH_NO_AUTOSTATE(dwords);
363 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
364 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
365 END_BATCH();
366 }
367
368 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
369 {
370 r200ContextPtr r200 = R200_CONTEXT(ctx);
371 BATCH_LOCALS(&r200->radeon);
372 uint32_t dwords = atom->check(ctx, atom);
373
374 BEGIN_BATCH_NO_AUTOSTATE(dwords);
375 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
376 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
377 END_BATCH();
378 }
379
380 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
381 {
382 r200ContextPtr r200 = R200_CONTEXT(ctx);
383 BATCH_LOCALS(&r200->radeon);
384 uint32_t dwords = atom->check(ctx, atom);
385
386 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
387 }
388
389 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
390 {
391 r200ContextPtr r200 = R200_CONTEXT(ctx);
392 BATCH_LOCALS(&r200->radeon);
393 uint32_t dwords = atom->check(ctx, atom);
394
395 BEGIN_BATCH_NO_AUTOSTATE(dwords);
396 OUT_SCL(atom->cmd[0], atom->cmd+1);
397 END_BATCH();
398 }
399
400
401 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
402 {
403 r200ContextPtr r200 = R200_CONTEXT(ctx);
404 BATCH_LOCALS(&r200->radeon);
405 uint32_t dwords = atom->check(ctx, atom);
406
407 BEGIN_BATCH_NO_AUTOSTATE(dwords);
408 OUT_VEC(atom->cmd[0], atom->cmd+1);
409 END_BATCH();
410 }
411
412 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
413 {
414 r200ContextPtr r200 = R200_CONTEXT(ctx);
415 BATCH_LOCALS(&r200->radeon);
416 struct radeon_renderbuffer *rrb;
417 uint32_t cbpitch;
418 uint32_t zbpitch, depth_fmt;
419 uint32_t dwords = atom->check(ctx, atom);
420
421 /* output the first 7 bytes of context */
422 BEGIN_BATCH_NO_AUTOSTATE(dwords);
423 OUT_BATCH_TABLE(atom->cmd, 5);
424
425 rrb = radeon_get_depthbuffer(&r200->radeon);
426 if (!rrb) {
427 OUT_BATCH(0);
428 OUT_BATCH(0);
429 } else {
430 zbpitch = (rrb->pitch / rrb->cpp);
431 if (r200->using_hyperz)
432 zbpitch |= RADEON_DEPTH_HYPERZ;
433 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
434 OUT_BATCH(zbpitch);
435 if (rrb->cpp == 4)
436 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
437 else
438 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
439 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
440 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
441 }
442
443 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
444 OUT_BATCH(atom->cmd[CTX_CMD_1]);
445 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
446
447 rrb = radeon_get_colorbuffer(&r200->radeon);
448 if (!rrb || !rrb->bo) {
449 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
450 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
451 } else {
452 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
453 if (rrb->cpp == 4)
454 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
455 else
456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
457
458 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
459 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
460 }
461
462 OUT_BATCH(atom->cmd[CTX_CMD_2]);
463
464 if (!rrb || !rrb->bo) {
465 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
466 } else {
467 cbpitch = (rrb->pitch / rrb->cpp);
468 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
469 cbpitch |= R200_COLOR_TILE_ENABLE;
470 OUT_BATCH(cbpitch);
471 }
472
473 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
474 OUT_BATCH_TABLE((atom->cmd + 14), 4);
475
476 END_BATCH();
477 }
478
479 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
480 {
481 r200ContextPtr r200 = R200_CONTEXT(ctx);
482 struct radeon_renderbuffer *rrb, *drb;
483 uint32_t dwords;
484
485 rrb = radeon_get_colorbuffer(&r200->radeon);
486 if (!rrb || !rrb->bo) {
487 return 0;
488 }
489
490 drb = radeon_get_depthbuffer(&r200->radeon);
491
492 dwords = 10;
493 if (drb)
494 dwords += 6;
495 if (rrb)
496 dwords += 8;
497 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
498 dwords += 4;
499
500
501 return dwords;
502 }
503
504 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
505 {
506 r200ContextPtr r200 = R200_CONTEXT(ctx);
507 BATCH_LOCALS(&r200->radeon);
508 struct radeon_renderbuffer *rrb, *drb;
509 uint32_t cbpitch = 0;
510 uint32_t zbpitch = 0;
511 uint32_t dwords = atom->check(ctx, atom);
512 uint32_t depth_fmt;
513
514 rrb = radeon_get_colorbuffer(&r200->radeon);
515 if (!rrb || !rrb->bo) {
516 return;
517 }
518
519 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
520 if (rrb->cpp == 4)
521 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
522 else switch (rrb->base._ActualFormat) {
523 case GL_RGB5:
524 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
525 break;
526 case GL_RGBA4:
527 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
528 break;
529 case GL_RGB5_A1:
530 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
531 break;
532 }
533
534 cbpitch = (rrb->pitch / rrb->cpp);
535 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
536 cbpitch |= R200_COLOR_TILE_ENABLE;
537
538 drb = radeon_get_depthbuffer(&r200->radeon);
539 if (drb) {
540 zbpitch = (drb->pitch / drb->cpp);
541 if (drb->cpp == 4)
542 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
543 else
544 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
545 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
546 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
547 }
548
549 /* output the first 7 bytes of context */
550 BEGIN_BATCH_NO_AUTOSTATE(dwords);
551
552 /* In the CS case we need to split this up */
553 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
554 OUT_BATCH_TABLE((atom->cmd + 1), 4);
555
556 if (drb) {
557 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
558 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
559
560 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
561 OUT_BATCH(zbpitch);
562 }
563
564 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
565 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
566 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
567 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
568 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
569
570
571 if (rrb) {
572 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
573 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
574
575 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
576 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
577 }
578
579 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
580 OUT_BATCH_TABLE((atom->cmd + 14), 4);
581 }
582
583 END_BATCH();
584 }
585
586 static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
587 {
588 r200ContextPtr r200 = R200_CONTEXT(ctx);
589 uint32_t dwords = atom->cmd_size + 2;
590 int i = atom->idx;
591 radeonTexObj *t = r200->state.texture.unit[i].texobj;
592 if (!(t && t->mt && !t->image_override))
593 dwords -= 2;
594
595 return dwords;
596 }
597
598 static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
599 {
600 r200ContextPtr r200 = R200_CONTEXT(ctx);
601 /** XOR is bit flip operation so use it for finding pair */
602 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
603 return 0;
604
605 return get_tex_size(ctx, atom);
606 }
607
608 static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
609 {
610 r200ContextPtr r200 = R200_CONTEXT(ctx);
611 if (!(r200->state.texture.unit[atom->idx].unitneeded))
612 return 0;
613
614 return get_tex_size(ctx, atom);
615 }
616
617
618 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
619 {
620 r200ContextPtr r200 = R200_CONTEXT(ctx);
621 BATCH_LOCALS(&r200->radeon);
622 uint32_t dwords = atom->check(ctx, atom);
623 int i = atom->idx;
624 radeonTexObj *t = r200->state.texture.unit[i].texobj;
625
626 BEGIN_BATCH_NO_AUTOSTATE(dwords);
627 /* is this ok even with drm older than 1.18? */
628 OUT_BATCH_TABLE(atom->cmd, 10);
629
630 if (t && t->mt && !t->image_override) {
631 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
632 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
633 } else if (!t) {
634 /* workaround for old CS mechanism */
635 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
636 } else {
637 OUT_BATCH(t->override_offset);
638 }
639
640 END_BATCH();
641 }
642
643 static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
644 {
645 r200ContextPtr r200 = R200_CONTEXT(ctx);
646 uint32_t dwords = atom->cmd_size + 2;
647 int hastexture = 1;
648 int i = atom->idx;
649 radeonTexObj *t = r200->state.texture.unit[i].texobj;
650 if (!t)
651 hastexture = 0;
652 else {
653 if (!t->mt && !t->bo)
654 hastexture = 0;
655 }
656
657 if (!hastexture)
658 dwords -= 4;
659 return dwords;
660 }
661
662 static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
663 {
664 r200ContextPtr r200 = R200_CONTEXT(ctx);
665 /** XOR is bit flip operation so use it for finding pair */
666 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
667 return 0;
668
669 return get_tex_mm_size(ctx, atom);
670 }
671
672 static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
673 {
674 r200ContextPtr r200 = R200_CONTEXT(ctx);
675 if (!(r200->state.texture.unit[atom->idx].unitneeded))
676 return 0;
677
678 return get_tex_mm_size(ctx, atom);
679 }
680
681
682 static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
683 {
684 r200ContextPtr r200 = R200_CONTEXT(ctx);
685 BATCH_LOCALS(&r200->radeon);
686 uint32_t dwords = atom->check(ctx, atom);
687 int i = atom->idx;
688 radeonTexObj *t = r200->state.texture.unit[i].texobj;
689 if (!r200->state.texture.unit[i].unitneeded)
690 dwords -= 4;
691 BEGIN_BATCH_NO_AUTOSTATE(dwords);
692
693 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
694 OUT_BATCH_TABLE((atom->cmd + 1), 8);
695
696 if (dwords > atom->cmd_size) {
697 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
698 if (t->mt && !t->image_override) {
699 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
700 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
701 } else {
702 if (t->bo)
703 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
704 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
705 }
706 }
707 END_BATCH();
708 }
709
710
711 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
712 {
713 r200ContextPtr r200 = R200_CONTEXT(ctx);
714 BATCH_LOCALS(&r200->radeon);
715 uint32_t dwords = atom->check(ctx, atom);
716 int i = atom->idx, j;
717 radeonTexObj *t = r200->state.texture.unit[i].texobj;
718 radeon_mipmap_level *lvl;
719
720 if (!(t && !t->image_override))
721 dwords = 2;
722
723 BEGIN_BATCH_NO_AUTOSTATE(dwords);
724 /* XXX that size won't really match with image_override... */
725 OUT_BATCH_TABLE(atom->cmd, 2);
726
727 if (t && !t->image_override) {
728 lvl = &t->mt->levels[0];
729 OUT_BATCH_TABLE((atom->cmd + 2), 1);
730 for (j = 1; j <= 5; j++) {
731 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
732 RADEON_GEM_DOMAIN_VRAM, 0, 0);
733 }
734 }
735 END_BATCH();
736 }
737
738 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
739 {
740 r200ContextPtr r200 = R200_CONTEXT(ctx);
741 BATCH_LOCALS(&r200->radeon);
742 uint32_t dwords = atom->check(ctx, atom);
743 int i = atom->idx, j;
744 radeonTexObj *t = r200->state.texture.unit[i].texobj;
745 radeon_mipmap_level *lvl;
746 if (!(t && !t->image_override))
747 dwords = 2;
748
749 BEGIN_BATCH_NO_AUTOSTATE(dwords);
750 OUT_BATCH_TABLE(atom->cmd, 2);
751
752 if (t && !t->image_override) {
753 lvl = &t->mt->levels[0];
754 for (j = 1; j <= 5; j++) {
755 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
756 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
757 RADEON_GEM_DOMAIN_VRAM, 0, 0);
758 }
759 }
760 END_BATCH();
761 }
762
763 /* Initialize the context's hardware state.
764 */
765 void r200InitState( r200ContextPtr rmesa )
766 {
767 GLcontext *ctx = rmesa->radeon.glCtx;
768 GLuint i;
769
770 rmesa->radeon.state.color.clear = 0x00000000;
771
772 switch ( ctx->Visual.depthBits ) {
773 case 16:
774 rmesa->radeon.state.depth.clear = 0x0000ffff;
775 rmesa->radeon.state.stencil.clear = 0x00000000;
776 break;
777 case 24:
778 default:
779 rmesa->radeon.state.depth.clear = 0x00ffffff;
780 rmesa->radeon.state.stencil.clear = 0xffff0000;
781 break;
782 }
783
784 rmesa->radeon.Fallback = 0;
785
786 rmesa->radeon.hw.max_state_size = 0;
787
788 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
789 do { \
790 rmesa->hw.ATOM.cmd_size = SZ; \
791 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
792 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
793 rmesa->hw.ATOM.name = NM; \
794 rmesa->hw.ATOM.idx = IDX; \
795 rmesa->hw.ATOM.check = check_##CHK; \
796 rmesa->hw.ATOM.dirty = GL_FALSE; \
797 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
798 } while (0)
799
800
801 /* Allocate state buffers:
802 */
803 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
804 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
805 else
806 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
807
808 if (rmesa->radeon.radeonScreen->kernel_mm)
809 {
810 rmesa->hw.ctx.emit = ctx_emit_cs;
811 rmesa->hw.ctx.check = check_always_ctx;
812 }
813 else
814 {
815 rmesa->hw.ctx.emit = ctx_emit;
816 }
817 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
818 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
819 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
820 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
821 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
822 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
823 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
824 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
825 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
826 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
827 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
828 {
829 int state_size = TEX_STATE_SIZE_NEWDRM;
830 if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) {
831 state_size = TEX_STATE_SIZE_OLDDRM;
832 }
833 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
834 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
835 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
836 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
837 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
838 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
839 }
840 else {
841 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
842 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
843 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
844 }
845 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
846 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
847 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
848 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
849 if (!rmesa->radeon.radeonScreen->kernel_mm)
850 {
851 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
852 rmesa->hw.tex[0].check = check_tex_pair;
853 rmesa->hw.tex[1].check = check_tex_pair;
854 } else {
855 rmesa->hw.tex[0].check = check_tex;
856 rmesa->hw.tex[1].check = check_tex;
857 }
858 rmesa->hw.tex[2].check = check_tex;
859 rmesa->hw.tex[3].check = check_tex;
860 rmesa->hw.tex[4].check = check_tex;
861 rmesa->hw.tex[5].check = check_tex;
862 }
863 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
864 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
865 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
866 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
867 } else {
868 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 );
869 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
870 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
871 }
872 }
873 }
874
875 for (i = 0; i < 6; i++)
876 if (rmesa->radeon.radeonScreen->kernel_mm)
877 rmesa->hw.tex[i].emit = tex_emit_mm;
878 else
879 rmesa->hw.tex[i].emit = tex_emit;
880 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
881 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
882 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
883 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
884 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
885 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
886 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
887 for (i = 0; i < 6; i++)
888 if (rmesa->radeon.radeonScreen->kernel_mm) {
889 rmesa->hw.cube[i].emit = cube_emit_cs;
890 rmesa->hw.cube[i].check = check_tex_cube_cs;
891 } else
892 rmesa->hw.cube[i].emit = cube_emit;
893 }
894 else {
895 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
896 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
897 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
898 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
899 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
900 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
901 }
902
903 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
904 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
905 if (rmesa->radeon.radeonScreen->kernel_mm) {
906 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
907 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
908 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
909 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
910 } else {
911 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
912 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
913 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
914 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
915 }
916 }
917 else {
918 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
919 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
920 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
921 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
922 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
923 }
924 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
925 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
926 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
927 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
928 if (rmesa->radeon.radeonScreen->kernel_mm) {
929 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 );
930 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 );
931 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 );
932 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 );
933 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 );
934 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
935 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 );
936 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
937 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 );
938 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 );
939 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
940 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 );
941 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 );
942 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 );
943 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 );
944 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
945 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
946 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
947 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
948 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
949 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
950 ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 );
951 ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 );
952 ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 );
953 ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 );
954 ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 );
955 ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 );
956 ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 );
957 ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 );
958 } else {
959 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
960 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
961 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
962 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
963 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
964 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
965 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
966 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
967 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
968 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
969 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
970 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
971 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
972 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
973 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
974 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
975 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
976 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
977 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
978 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
979 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
980 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
981 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
982 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
983 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
984 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
985 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
986 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
987 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
988 }
989 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
990 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
991 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
992 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
993 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
994 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
995 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
996 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
997 }
998 else {
999 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1000 }
1001 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
1002 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1003 if (rmesa->radeon.radeonScreen->kernel_mm)
1004 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1005 else
1006 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1007 }
1008 else {
1009 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1010 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1011 }
1012
1013 r200SetUpAtomList( rmesa );
1014
1015 /* Fill in the packet headers:
1016 */
1017 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
1018 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
1019 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
1020 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
1021 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
1022 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
1023 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
1024 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
1025 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1026 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
1027 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
1028 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
1029 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
1030 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
1031 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
1032 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
1033 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
1034 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
1035 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
1036 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
1037 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1038 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
1039 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
1040 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1041 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
1042 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1043 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
1044 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1045 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
1046 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1047 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
1048 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1049 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
1050 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1051 } else {
1052 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
1053 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1054 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
1055 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1056 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
1057 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1058 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
1059 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1060 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
1061 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1062 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
1063 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1064 }
1065 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
1066 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
1067 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
1068 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
1069 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
1070 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
1071 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
1072 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
1073 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
1074 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
1075 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
1076 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
1077 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
1078 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
1079 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
1080 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
1081 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
1082 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
1083 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
1084 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
1085 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
1086 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
1087 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
1088 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1089 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
1090 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
1091 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
1092 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
1093 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
1094 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
1095 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
1096 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
1097 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
1098 if (rmesa->radeon.radeonScreen->kernel_mm) {
1099 rmesa->hw.mtl[0].emit = mtl_emit;
1100 rmesa->hw.mtl[1].emit = mtl_emit;
1101
1102 rmesa->hw.vpi[0].emit = veclinear_emit;
1103 rmesa->hw.vpi[1].emit = veclinear_emit;
1104 rmesa->hw.vpp[0].emit = veclinear_emit;
1105 rmesa->hw.vpp[1].emit = veclinear_emit;
1106
1107 rmesa->hw.grd.emit = scl_emit;
1108 rmesa->hw.fog.emit = vec_emit;
1109 rmesa->hw.glt.emit = vec_emit;
1110 rmesa->hw.eye.emit = vec_emit;
1111
1112 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
1113 rmesa->hw.mat[i].emit = vec_emit;
1114
1115 for (i = 0; i < 8; i++)
1116 rmesa->hw.lit[i].emit = lit_emit;
1117
1118 for (i = 0; i < 6; i++)
1119 rmesa->hw.ucp[i].emit = vec_emit;
1120
1121 rmesa->hw.ptp.emit = ptp_emit;
1122 }
1123
1124
1125
1126 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
1127 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
1128 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
1129 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
1130 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
1131 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
1132 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
1133 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
1134
1135 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
1136 cmdveclinear( R200_PVS_PROG0, 64 );
1137 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
1138 cmdveclinear( R200_PVS_PROG1, 64 );
1139 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
1140 cmdveclinear( R200_PVS_PARAM0, 96 );
1141 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
1142 cmdveclinear( R200_PVS_PARAM1, 96 );
1143
1144 rmesa->hw.grd.cmd[GRD_CMD_0] =
1145 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
1146 rmesa->hw.fog.cmd[FOG_CMD_0] =
1147 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
1148 rmesa->hw.glt.cmd[GLT_CMD_0] =
1149 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
1150 rmesa->hw.eye.cmd[EYE_CMD_0] =
1151 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
1152
1153 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
1154 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1155 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1156 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1157 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1158 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1159 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1160 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1161 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1162 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1163 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1164 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1165 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1166 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1167 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1168 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1169 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1170 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1171
1172 for (i = 0 ; i < 8; i++) {
1173 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1174 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1175 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1176 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1177 }
1178
1179 for (i = 0 ; i < 6; i++) {
1180 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1181 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1182 }
1183
1184 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1185 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1186 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1187 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1188
1189 /* Initial Harware state:
1190 */
1191 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1192 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1193
1194 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1195 R200_FOG_USE_SPEC_ALPHA);
1196
1197 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1198
1199 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1200 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1201 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1202
1203 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1204 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1205 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1206 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1207 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1208 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1209 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1210 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1211 }
1212
1213 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1214 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1215
1216 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1217 ((rmesa->radeon.radeonScreen->depthPitch &
1218 R200_DEPTHPITCH_MASK) |
1219 R200_DEPTH_ENDIAN_NO_SWAP);
1220
1221 if (rmesa->using_hyperz)
1222 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1223
1224 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1225 R200_STENCIL_TEST_ALWAYS |
1226 R200_STENCIL_FAIL_KEEP |
1227 R200_STENCIL_ZPASS_KEEP |
1228 R200_STENCIL_ZFAIL_KEEP |
1229 R200_Z_WRITE_ENABLE);
1230
1231 if (rmesa->using_hyperz) {
1232 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1233 R200_Z_DECOMPRESSION_ENABLE;
1234 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1235 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1236 }
1237
1238 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1239 | R200_TEX_BLEND_0_ENABLE);
1240
1241 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1242 case DRI_CONF_DITHER_XERRORDIFFRESET:
1243 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1244 break;
1245 case DRI_CONF_DITHER_ORDERED:
1246 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1247 break;
1248 }
1249 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1250 DRI_CONF_ROUND_ROUND )
1251 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1252 else
1253 rmesa->radeon.state.color.roundEnable = 0;
1254 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1255 DRI_CONF_COLOR_REDUCTION_DITHER )
1256 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1257 else
1258 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1259
1260 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1261 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1262 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1263
1264 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1265 R200_BFACE_SOLID |
1266 R200_FFACE_SOLID |
1267 R200_FLAT_SHADE_VTX_LAST |
1268 R200_DIFFUSE_SHADE_GOURAUD |
1269 R200_ALPHA_SHADE_GOURAUD |
1270 R200_SPECULAR_SHADE_GOURAUD |
1271 R200_FOG_SHADE_GOURAUD |
1272 R200_DISC_FOG_SHADE_GOURAUD |
1273 R200_VTX_PIX_CENTER_OGL |
1274 R200_ROUND_MODE_TRUNC |
1275 R200_ROUND_PREC_8TH_PIX);
1276
1277 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1278 R200_SCISSOR_ENABLE);
1279
1280 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1281
1282 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1283 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1284 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1285
1286 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1287
1288 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1289 ((0x00 << R200_STENCIL_REF_SHIFT) |
1290 (0xff << R200_STENCIL_MASK_SHIFT) |
1291 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1292
1293 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1294 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1295
1296 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1297
1298 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1299 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1300 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1301 R200_STIPPLE_BIG_BIT_ORDER);
1302
1303
1304 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1305 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1306 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1307 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1308 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1309 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1310 #ifdef MESA_BIG_ENDIAN
1311 R200_VC_32BIT_SWAP;
1312 #else
1313 R200_VC_NO_SWAP;
1314 #endif
1315
1316 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1317 /* Bypass TCL */
1318 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1319 }
1320
1321 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1322 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1323 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1324 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1325 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1326 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1327 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1328 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1329 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1330 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1331 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1332 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1333 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1334 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1335 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1336
1337
1338 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1339 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1340 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1341 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1342 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1343 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1344
1345 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1346 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1347 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1348 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1349 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1350 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1351 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1352 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1353 (/* R200_TEXCOORD_PROJ | */
1354 0x100000); /* Small default bias */
1355 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1356 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1357 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1358 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1359 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1360 }
1361 else {
1362 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1363 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1364 }
1365
1366 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1367 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1368 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1369 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1370 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1371 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1372 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1373 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1374 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1375 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1376 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1377
1378 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1379 (R200_TXC_ARG_A_ZERO |
1380 R200_TXC_ARG_B_ZERO |
1381 R200_TXC_ARG_C_DIFFUSE_COLOR |
1382 R200_TXC_OP_MADD);
1383
1384 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1385 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1386 R200_TXC_SCALE_1X |
1387 R200_TXC_CLAMP_0_1 |
1388 R200_TXC_OUTPUT_REG_R0);
1389
1390 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1391 (R200_TXA_ARG_A_ZERO |
1392 R200_TXA_ARG_B_ZERO |
1393 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1394 R200_TXA_OP_MADD);
1395
1396 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1397 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1398 R200_TXA_SCALE_1X |
1399 R200_TXA_CLAMP_0_1 |
1400 R200_TXA_OUTPUT_REG_R0);
1401 }
1402
1403 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1404 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1405 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1406 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1407 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1408 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1409
1410 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1411 (R200_VAP_TCL_ENABLE |
1412 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1413
1414 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1415 (R200_VPORT_X_SCALE_ENA |
1416 R200_VPORT_Y_SCALE_ENA |
1417 R200_VPORT_Z_SCALE_ENA |
1418 R200_VPORT_X_OFFSET_ENA |
1419 R200_VPORT_Y_OFFSET_ENA |
1420 R200_VPORT_Z_OFFSET_ENA |
1421 /* FIXME: Turn on for tex rect only */
1422 R200_VTX_ST_DENORMALIZED |
1423 R200_VTX_W0_FMT);
1424
1425
1426 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1427 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1428 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1429 ((R200_VTX_Z0 | R200_VTX_W0 |
1430 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1431 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1432 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1433 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1434
1435
1436 /* Matrix selection */
1437 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1438 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1439
1440 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1441 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1442
1443 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1444 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1445
1446 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1447 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1448 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1449 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1450 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1451
1452 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1453 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1454 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1455
1456
1457 /* General TCL state */
1458 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1459 (R200_SPECULAR_LIGHTS |
1460 R200_DIFFUSE_SPECULAR_COMBINE |
1461 R200_LOCAL_LIGHT_VEC_GL |
1462 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1463 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1464
1465 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1466 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1467 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1468 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1469 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1470 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1471 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1472 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1473 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1474
1475 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1476 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1477 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1478 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1479
1480 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1481 (R200_UCP_IN_CLIP_SPACE |
1482 R200_CULL_FRONT_IS_CCW);
1483
1484 /* Texgen/Texmat state */
1485 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1486 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1487 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1488 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1489 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1490 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1491 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1492 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1493 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1494 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1495 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1496 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1497 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1498 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1499 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1500 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1501 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1502
1503
1504 for (i = 0 ; i < 8; i++) {
1505 struct gl_light *l = &ctx->Light.Light[i];
1506 GLenum p = GL_LIGHT0 + i;
1507 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1508
1509 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1510 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1511 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1512 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1513 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1514 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1515 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1516 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1517 &l->ConstantAttenuation );
1518 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1519 &l->LinearAttenuation );
1520 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1521 &l->QuadraticAttenuation );
1522 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1523 }
1524
1525 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1526 ctx->Light.Model.Ambient );
1527
1528 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1529
1530 for (i = 0 ; i < 6; i++) {
1531 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1532 }
1533
1534 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1535 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1536 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1537 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1538 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1539 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1540
1541 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1542 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1543 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1544 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1545
1546 rmesa->hw.eye.cmd[EYE_X] = 0;
1547 rmesa->hw.eye.cmd[EYE_Y] = 0;
1548 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1549 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1550
1551 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1552 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1553
1554 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1555 location? In any case, since point attenuation triggers _needeyecoords,
1556 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1557 isn't set */
1558 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1559 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1560 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1561 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1562 /* no idea what the ptp_vport_scale values are good for, except the
1563 PTSIZE one - hopefully doesn't matter */
1564 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1565 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1566 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1567 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1568 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1569 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1570 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1571 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1572 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1573 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1574 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1575 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1576
1577 r200LightingSpaceChange( ctx );
1578
1579 rmesa->radeon.hw.all_dirty = GL_TRUE;
1580
1581 rcommonInitCmdBuf(&rmesa->radeon);
1582 }