src/myhdl/mux.py

   1 # mux.py
   2
   3 from math import log
   4 from myhdl import *
   5
   6 period = 20  # clk frequency = 50 MHz
   7
   8
   9 @block
  10 def mux4(clk, in_a, in_b, in_c, in_d,
  11          selector, out):
  12     sel_r = Signal(intbv(0)[2:0])
  13     sel25 = Signal(intbv(0)[4:0])
  14
  15     #@always(clk.posedge, reset_n.negedge)
  16     #def logic_reg():
  17     #    if reset_n == 0:
  18     #        out.next = 0
  19     #    else:
  20     #        out.next = count_next
  21
  22     @always(clk.posedge)
  23     def logic_selection():
  24         sel_r.next = selector
  25
  26     @always(clk.posedge)
  27     def logic_next():
  28         if selector != sel_r:
  29             sel25.next = intbv(0)[2:0]
  30         else:
  31             if selector == intbv(0)[2:0]:
  32                 sel25.next = intbv(1)[4:0]
  33             if selector == intbv(1)[2:0]:
  34                 sel25.next = intbv(2)[4:0]
  35             if selector == intbv(2)[2:0]:
  36                 sel25.next = intbv(4)[4:0]
  37             if selector == intbv(3)[2:0]:
  38                 sel25.next = intbv(8)[4:0]
  39
  40     #@always(clk.posedge, clk.negedge)
  41     @always(sel25, in_a, in_b, in_c, in_d)
  42     def make_out():
  43         out.next = bool(in_a if sel25[0] else False) | \
  44                    bool(in_b if sel25[1] else False) | \
  45                    bool(in_c if sel25[2] else False) | \
  46                    bool(in_d if sel25[3] else False)
  47
  48     return instances()  # return all instances
  49
  50
  51 # testbench
  52 @block
  53 def mux_tb():
  54
  55     clk = Signal(bool(0))
  56     in_a = Signal(intbv(0)[1:0])
  57     in_b = Signal(intbv(0)[1:0])
  58     in_c = Signal(intbv(0)[1:0])
  59     in_d = Signal(intbv(0)[1:0])
  60     selector = Signal(intbv(0)[2:0])
  61     out = Signal(bool(0))
  62
  63     mux_inst = mux4(clk, in_a, in_b, in_c, in_d, selector, out)
  64
  65     @instance
  66     def clk_signal():
  67         while True:
  68             clk.next = not clk
  69             if clk:
  70                 in_a.next = not in_a
  71                 if in_a:
  72                     in_b.next = not in_b
  73                     if in_b:
  74                         in_c.next = not in_c
  75                         if in_c:
  76                             in_d.next = not in_d
  77                             if in_d:
  78                                 if selector == 3:
  79                                     selector.next = 0
  80                                 else:
  81                                     selector.next = selector + 1
  82             yield delay(period // 2)
  83
  84     # print simulation data on screen and file
  85     file_data = open("mux.csv", 'w')  # file for saving data
  86     # # print header on screen
  87     s = "{0},{1},{2},{3},{4},{5}".format("in_a", "in_b", "in_c", "in_d",
  88                                          "selector", "out")
  89     print(s)
  90     # # print header to file
  91     file_data.write(s)
  92     # print data on each clock
  93
  94     @always(clk.posedge)
  95     def print_data():
  96         # print on screen
  97         # print.format is not supported in MyHDL 1.0
  98         s = str(in_a) + "," + str(in_b) + "," + str(in_c) + "," + str(in_d)
  99         s = s + "," + str(selector) + "," + str(out)
 100         print(s)
 101
 102         # print in file
 103         # print.format is not supported in MyHDL 1.0
 104         #file_data.write(s + "\n")
 105
 106     return instances()
 107
 108
 109 def main():
 110
 111     clk = Signal(bool(0))
 112     in_a = Signal(intbv(0)[1:0])
 113     in_b = Signal(intbv(0)[1:0])
 114     in_c = Signal(intbv(0)[1:0])
 115     in_d = Signal(intbv(0)[1:0])
 116     selector = Signal(intbv(0)[2:0])
 117     out = Signal(bool(0))
 118
 119     mux_v = mux4(clk, in_a, in_b, in_c, in_d, selector, out)
 120     mux_v.convert(hdl="Verilog", initial_values=True)
 121
 122     # test bench
 123     tb = mux_tb()
 124     tb.convert(hdl="Verilog", initial_values=True)
 125     # keep following lines below the 'tb.convert' line
 126     # otherwise error will be reported
 127     tb.config_sim(trace=True)
 128     tb.run_sim(66 * period)  # run for 15 clock cycle
 129
 130
 131 if __name__ == '__main__':
 132     main()