7bd75a6c721e300e302d2c1d288b8cff5f22e1a7
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26 from nmigen
.compat
.fhdl
.specials
import Memory
27 from nmigen
import Module
, Signal
, Mux
, Elaboratable
28 from nmigen
.utils
import bits_for
29 from nmigen
.cli
import main
30 from nmigen
.lib
.fifo
import FIFOInterface
32 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185 # noqa
35 class Queue(FIFOInterface
, Elaboratable
):
36 def __init__(self
, width
, depth
, fwft
=True, pipe
=False):
37 """ Queue (FIFO) with pipe mode and first-write fall-through capability
39 * :width: width of Queue data in/out
40 * :depth: queue depth. NOTE: may be set to 0 (this is ok)
41 * :fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
42 * :pipe : pipe mode. NOTE: this mode can cause unanticipated
43 problems. when read is enabled, so is w_rdy.
44 therefore if read is enabled, the data ABSOLUTELY MUST
47 fwft mode = True basically means that the data may be transferred
48 combinatorially from input to output.
51 * level: available free space (number of unread entries)
53 w_data = enq_data, w_rdy = enq_ready, w_en = enq_valid
54 r_data = deq_data, r_en = deq_ready, r_rdy = deq_valid
56 FIFOInterface
.__init
__(self
, width
=width
, depth
=depth
, fwft
=fwft
)
59 self
.level
= Signal(bits_for(depth
))
61 def elaborate(self
, platform
):
64 # set up an SRAM. XXX bug in Memory: cannot create SRAM of depth 1
65 ram
= Memory(self
.width
, self
.depth
if self
.depth
> 1 else 2)
66 m
.submodules
.ram
= ram
67 m
.submodules
.ram_read
= ram_read
= ram
.read_port(domain
="comb")
68 m
.submodules
.ram_write
= ram_write
= ram
.write_port()
70 # convenience names, for people familiar with ready/valid terminology
71 # "p" stands for "previous stage", "n" stands for "next stage"
72 # for people familiar with the chisel Decoupled library:
73 # enq is "enqueue" (data in, aka "prev stage"),
74 # deq is "dequeue" (data out, aka "next stage")
75 p_o_ready
= self
.w_rdy
77 enq_data
= self
.w_data
# aka p_i_data
79 n_o_valid
= self
.r_rdy
81 deq_data
= self
.r_data
# aka n_o_data
84 ptr_width
= bits_for(self
.depth
- 1) if self
.depth
> 1 else 0
85 enq_ptr
= Signal(ptr_width
) # cyclic pointer to "insert" point (wrport)
86 deq_ptr
= Signal(ptr_width
) # cyclic pointer to "remove" point (rdport)
87 maybe_full
= Signal() # not reset_less (set by sync)
90 do_enq
= Signal(reset_less
=True)
91 do_deq
= Signal(reset_less
=True)
92 ptr_diff
= Signal(ptr_width
)
93 ptr_match
= Signal(reset_less
=True)
94 empty
= Signal(reset_less
=True)
95 full
= Signal(reset_less
=True)
96 enq_max
= Signal(reset_less
=True)
97 deq_max
= Signal(reset_less
=True)
99 m
.d
.comb
+= [ptr_match
.eq(enq_ptr
== deq_ptr
), # read-ptr = write-ptr
100 ptr_diff
.eq(enq_ptr
- deq_ptr
),
101 enq_max
.eq(enq_ptr
== self
.depth
- 1),
102 deq_max
.eq(deq_ptr
== self
.depth
- 1),
103 empty
.eq(ptr_match
& ~maybe_full
),
104 full
.eq(ptr_match
& maybe_full
),
105 do_enq
.eq(p_o_ready
& p_i_valid
), # write conditions ok
106 do_deq
.eq(n_i_ready
& n_o_valid
), # read conditions ok
108 # set r_rdy and w_rdy (NOTE: see pipe mode below)
109 n_o_valid
.eq(~empty
), # cannot read if empty!
110 p_o_ready
.eq(~full
), # cannot write if full!
112 # set up memory and connect to input and output
113 ram_write
.addr
.eq(enq_ptr
),
114 ram_write
.data
.eq(enq_data
),
115 ram_write
.en
.eq(do_enq
),
116 ram_read
.addr
.eq(deq_ptr
),
117 deq_data
.eq(ram_read
.data
) # NOTE: overridden in fwft mode
120 # under write conditions, SRAM write-pointer moves on next clock
122 m
.d
.sync
+= enq_ptr
.eq(Mux(enq_max
, 0, enq_ptr
+1))
124 # under read conditions, SRAM read-pointer moves on next clock
126 m
.d
.sync
+= deq_ptr
.eq(Mux(deq_max
, 0, deq_ptr
+1))
128 # if read-but-not-write or write-but-not-read, maybe_full set
129 with m
.If(do_enq
!= do_deq
):
130 m
.d
.sync
+= maybe_full
.eq(do_enq
)
132 # first-word fall-through: same as "flow" parameter in Chisel3 Queue
133 # basically instead of relying on the Memory characteristics (which
134 # in FPGAs do not have write-through), then when the queue is empty
135 # take the output directly from the input, i.e. *bypass* the SRAM.
136 # this done combinatorially to give the exact same characteristics
137 # as Memory "write-through"... without relying on a changing API
139 with m
.If(p_i_valid
):
140 m
.d
.comb
+= n_o_valid
.eq(1)
142 m
.d
.comb
+= deq_data
.eq(enq_data
)
143 m
.d
.comb
+= do_deq
.eq(0)
144 with m
.If(n_i_ready
):
145 m
.d
.comb
+= do_enq
.eq(0)
147 # pipe mode: if next stage says it's ready (r_rdy), w_en
148 # *must* declare the input ready (w_rdy).
150 with m
.If(n_i_ready
):
151 m
.d
.comb
+= p_o_ready
.eq(1)
153 # set the count (available free space), optimise on power-of-two
154 if self
.depth
== 1 << ptr_width
: # is depth a power of 2
155 m
.d
.comb
+= self
.level
.eq(
156 Mux(maybe_full
& ptr_match
, self
.depth
, 0) | ptr_diff
)
158 m
.d
.comb
+= self
.level
.eq(Mux(ptr_match
,
159 Mux(maybe_full
, self
.depth
, 0),
160 Mux(deq_ptr
> enq_ptr
,
161 self
.depth
+ ptr_diff
,
167 if __name__
== "__main__":
168 reg_stage
= Queue(1, 1, pipe
=True)
169 break_ready_chain_stage
= Queue(1, 1, pipe
=True, fwft
=True)
173 def queue_ports(queue
, name_prefix
):
175 for name
in ["level",
179 port
= getattr(queue
, name
)
180 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
181 m
.d
.comb
+= signal
.eq(port
)
182 retval
.append(signal
)
186 port
= getattr(queue
, name
)
187 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
188 m
.d
.comb
+= port
.eq(signal
)
189 retval
.append(signal
)
192 m
.submodules
.reg_stage
= reg_stage
193 ports
+= queue_ports(reg_stage
, "reg_stage_")
194 m
.submodules
.break_ready_chain_stage
= break_ready_chain_stage
195 ports
+= queue_ports(break_ready_chain_stage
, "break_ready_chain_stage_")