2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
78 static midgard_block
*
79 create_empty_block(compiler_context
*ctx
)
81 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
83 blk
->predecessors
= _mesa_set_create(blk
,
85 _mesa_key_pointer_equal
);
87 blk
->source_id
= ctx
->block_source_count
++;
93 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
99 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
100 if (block
->successors
[i
] == successor
)
104 block
->successors
[block
->nr_successors
++] = successor
;
105 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
107 /* Note the predecessor in the other direction */
108 _mesa_set_add(successor
->predecessors
, block
);
112 schedule_barrier(compiler_context
*ctx
)
114 midgard_block
*temp
= ctx
->after_block
;
115 ctx
->after_block
= create_empty_block(ctx
);
117 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
118 list_inithead(&ctx
->after_block
->instructions
);
119 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
120 ctx
->current_block
= ctx
->after_block
;
121 ctx
->after_block
= temp
;
124 /* Helpers to generate midgard_instruction's using macro magic, since every
125 * driver seems to do it that way */
127 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
129 #define M_LOAD_STORE(name, store) \
130 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
131 midgard_instruction i = { \
132 .type = TAG_LOAD_STORE_4, \
135 .src = { ~0, ~0, ~0 }, \
136 .swizzle = SWIZZLE_IDENTITY_4, \
138 .op = midgard_op_##name, \
151 #define M_LOAD(name) M_LOAD_STORE(name, false)
152 #define M_STORE(name) M_LOAD_STORE(name, true)
154 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
155 * the corresponding Midgard source */
157 static midgard_vector_alu_src
158 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
159 bool half
, bool sext
)
161 /* Figure out how many components there are so we can adjust.
162 * Specifically we want to broadcast the last channel so things like
166 if (broadcast_count
&& src
) {
167 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
169 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
170 src
->swizzle
[c
] = last_component
;
174 midgard_vector_alu_src alu_src
= {
181 alu_src
.mod
= midgard_int_normal
;
183 /* Sign/zero-extend if needed */
187 midgard_int_sign_extend
188 : midgard_int_zero_extend
;
191 /* These should have been lowered away */
193 assert(!(src
->abs
|| src
->negate
));
196 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
202 /* load/store instructions have both 32-bit and 16-bit variants, depending on
203 * whether we are using vectors composed of highp or mediump. At the moment, we
204 * don't support half-floats -- this requires changes in other parts of the
205 * compiler -- therefore the 16-bit versions are commented out. */
207 //M_LOAD(ld_attr_16);
209 //M_LOAD(ld_vary_16);
214 M_LOAD(ld_color_buffer_8
);
215 //M_STORE(st_vary_16);
217 M_LOAD(ld_cubemap_coords
);
218 M_LOAD(ld_compute_id
);
220 static midgard_instruction
221 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
223 midgard_branch_cond branch
= {
231 memcpy(&compact
, &branch
, sizeof(branch
));
233 midgard_instruction ins
= {
235 .unit
= ALU_ENAB_BR_COMPACT
,
236 .prepacked_branch
= true,
237 .compact_branch
= true,
238 .br_compact
= compact
,
240 .src
= { ~0, ~0, ~0 },
243 if (op
== midgard_jmp_writeout_op_writeout
)
249 static midgard_instruction
250 v_branch(bool conditional
, bool invert
)
252 midgard_instruction ins
= {
254 .unit
= ALU_ENAB_BRANCH
,
255 .compact_branch
= true,
257 .conditional
= conditional
,
258 .invert_conditional
= invert
261 .src
= { ~0, ~0, ~0 },
267 static midgard_branch_extended
268 midgard_create_branch_extended( midgard_condition cond
,
269 midgard_jmp_writeout_op op
,
271 signed quadword_offset
)
273 /* The condition code is actually a LUT describing a function to
274 * combine multiple condition codes. However, we only support a single
275 * condition code at the moment, so we just duplicate over a bunch of
278 uint16_t duplicated_cond
=
288 midgard_branch_extended branch
= {
290 .dest_tag
= dest_tag
,
291 .offset
= quadword_offset
,
292 .cond
= duplicated_cond
299 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
301 ins
->has_constants
= true;
302 memcpy(&ins
->constants
, constants
, 16);
306 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
308 return glsl_count_attribute_slots(type
, false);
311 /* Lower fdot2 to a vector multiplication followed by channel addition */
313 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
315 if (alu
->op
!= nir_op_fdot2
)
318 b
->cursor
= nir_before_instr(&alu
->instr
);
320 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
321 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
323 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
325 nir_ssa_def
*sum
= nir_fadd(b
,
326 nir_channel(b
, product
, 0),
327 nir_channel(b
, product
, 1));
329 /* Replace the fdot2 with this sum */
330 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
334 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
336 /* This is way too meta */
337 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
338 unsigned idx_idx
= is_store
? 1 : 0;
340 nir_src index
= instr
->src
[idx_idx
];
341 assert(nir_src_is_const(index
));
342 uint32_t uindex
= nir_src_as_uint(index
);
344 return PAN_SYSVAL(SSBO
, uindex
);
348 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
350 switch (instr
->intrinsic
) {
351 case nir_intrinsic_load_viewport_scale
:
352 return PAN_SYSVAL_VIEWPORT_SCALE
;
353 case nir_intrinsic_load_viewport_offset
:
354 return PAN_SYSVAL_VIEWPORT_OFFSET
;
355 case nir_intrinsic_load_num_work_groups
:
356 return PAN_SYSVAL_NUM_WORK_GROUPS
;
357 case nir_intrinsic_load_ssbo
:
358 case nir_intrinsic_store_ssbo
:
359 return midgard_sysval_for_ssbo(instr
);
365 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
368 nir_intrinsic_instr
*intr
;
369 nir_dest
*dst
= NULL
;
373 bool is_store
= false;
375 switch (instr
->type
) {
376 case nir_instr_type_intrinsic
:
377 intr
= nir_instr_as_intrinsic(instr
);
378 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
380 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
382 case nir_instr_type_tex
:
383 tex
= nir_instr_as_tex(instr
);
384 if (tex
->op
!= nir_texop_txs
)
387 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
388 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
389 nir_tex_instr_dest_size(tex
) -
390 (tex
->is_array
? 1 : 0),
398 if (dest
&& dst
&& !is_store
)
399 *dest
= nir_dest_index(ctx
, dst
);
405 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
409 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
413 /* We have a sysval load; check if it's already been assigned */
415 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
418 /* It hasn't -- so assign it now! */
420 unsigned id
= ctx
->sysval_count
++;
421 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
422 ctx
->sysvals
[id
] = sysval
;
426 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
428 ctx
->sysval_count
= 0;
430 nir_foreach_function(function
, shader
) {
431 if (!function
->impl
) continue;
433 nir_foreach_block(block
, function
->impl
) {
434 nir_foreach_instr_safe(instr
, block
) {
435 midgard_nir_assign_sysval_body(ctx
, instr
);
442 midgard_nir_lower_fdot2(nir_shader
*shader
)
444 bool progress
= false;
446 nir_foreach_function(function
, shader
) {
447 if (!function
->impl
) continue;
450 nir_builder
*b
= &_b
;
451 nir_builder_init(b
, function
->impl
);
453 nir_foreach_block(block
, function
->impl
) {
454 nir_foreach_instr_safe(instr
, block
) {
455 if (instr
->type
!= nir_instr_type_alu
) continue;
457 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
458 midgard_nir_lower_fdot2_body(b
, alu
);
464 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
471 /* Flushes undefined values to zero */
474 optimise_nir(nir_shader
*nir
)
477 unsigned lower_flrp
=
478 (nir
->options
->lower_flrp16
? 16 : 0) |
479 (nir
->options
->lower_flrp32
? 32 : 0) |
480 (nir
->options
->lower_flrp64
? 64 : 0);
482 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
483 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
484 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
486 nir_lower_tex_options lower_tex_options
= {
487 .lower_txs_lod
= true,
491 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
496 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
497 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
499 NIR_PASS(progress
, nir
, nir_copy_prop
);
500 NIR_PASS(progress
, nir
, nir_opt_dce
);
501 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
502 NIR_PASS(progress
, nir
, nir_opt_cse
);
503 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
504 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
505 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
507 if (lower_flrp
!= 0) {
508 bool lower_flrp_progress
= false;
509 NIR_PASS(lower_flrp_progress
,
513 false /* always_precise */,
514 nir
->options
->lower_ffma
);
515 if (lower_flrp_progress
) {
516 NIR_PASS(progress
, nir
,
517 nir_opt_constant_folding
);
521 /* Nothing should rematerialize any flrps, so we only
522 * need to do this lowering once.
527 NIR_PASS(progress
, nir
, nir_opt_undef
);
528 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
530 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
533 nir_var_function_temp
);
535 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
538 /* Must be run at the end to prevent creation of fsin/fcos ops */
539 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
544 NIR_PASS(progress
, nir
, nir_opt_dce
);
545 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
546 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
547 NIR_PASS(progress
, nir
, nir_copy_prop
);
550 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
552 /* We implement booleans as 32-bit 0/~0 */
553 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
555 /* Now that booleans are lowered, we can run out late opts */
556 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
558 /* Lower mods for float ops only. Integer ops don't support modifiers
559 * (saturate doesn't make sense on integers, neg/abs require dedicated
562 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
563 NIR_PASS(progress
, nir
, nir_copy_prop
);
564 NIR_PASS(progress
, nir
, nir_opt_dce
);
566 /* Take us out of SSA */
567 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
568 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
570 /* We are a vector architecture; write combine where possible */
571 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
572 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
574 NIR_PASS(progress
, nir
, nir_opt_dce
);
577 /* Do not actually emit a load; instead, cache the constant for inlining */
580 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
582 nir_ssa_def def
= instr
->def
;
584 float *v
= rzalloc_array(NULL
, float, 4);
585 nir_const_value_to_array(v
, instr
->value
, instr
->def
.num_components
, f32
);
587 /* Shifted for SSA, +1 for off-by-one */
588 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
591 /* Normally constants are embedded implicitly, but for I/O and such we have to
592 * explicitly emit a move with the constant source */
595 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
597 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
599 if (constant_value
) {
600 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
601 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
602 emit_mir_instruction(ctx
, ins
);
607 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
609 unsigned comp
= src
->swizzle
[0];
611 for (unsigned c
= 1; c
< nr_components
; ++c
) {
612 if (src
->swizzle
[c
] != comp
)
619 #define ALU_CASE(nir, _op) \
621 op = midgard_alu_op_##_op; \
622 assert(src_bitsize == dst_bitsize); \
625 #define ALU_CASE_BCAST(nir, _op, count) \
627 op = midgard_alu_op_##_op; \
628 broadcast_swizzle = count; \
629 assert(src_bitsize == dst_bitsize); \
632 nir_is_fzero_constant(nir_src src
)
634 if (!nir_src_is_const(src
))
637 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
638 if (nir_src_comp_as_float(src
, c
) != 0.0)
645 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
646 * special treatment override this anyway. */
648 static midgard_reg_mode
649 reg_mode_for_nir(nir_alu_instr
*instr
)
651 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
653 switch (src_bitsize
) {
655 return midgard_reg_mode_8
;
657 return midgard_reg_mode_16
;
659 return midgard_reg_mode_32
;
661 return midgard_reg_mode_64
;
663 unreachable("Invalid bit size");
668 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
670 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
671 * is handled elsewhere */
673 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
674 midgard_emit_derivatives(ctx
, instr
);
678 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
680 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
681 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
682 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
684 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
685 * supported. A few do not and are commented for now. Also, there are a
686 * number of NIR ops which Midgard does not support and need to be
687 * lowered, also TODO. This switch block emits the opcode and calling
688 * convention of the Midgard instruction; actual packing is done in
693 /* Number of components valid to check for the instruction (the rest
694 * will be forced to the last), or 0 to use as-is. Relevant as
695 * ball-type instructions have a channel count in NIR but are all vec4
698 unsigned broadcast_swizzle
= 0;
700 /* What register mode should we operate in? */
701 midgard_reg_mode reg_mode
=
702 reg_mode_for_nir(instr
);
704 /* Do we need a destination override? Used for inline
707 midgard_dest_override dest_override
=
708 midgard_dest_override_none
;
710 /* Should we use a smaller respective source and sign-extend? */
712 bool half_1
= false, sext_1
= false;
713 bool half_2
= false, sext_2
= false;
715 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
716 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
719 ALU_CASE(fadd
, fadd
);
720 ALU_CASE(fmul
, fmul
);
721 ALU_CASE(fmin
, fmin
);
722 ALU_CASE(fmax
, fmax
);
723 ALU_CASE(imin
, imin
);
724 ALU_CASE(imax
, imax
);
725 ALU_CASE(umin
, umin
);
726 ALU_CASE(umax
, umax
);
727 ALU_CASE(ffloor
, ffloor
);
728 ALU_CASE(fround_even
, froundeven
);
729 ALU_CASE(ftrunc
, ftrunc
);
730 ALU_CASE(fceil
, fceil
);
731 ALU_CASE(fdot3
, fdot3
);
732 ALU_CASE(fdot4
, fdot4
);
733 ALU_CASE(iadd
, iadd
);
734 ALU_CASE(isub
, isub
);
735 ALU_CASE(imul
, imul
);
737 /* Zero shoved as second-arg */
738 ALU_CASE(iabs
, iabsdiff
);
742 ALU_CASE(feq32
, feq
);
743 ALU_CASE(fne32
, fne
);
744 ALU_CASE(flt32
, flt
);
745 ALU_CASE(ieq32
, ieq
);
746 ALU_CASE(ine32
, ine
);
747 ALU_CASE(ilt32
, ilt
);
748 ALU_CASE(ult32
, ult
);
750 /* We don't have a native b2f32 instruction. Instead, like many
751 * GPUs, we exploit booleans as 0/~0 for false/true, and
752 * correspondingly AND
753 * by 1.0 to do the type conversion. For the moment, prime us
756 * iand [whatever], #0
758 * At the end of emit_alu (as MIR), we'll fix-up the constant
761 ALU_CASE(b2f32
, iand
);
762 ALU_CASE(b2i32
, iand
);
764 /* Likewise, we don't have a dedicated f2b32 instruction, but
765 * we can do a "not equal to 0.0" test. */
767 ALU_CASE(f2b32
, fne
);
768 ALU_CASE(i2b32
, ine
);
770 ALU_CASE(frcp
, frcp
);
771 ALU_CASE(frsq
, frsqrt
);
772 ALU_CASE(fsqrt
, fsqrt
);
773 ALU_CASE(fexp2
, fexp2
);
774 ALU_CASE(flog2
, flog2
);
776 ALU_CASE(f2i32
, f2i_rtz
);
777 ALU_CASE(f2u32
, f2u_rtz
);
778 ALU_CASE(i2f32
, i2f_rtz
);
779 ALU_CASE(u2f32
, u2f_rtz
);
781 ALU_CASE(f2i16
, f2i_rtz
);
782 ALU_CASE(f2u16
, f2u_rtz
);
783 ALU_CASE(i2f16
, i2f_rtz
);
784 ALU_CASE(u2f16
, u2f_rtz
);
786 ALU_CASE(fsin
, fsin
);
787 ALU_CASE(fcos
, fcos
);
789 /* We'll set invert */
790 ALU_CASE(inot
, imov
);
791 ALU_CASE(iand
, iand
);
793 ALU_CASE(ixor
, ixor
);
794 ALU_CASE(ishl
, ishl
);
795 ALU_CASE(ishr
, iasr
);
796 ALU_CASE(ushr
, ilsr
);
798 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
799 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
800 ALU_CASE(b32all_fequal4
, fball_eq
);
802 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
803 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
804 ALU_CASE(b32any_fnequal4
, fbany_neq
);
806 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
807 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
808 ALU_CASE(b32all_iequal4
, iball_eq
);
810 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
811 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
812 ALU_CASE(b32any_inequal4
, ibany_neq
);
814 /* Source mods will be shoved in later */
815 ALU_CASE(fabs
, fmov
);
816 ALU_CASE(fneg
, fmov
);
817 ALU_CASE(fsat
, fmov
);
819 /* For size conversion, we use a move. Ideally though we would squash
820 * these ops together; maybe that has to happen after in NIR as part of
821 * propagation...? An earlier algebraic pass ensured we step down by
822 * only / exactly one size. If stepping down, we use a dest override to
823 * reduce the size; if stepping up, we use a larger-sized move with a
824 * half source and a sign/zero-extension modifier */
830 /* If we end up upscale, we'll need a sign-extend on the
831 * operand (the second argument) */
839 op
= midgard_alu_op_imov
;
841 if (dst_bitsize
== (src_bitsize
* 2)) {
845 /* Use a greater register mode */
847 } else if (src_bitsize
== (dst_bitsize
* 2)) {
848 /* Converting down */
849 dest_override
= midgard_dest_override_lower
;
856 assert(src_bitsize
== 32);
858 op
= midgard_alu_op_fmov
;
859 dest_override
= midgard_dest_override_lower
;
864 assert(src_bitsize
== 16);
866 op
= midgard_alu_op_fmov
;
873 /* For greater-or-equal, we lower to less-or-equal and flip the
881 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
882 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
883 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
884 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
887 /* Swap via temporary */
888 nir_alu_src temp
= instr
->src
[1];
889 instr
->src
[1] = instr
->src
[0];
890 instr
->src
[0] = temp
;
895 case nir_op_b32csel
: {
896 /* Midgard features both fcsel and icsel, depending on
897 * the type of the arguments/output. However, as long
898 * as we're careful we can _always_ use icsel and
899 * _never_ need fcsel, since the latter does additional
900 * floating-point-specific processing whereas the
901 * former just moves bits on the wire. It's not obvious
902 * why these are separate opcodes, save for the ability
903 * to do things like sat/pos/abs/neg for free */
905 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
906 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
908 /* The condition is the first argument; move the other
909 * arguments up one to be a binary instruction for
910 * Midgard with the condition last */
912 nir_alu_src temp
= instr
->src
[2];
914 instr
->src
[2] = instr
->src
[0];
915 instr
->src
[0] = instr
->src
[1];
916 instr
->src
[1] = temp
;
922 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
927 /* Midgard can perform certain modifiers on output of an ALU op */
930 if (midgard_is_integer_out_op(op
)) {
931 outmod
= midgard_outmod_int_wrap
;
933 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
934 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
937 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
939 if (instr
->op
== nir_op_fmax
) {
940 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
941 op
= midgard_alu_op_fmov
;
943 outmod
= midgard_outmod_pos
;
944 instr
->src
[0] = instr
->src
[1];
945 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
946 op
= midgard_alu_op_fmov
;
948 outmod
= midgard_outmod_pos
;
952 /* Fetch unit, quirks, etc information */
953 unsigned opcode_props
= alu_opcode_props
[op
].props
;
954 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
956 /* src0 will always exist afaik, but src1 will not for 1-argument
957 * instructions. The latter can only be fetched if the instruction
958 * needs it, or else we may segfault. */
960 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
961 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
962 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
963 assert(nr_inputs
<= 3);
965 /* Rather than use the instruction generation helpers, we do it
966 * ourselves here to avoid the mess */
968 midgard_instruction ins
= {
971 quirk_flipped_r24
? ~0 : src0
,
972 quirk_flipped_r24
? src0
: src1
,
978 nir_alu_src
*nirmods
[3] = { NULL
};
980 if (nr_inputs
>= 2) {
981 nirmods
[0] = &instr
->src
[0];
982 nirmods
[1] = &instr
->src
[1];
983 } else if (nr_inputs
== 1) {
984 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
990 nirmods
[2] = &instr
->src
[2];
992 /* These were lowered to a move, so apply the corresponding mod */
994 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
995 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
997 if (instr
->op
== nir_op_fneg
)
998 s
->negate
= !s
->negate
;
1000 if (instr
->op
== nir_op_fabs
)
1004 bool is_int
= midgard_is_integer_op(op
);
1006 ins
.mask
= mask_of(nr_components
);
1008 midgard_vector_alu alu
= {
1010 .reg_mode
= reg_mode
,
1011 .dest_override
= dest_override
,
1014 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1015 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1018 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1021 ins
.mask
&= instr
->dest
.write_mask
;
1023 for (unsigned m
= 0; m
< 3; ++m
) {
1027 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
1028 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
1030 /* Replicate. TODO: remove when vec16 lands */
1031 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
1032 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1035 if (nr_inputs
== 3) {
1036 /* Conditions can't have mods */
1037 assert(!nirmods
[2]->abs
);
1038 assert(!nirmods
[2]->negate
);
1043 /* Late fixup for emulated instructions */
1045 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1046 /* Presently, our second argument is an inline #0 constant.
1047 * Switch over to an embedded 1.0 constant (that can't fit
1048 * inline, since we're 32-bit, not 16-bit like the inline
1051 ins
.has_inline_constant
= false;
1052 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1053 ins
.has_constants
= true;
1055 if (instr
->op
== nir_op_b2f32
) {
1057 memcpy(&ins
.constants
, &f
, sizeof(float));
1059 ins
.constants
[0] = 1;
1063 for (unsigned c
= 0; c
< 16; ++c
)
1064 ins
.swizzle
[1][c
] = 0;
1065 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1066 /* Lots of instructions need a 0 plonked in */
1067 ins
.has_inline_constant
= false;
1068 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1069 ins
.has_constants
= true;
1070 ins
.constants
[0] = 0;
1072 for (unsigned c
= 0; c
< 16; ++c
)
1073 ins
.swizzle
[1][c
] = 0;
1074 } else if (instr
->op
== nir_op_inot
) {
1078 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1079 /* To avoid duplicating the lookup tables (probably), true LUT
1080 * instructions can only operate as if they were scalars. Lower
1081 * them here by changing the component. */
1083 unsigned orig_mask
= ins
.mask
;
1085 for (int i
= 0; i
< nr_components
; ++i
) {
1086 /* Mask the associated component, dropping the
1087 * instruction if needed */
1090 ins
.mask
&= orig_mask
;
1095 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1096 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1098 emit_mir_instruction(ctx
, ins
);
1101 emit_mir_instruction(ctx
, ins
);
1108 mir_mask_for_intr(nir_instr
*instr
, bool is_read
)
1110 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1113 return mask_of(nir_intrinsic_dest_components(intr
));
1115 return nir_intrinsic_write_mask(intr
);
1118 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1119 * optimized) versions of UBO #0 */
1121 midgard_instruction
*
1123 compiler_context
*ctx
,
1127 nir_src
*indirect_offset
,
1130 /* TODO: half-floats */
1132 midgard_instruction ins
= m_ld_ubo_int4(dest
, offset
);
1134 /* TODO: Don't split */
1135 ins
.load_store
.varying_parameters
= (offset
& 0x7F) << 3;
1136 ins
.load_store
.address
= offset
>> 7;
1137 ins
.mask
= mir_mask_for_intr(instr
, true);
1139 if (indirect_offset
) {
1140 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1141 ins
.load_store
.arg_2
= 0x80;
1143 ins
.load_store
.arg_2
= 0x1E;
1146 ins
.load_store
.arg_1
= index
;
1148 return emit_mir_instruction(ctx
, ins
);
1151 /* SSBO reads are like UBO reads if you squint */
1155 compiler_context
*ctx
,
1160 nir_src
*indirect_offset
,
1165 midgard_instruction ins
;
1168 ins
= m_ld_int4(srcdest
, offset
);
1170 ins
= m_st_int4(srcdest
, offset
);
1172 /* SSBO reads use a generic memory read interface, so we need the
1173 * address of the SSBO as the first argument. This is a sysval. */
1175 unsigned addr
= make_compiler_temp(ctx
);
1176 emit_sysval_read(ctx
, instr
, addr
, 2);
1178 /* The source array:
1180 * src[0] = store ? value : unused
1184 * We would like arg_1 = the address and
1185 * arg_2 = the offset.
1190 /* TODO: What is this? It looks superficially like a shift << 5, but
1191 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1192 * indirect offset. */
1194 if (indirect_offset
) {
1195 ins
.load_store
.arg_1
|= 0xE0;
1196 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1198 ins
.load_store
.arg_2
= 0x7E;
1201 /* TODO: Bounds check */
1203 /* Finally, we emit the direct offset */
1205 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1206 ins
.load_store
.address
= (offset
>> 9);
1207 ins
.mask
= mir_mask_for_intr(instr
, is_read
);
1209 emit_mir_instruction(ctx
, ins
);
1214 compiler_context
*ctx
,
1215 unsigned dest
, unsigned offset
,
1216 unsigned nr_comp
, unsigned component
,
1217 nir_src
*indirect_offset
, nir_alu_type type
)
1219 /* XXX: Half-floats? */
1220 /* TODO: swizzle, mask */
1222 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1223 ins
.mask
= mask_of(nr_comp
);
1225 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1226 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1228 midgard_varying_parameter p
= {
1230 .interpolation
= midgard_interp_default
,
1231 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1235 memcpy(&u
, &p
, sizeof(p
));
1236 ins
.load_store
.varying_parameters
= u
;
1238 if (indirect_offset
)
1239 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1241 ins
.load_store
.arg_2
= 0x1E;
1243 ins
.load_store
.arg_1
= 0x9E;
1245 /* Use the type appropriate load */
1249 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1252 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1254 case nir_type_float
:
1255 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1258 unreachable("Attempted to load unknown type");
1262 emit_mir_instruction(ctx
, ins
);
1266 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1267 unsigned nr_components
)
1271 /* Figure out which uniform this is */
1272 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1273 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1275 if (dest_override
>= 0)
1276 dest
= dest_override
;
1278 /* Sysvals are prefix uniforms */
1279 unsigned uniform
= ((uintptr_t) val
) - 1;
1281 /* Emit the read itself -- this is never indirect */
1282 midgard_instruction
*ins
=
1283 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1285 ins
->mask
= mask_of(nr_components
);
1289 compute_builtin_arg(nir_op op
)
1292 case nir_intrinsic_load_work_group_id
:
1294 case nir_intrinsic_load_local_invocation_id
:
1297 unreachable("Invalid compute paramater loaded");
1301 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1302 * Handle MRT here */
1305 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1307 emit_explicit_constant(ctx
, src
, src
);
1309 /* If we're doing MRT, we need to specify the render target */
1311 midgard_instruction rt_move
= {
1316 /* We'll write to r1.z */
1317 rt_move
= v_mov(~0, SSA_FIXED_REGISTER(1));
1318 rt_move
.mask
= 1 << COMPONENT_Z
;
1319 rt_move
.unit
= UNIT_SADD
;
1321 /* r1.z = (rt * 0x100) */
1322 rt_move
.has_inline_constant
= true;
1323 rt_move
.inline_constant
= (rt
* 0x100);
1326 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1329 emit_mir_instruction(ctx
, rt_move
);
1332 /* Next, generate the branch. For R render targets in the writeout, the
1333 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1335 unsigned outputs
= ctx
->is_blend
? 1 : ctx
->nir
->num_outputs
;
1336 unsigned offset
= (2 * (outputs
- 1)) + rt
;
1338 struct midgard_instruction ins
=
1339 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1341 /* Add dependencies */
1343 ins
.src
[1] = rt_move
.dest
;
1345 /* Emit the branch */
1346 emit_mir_instruction(ctx
, ins
);
1350 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1352 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1353 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1354 ins
.mask
= mask_of(3);
1355 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1356 emit_mir_instruction(ctx
, ins
);
1359 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1361 unsigned offset
= 0, reg
;
1363 switch (instr
->intrinsic
) {
1364 case nir_intrinsic_discard_if
:
1365 case nir_intrinsic_discard
: {
1366 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1367 struct midgard_instruction discard
= v_branch(conditional
, false);
1368 discard
.branch
.target_type
= TARGET_DISCARD
;
1371 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1373 emit_mir_instruction(ctx
, discard
);
1374 schedule_barrier(ctx
);
1379 case nir_intrinsic_load_uniform
:
1380 case nir_intrinsic_load_ubo
:
1381 case nir_intrinsic_load_ssbo
:
1382 case nir_intrinsic_load_input
: {
1383 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1384 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1385 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1387 /* Get the base type of the intrinsic */
1388 /* TODO: Infer type? Does it matter? */
1390 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1391 t
= nir_alu_type_get_base_type(t
);
1393 if (!(is_ubo
|| is_ssbo
)) {
1394 offset
= nir_intrinsic_base(instr
);
1397 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1399 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1401 bool direct
= nir_src_is_const(*src_offset
);
1402 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1405 offset
+= nir_src_as_uint(*src_offset
);
1407 /* We may need to apply a fractional offset */
1408 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1409 nir_intrinsic_component(instr
) : 0;
1410 reg
= nir_dest_index(ctx
, &instr
->dest
);
1412 if (is_uniform
&& !ctx
->is_blend
) {
1413 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1414 } else if (is_ubo
) {
1415 nir_src index
= instr
->src
[0];
1417 /* We don't yet support indirect UBOs. For indirect
1418 * block numbers (if that's possible), we don't know
1419 * enough about the hardware yet. For indirect sources,
1420 * we know what we need but we need to add some NIR
1421 * support for lowering correctly with respect to
1424 assert(nir_src_is_const(index
));
1425 assert(nir_src_is_const(*src_offset
));
1427 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1428 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1429 } else if (is_ssbo
) {
1430 nir_src index
= instr
->src
[0];
1431 assert(nir_src_is_const(index
));
1432 uint32_t uindex
= nir_src_as_uint(index
);
1434 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1435 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1436 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1437 } else if (ctx
->is_blend
) {
1438 /* For blend shaders, load the input color, which is
1439 * preloaded to r0 */
1441 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1442 emit_mir_instruction(ctx
, move
);
1443 schedule_barrier(ctx
);
1444 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1445 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1446 ins
.load_store
.arg_1
= 0x1E;
1447 ins
.load_store
.arg_2
= 0x1E;
1448 ins
.mask
= mask_of(nr_comp
);
1450 /* Use the type appropriate load */
1454 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1457 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1459 case nir_type_float
:
1460 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1463 unreachable("Attempted to load unknown type");
1467 emit_mir_instruction(ctx
, ins
);
1469 DBG("Unknown load\n");
1476 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1478 case nir_intrinsic_load_raw_output_pan
:
1479 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1480 reg
= nir_dest_index(ctx
, &instr
->dest
);
1481 assert(ctx
->is_blend
);
1483 /* T720 and below use different blend opcodes with slightly
1484 * different semantics than T760 and up */
1486 midgard_instruction ld
= m_ld_color_buffer_8(reg
, 0);
1487 bool old_blend
= ctx
->gpu_id
< 0x750;
1489 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1490 ld
.load_store
.op
= old_blend
?
1491 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1492 midgard_op_ld_color_buffer_u8_as_fp16
;
1495 ld
.load_store
.address
= 1;
1496 ld
.load_store
.arg_2
= 0x1E;
1499 for (unsigned c
= 2; c
< 16; ++c
)
1500 ld
.swizzle
[0][c
] = 0;
1503 emit_mir_instruction(ctx
, ld
);
1506 case nir_intrinsic_load_blend_const_color_rgba
: {
1507 assert(ctx
->is_blend
);
1508 reg
= nir_dest_index(ctx
, &instr
->dest
);
1510 /* Blend constants are embedded directly in the shader and
1511 * patched in, so we use some magic routing */
1513 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1514 ins
.has_constants
= true;
1515 ins
.has_blend_constant
= true;
1516 emit_mir_instruction(ctx
, ins
);
1520 case nir_intrinsic_store_output
:
1521 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1523 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1525 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1527 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1528 /* Determine number of render targets */
1529 emit_fragment_store(ctx
, reg
, offset
);
1530 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1531 /* We should have been vectorized, though we don't
1532 * currently check that st_vary is emitted only once
1533 * per slot (this is relevant, since there's not a mask
1534 * parameter available on the store [set to 0 by the
1535 * blob]). We do respect the component by adjusting the
1536 * swizzle. If this is a constant source, we'll need to
1537 * emit that explicitly. */
1539 emit_explicit_constant(ctx
, reg
, reg
);
1541 unsigned component
= nir_intrinsic_component(instr
);
1542 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1544 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1545 st
.load_store
.arg_1
= 0x9E;
1546 st
.load_store
.arg_2
= 0x1E;
1548 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
[0]); ++i
)
1549 st
.swizzle
[0][i
] = MIN2(i
+ component
, nr_comp
);
1551 emit_mir_instruction(ctx
, st
);
1553 DBG("Unknown store\n");
1559 /* Special case of store_output for lowered blend shaders */
1560 case nir_intrinsic_store_raw_output_pan
:
1561 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1562 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1563 emit_fragment_store(ctx
, reg
, 0);
1567 case nir_intrinsic_store_ssbo
:
1568 assert(nir_src_is_const(instr
->src
[1]));
1570 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1571 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1572 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1573 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1575 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1577 emit_explicit_constant(ctx
, reg
, reg
);
1578 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1581 case nir_intrinsic_load_viewport_scale
:
1582 case nir_intrinsic_load_viewport_offset
:
1583 case nir_intrinsic_load_num_work_groups
:
1584 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1587 case nir_intrinsic_load_work_group_id
:
1588 case nir_intrinsic_load_local_invocation_id
:
1589 emit_compute_builtin(ctx
, instr
);
1593 printf ("Unhandled intrinsic\n");
1600 midgard_tex_format(enum glsl_sampler_dim dim
)
1603 case GLSL_SAMPLER_DIM_1D
:
1604 case GLSL_SAMPLER_DIM_BUF
:
1607 case GLSL_SAMPLER_DIM_2D
:
1608 case GLSL_SAMPLER_DIM_EXTERNAL
:
1609 case GLSL_SAMPLER_DIM_RECT
:
1612 case GLSL_SAMPLER_DIM_3D
:
1615 case GLSL_SAMPLER_DIM_CUBE
:
1616 return MALI_TEX_CUBE
;
1619 DBG("Unknown sampler dim type\n");
1625 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1629 pan_attach_constant_bias(
1630 compiler_context
*ctx
,
1632 midgard_texture_word
*word
)
1634 /* To attach as constant, it has to *be* constant */
1636 if (!nir_src_is_const(lod
))
1639 float f
= nir_src_as_float(lod
);
1641 /* Break into fixed-point */
1643 float lod_frac
= f
- lod_int
;
1645 /* Carry over negative fractions */
1646 if (lod_frac
< 0.0) {
1652 word
->bias
= float_to_ubyte(lod_frac
);
1653 word
->bias_int
= lod_int
;
1658 static enum mali_sampler_type
1659 midgard_sampler_type(nir_alu_type t
) {
1660 switch (nir_alu_type_get_base_type(t
))
1662 case nir_type_float
:
1663 return MALI_SAMPLER_FLOAT
;
1665 return MALI_SAMPLER_SIGNED
;
1667 return MALI_SAMPLER_UNSIGNED
;
1669 unreachable("Unknown sampler type");
1674 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1675 unsigned midgard_texop
)
1678 //assert (!instr->sampler);
1679 //assert (!instr->texture_array_size);
1681 int texture_index
= instr
->texture_index
;
1682 int sampler_index
= texture_index
;
1684 /* No helper to build texture words -- we do it all here */
1685 midgard_instruction ins
= {
1686 .type
= TAG_TEXTURE_4
,
1688 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1689 .src
= { ~0, ~0, ~0 },
1690 .swizzle
= SWIZZLE_IDENTITY_4
,
1692 .op
= midgard_texop
,
1693 .format
= midgard_tex_format(instr
->sampler_dim
),
1694 .texture_handle
= texture_index
,
1695 .sampler_handle
= sampler_index
,
1701 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1705 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1706 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1707 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1709 switch (instr
->src
[i
].src_type
) {
1710 case nir_tex_src_coord
: {
1711 emit_explicit_constant(ctx
, index
, index
);
1713 /* Texelfetch coordinates uses all four elements
1714 * (xyz/index) regardless of texture dimensionality,
1715 * which means it's necessary to zero the unused
1716 * components to keep everything happy */
1718 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1719 unsigned old_index
= index
;
1721 index
= make_compiler_temp(ctx
);
1723 /* mov index, old_index */
1724 midgard_instruction mov
= v_mov(old_index
, index
);
1726 emit_mir_instruction(ctx
, mov
);
1728 /* mov index.zw, #0 */
1729 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), index
);
1730 mov
.has_constants
= true;
1731 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1732 emit_mir_instruction(ctx
, mov
);
1735 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1736 /* texelFetch is undefined on samplerCube */
1737 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1739 /* For cubemaps, we use a special ld/st op to
1740 * select the face and copy the xy into the
1741 * texture register */
1743 unsigned temp
= make_compiler_temp(ctx
);
1744 midgard_instruction ld
= m_ld_cubemap_coords(temp
, 0);
1746 ld
.mask
= 0x3; /* xy */
1747 ld
.load_store
.arg_1
= 0x20;
1748 ld
.swizzle
[1][3] = COMPONENT_X
;
1749 emit_mir_instruction(ctx
, ld
);
1753 ins
.swizzle
[1][2] = COMPONENT_X
;
1754 ins
.swizzle
[1][3] = COMPONENT_X
;
1759 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1760 /* Array component in w but NIR wants it in z */
1761 if (nr_components
== 3) {
1762 ins
.swizzle
[1][2] = COMPONENT_Z
;
1763 ins
.swizzle
[1][3] = COMPONENT_Z
;
1764 } else if (nr_components
== 2) {
1765 ins
.swizzle
[1][2] = COMPONENT_X
;
1766 ins
.swizzle
[1][3] = COMPONENT_X
;
1768 unreachable("Invalid texture 2D components");
1774 case nir_tex_src_bias
:
1775 case nir_tex_src_lod
: {
1776 /* Try as a constant if we can */
1778 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1779 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1782 ins
.texture
.lod_register
= true;
1784 emit_explicit_constant(ctx
, index
, index
);
1790 unreachable("Unknown texture source type\n");
1794 emit_mir_instruction(ctx
, ins
);
1796 /* Used for .cont and .last hinting */
1797 ctx
->texture_op_count
++;
1801 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1803 /* Fixup op, since only textureLod is permitted in VS on later Midgard
1804 * but NIR can give generic tex in some cases (which confuses the
1805 * hardware). Interestingly, early Midgard lines up with NIR */
1807 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1809 if (is_vertex
&& instr
->op
== nir_texop_tex
&& ctx
->gpu_id
>= 0x750)
1810 instr
->op
= nir_texop_txl
;
1812 switch (instr
->op
) {
1815 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1818 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1821 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1824 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1827 unreachable("Unhanlded texture op");
1832 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1834 switch (instr
->type
) {
1835 case nir_jump_break
: {
1836 /* Emit a branch out of the loop */
1837 struct midgard_instruction br
= v_branch(false, false);
1838 br
.branch
.target_type
= TARGET_BREAK
;
1839 br
.branch
.target_break
= ctx
->current_loop_depth
;
1840 emit_mir_instruction(ctx
, br
);
1845 DBG("Unknown jump type %d\n", instr
->type
);
1851 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1853 switch (instr
->type
) {
1854 case nir_instr_type_load_const
:
1855 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1858 case nir_instr_type_intrinsic
:
1859 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1862 case nir_instr_type_alu
:
1863 emit_alu(ctx
, nir_instr_as_alu(instr
));
1866 case nir_instr_type_tex
:
1867 emit_tex(ctx
, nir_instr_as_tex(instr
));
1870 case nir_instr_type_jump
:
1871 emit_jump(ctx
, nir_instr_as_jump(instr
));
1874 case nir_instr_type_ssa_undef
:
1879 DBG("Unhandled instruction type\n");
1885 /* ALU instructions can inline or embed constants, which decreases register
1886 * pressure and saves space. */
1888 #define CONDITIONAL_ATTACH(idx) { \
1889 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1892 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1893 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1898 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1900 mir_foreach_instr_in_block(block
, alu
) {
1901 /* Other instructions cannot inline constants */
1902 if (alu
->type
!= TAG_ALU_4
) continue;
1903 if (alu
->compact_branch
) continue;
1905 /* If there is already a constant here, we can do nothing */
1906 if (alu
->has_constants
) continue;
1908 CONDITIONAL_ATTACH(0);
1910 if (!alu
->has_constants
) {
1911 CONDITIONAL_ATTACH(1)
1912 } else if (!alu
->inline_constant
) {
1913 /* Corner case: _two_ vec4 constants, for instance with a
1914 * csel. For this case, we can only use a constant
1915 * register for one, we'll have to emit a move for the
1916 * other. Note, if both arguments are constants, then
1917 * necessarily neither argument depends on the value of
1918 * any particular register. As the destination register
1919 * will be wiped, that means we can spill the constant
1920 * to the destination register.
1923 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
1924 unsigned scratch
= alu
->dest
;
1927 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
1928 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
1930 /* Set the source */
1931 alu
->src
[1] = scratch
;
1933 /* Inject us -before- the last instruction which set r31 */
1934 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
1940 /* Being a little silly with the names, but returns the op that is the bitwise
1941 * inverse of the op with the argument switched. I.e. (f and g are
1944 * f(a, b) = ~g(b, a)
1946 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1948 * f(a, b) = ~g(b, a)
1949 * ~f(a, b) = g(b, a)
1950 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1953 * Thus we define this function in pairs.
1956 static inline midgard_alu_op
1957 mir_contrapositive(midgard_alu_op op
)
1960 case midgard_alu_op_flt
:
1961 return midgard_alu_op_fle
;
1962 case midgard_alu_op_fle
:
1963 return midgard_alu_op_flt
;
1965 case midgard_alu_op_ilt
:
1966 return midgard_alu_op_ile
;
1967 case midgard_alu_op_ile
:
1968 return midgard_alu_op_ilt
;
1971 unreachable("No known contrapositive");
1975 /* Midgard supports two types of constants, embedded constants (128-bit) and
1976 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1977 * constants can be demoted to inline constants, for space savings and
1978 * sometimes a performance boost */
1981 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
1983 mir_foreach_instr_in_block(block
, ins
) {
1984 if (!ins
->has_constants
) continue;
1985 if (ins
->has_inline_constant
) continue;
1987 /* Blend constants must not be inlined by definition */
1988 if (ins
->has_blend_constant
) continue;
1990 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1991 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1992 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1994 if (!(is_16
|| is_32
))
1997 /* src1 cannot be an inline constant due to encoding
1998 * restrictions. So, if possible we try to flip the arguments
2001 int op
= ins
->alu
.op
;
2003 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2004 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2007 /* Conditionals can be inverted */
2008 case midgard_alu_op_flt
:
2009 case midgard_alu_op_ilt
:
2010 case midgard_alu_op_fle
:
2011 case midgard_alu_op_ile
:
2012 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2017 case midgard_alu_op_fcsel
:
2018 case midgard_alu_op_icsel
:
2019 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2028 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2029 /* Extract the source information */
2031 midgard_vector_alu_src
*src
;
2032 int q
= ins
->alu
.src2
;
2033 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2036 /* Component is from the swizzle. Take a nonzero component */
2038 unsigned first_comp
= ffs(ins
->mask
) - 1;
2039 unsigned component
= ins
->swizzle
[1][first_comp
];
2041 /* Scale constant appropriately, if we can legally */
2042 uint16_t scaled_constant
= 0;
2044 if (midgard_is_integer_op(op
) || is_16
) {
2045 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2046 scaled_constant
= (uint16_t) iconstants
[component
];
2048 /* Constant overflow after resize */
2049 if (scaled_constant
!= iconstants
[component
])
2052 float *f
= (float *) ins
->constants
;
2053 float original
= f
[component
];
2054 scaled_constant
= _mesa_float_to_half(original
);
2056 /* Check for loss of precision. If this is
2057 * mediump, we don't care, but for a highp
2058 * shader, we need to pay attention. NIR
2059 * doesn't yet tell us which mode we're in!
2060 * Practically this prevents most constants
2061 * from being inlined, sadly. */
2063 float fp32
= _mesa_half_to_float(scaled_constant
);
2065 if (fp32
!= original
)
2069 /* We don't know how to handle these with a constant */
2071 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2072 DBG("Bailing inline constant...\n");
2076 /* Make sure that the constant is not itself a vector
2077 * by checking if all accessed values are the same. */
2079 uint32_t *cons
= ins
->constants
;
2080 uint32_t value
= cons
[component
];
2082 bool is_vector
= false;
2083 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2085 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2086 /* We only care if this component is actually used */
2087 if (!(mask
& (1 << c
)))
2090 uint32_t test
= cons
[ins
->swizzle
[1][c
]];
2092 if (test
!= value
) {
2101 /* Get rid of the embedded constant */
2102 ins
->has_constants
= false;
2104 ins
->has_inline_constant
= true;
2105 ins
->inline_constant
= scaled_constant
;
2110 /* Dead code elimination for branches at the end of a block - only one branch
2111 * per block is legal semantically */
2114 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2116 bool branched
= false;
2118 mir_foreach_instr_in_block_safe(block
, ins
) {
2119 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2122 mir_remove_instruction(ins
);
2128 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2129 * the move can be propagated away entirely */
2132 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2135 if (comp
== midgard_outmod_none
)
2138 if (*outmod
== midgard_outmod_none
) {
2143 /* TODO: Compose rules */
2148 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2150 bool progress
= false;
2152 mir_foreach_instr_in_block_safe(block
, ins
) {
2153 if (ins
->type
!= TAG_ALU_4
) continue;
2154 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2155 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2157 /* TODO: Registers? */
2158 unsigned src
= ins
->src
[1];
2159 if (src
& IS_REG
) continue;
2161 /* There might be a source modifier, too */
2162 if (mir_nontrivial_source2_mod(ins
)) continue;
2164 /* Backpropagate the modifier */
2165 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2166 if (v
->type
!= TAG_ALU_4
) continue;
2167 if (v
->dest
!= src
) continue;
2169 /* Can we even take a float outmod? */
2170 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2172 midgard_outmod_float temp
= v
->alu
.outmod
;
2173 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2175 /* Throw in the towel.. */
2176 if (!progress
) break;
2178 /* Otherwise, transfer the modifier */
2179 v
->alu
.outmod
= temp
;
2180 ins
->alu
.outmod
= midgard_outmod_none
;
2190 emit_fragment_epilogue(compiler_context
*ctx
)
2192 /* Just emit the last chunk with the branch */
2193 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, ~0, midgard_condition_always
);
2196 static midgard_block
*
2197 emit_block(compiler_context
*ctx
, nir_block
*block
)
2199 midgard_block
*this_block
= ctx
->after_block
;
2200 ctx
->after_block
= NULL
;
2203 this_block
= create_empty_block(ctx
);
2205 list_addtail(&this_block
->link
, &ctx
->blocks
);
2207 this_block
->is_scheduled
= false;
2210 /* Set up current block */
2211 list_inithead(&this_block
->instructions
);
2212 ctx
->current_block
= this_block
;
2214 nir_foreach_instr(instr
, block
) {
2215 emit_instr(ctx
, instr
);
2216 ++ctx
->instruction_count
;
2222 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2225 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2227 midgard_block
*before_block
= ctx
->current_block
;
2229 /* Speculatively emit the branch, but we can't fill it in until later */
2230 EMIT(branch
, true, true);
2231 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2232 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2234 /* Emit the two subblocks. */
2235 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2236 midgard_block
*end_then_block
= ctx
->current_block
;
2238 /* Emit a jump from the end of the then block to the end of the else */
2239 EMIT(branch
, false, false);
2240 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2242 /* Emit second block, and check if it's empty */
2244 int else_idx
= ctx
->block_count
;
2245 int count_in
= ctx
->instruction_count
;
2246 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2247 midgard_block
*end_else_block
= ctx
->current_block
;
2248 int after_else_idx
= ctx
->block_count
;
2250 /* Now that we have the subblocks emitted, fix up the branches */
2255 if (ctx
->instruction_count
== count_in
) {
2256 /* The else block is empty, so don't emit an exit jump */
2257 mir_remove_instruction(then_exit
);
2258 then_branch
->branch
.target_block
= after_else_idx
;
2260 then_branch
->branch
.target_block
= else_idx
;
2261 then_exit
->branch
.target_block
= after_else_idx
;
2264 /* Wire up the successors */
2266 ctx
->after_block
= create_empty_block(ctx
);
2268 midgard_block_add_successor(before_block
, then_block
);
2269 midgard_block_add_successor(before_block
, else_block
);
2271 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2272 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2276 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2278 /* Remember where we are */
2279 midgard_block
*start_block
= ctx
->current_block
;
2281 /* Allocate a loop number, growing the current inner loop depth */
2282 int loop_idx
= ++ctx
->current_loop_depth
;
2284 /* Get index from before the body so we can loop back later */
2285 int start_idx
= ctx
->block_count
;
2287 /* Emit the body itself */
2288 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2290 /* Branch back to loop back */
2291 struct midgard_instruction br_back
= v_branch(false, false);
2292 br_back
.branch
.target_block
= start_idx
;
2293 emit_mir_instruction(ctx
, br_back
);
2295 /* Mark down that branch in the graph. */
2296 midgard_block_add_successor(start_block
, loop_block
);
2297 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2299 /* Find the index of the block about to follow us (note: we don't add
2300 * one; blocks are 0-indexed so we get a fencepost problem) */
2301 int break_block_idx
= ctx
->block_count
;
2303 /* Fix up the break statements we emitted to point to the right place,
2304 * now that we can allocate a block number for them */
2305 ctx
->after_block
= create_empty_block(ctx
);
2307 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2308 mir_foreach_instr_in_block(block
, ins
) {
2309 if (ins
->type
!= TAG_ALU_4
) continue;
2310 if (!ins
->compact_branch
) continue;
2311 if (ins
->prepacked_branch
) continue;
2313 /* We found a branch -- check the type to see if we need to do anything */
2314 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2316 /* It's a break! Check if it's our break */
2317 if (ins
->branch
.target_break
!= loop_idx
) continue;
2319 /* Okay, cool, we're breaking out of this loop.
2320 * Rewrite from a break to a goto */
2322 ins
->branch
.target_type
= TARGET_GOTO
;
2323 ins
->branch
.target_block
= break_block_idx
;
2325 midgard_block_add_successor(block
, ctx
->after_block
);
2329 /* Now that we've finished emitting the loop, free up the depth again
2330 * so we play nice with recursion amid nested loops */
2331 --ctx
->current_loop_depth
;
2333 /* Dump loop stats */
2337 static midgard_block
*
2338 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2340 midgard_block
*start_block
= NULL
;
2342 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2343 switch (node
->type
) {
2344 case nir_cf_node_block
: {
2345 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2348 start_block
= block
;
2353 case nir_cf_node_if
:
2354 emit_if(ctx
, nir_cf_node_as_if(node
));
2357 case nir_cf_node_loop
:
2358 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2361 case nir_cf_node_function
:
2370 /* Due to lookahead, we need to report the first tag executed in the command
2371 * stream and in branch targets. An initial block might be empty, so iterate
2372 * until we find one that 'works' */
2375 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2377 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2379 unsigned first_tag
= 0;
2381 mir_foreach_block_from(ctx
, initial_block
, v
) {
2382 if (v
->quadword_count
) {
2383 midgard_bundle
*initial_bundle
=
2384 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2386 first_tag
= initial_bundle
->tag
;
2395 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
, unsigned gpu_id
)
2397 struct util_dynarray
*compiled
= &program
->compiled
;
2399 midgard_debug
= debug_get_option_midgard_debug();
2401 /* TODO: Bound against what? */
2402 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2405 ctx
->stage
= nir
->info
.stage
;
2406 ctx
->is_blend
= is_blend
;
2407 ctx
->alpha_ref
= program
->alpha_ref
;
2408 ctx
->gpu_id
= gpu_id
;
2410 /* Start off with a safe cutoff, allowing usage of all 16 work
2411 * registers. Later, we'll promote uniform reads to uniform registers
2412 * if we determine it is beneficial to do so */
2413 ctx
->uniform_cutoff
= 8;
2415 /* Initialize at a global (not block) level hash tables */
2417 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2418 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2419 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2421 /* Record the varying mapping for the command stream's bookkeeping */
2423 struct exec_list
*varyings
=
2424 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2426 unsigned max_varying
= 0;
2427 nir_foreach_variable(var
, varyings
) {
2428 unsigned loc
= var
->data
.driver_location
;
2429 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2431 for (int c
= 0; c
< sz
; ++c
) {
2432 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2433 max_varying
= MAX2(max_varying
, loc
+ c
);
2437 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2438 * (so we don't accidentally duplicate the epilogue since mesa/st has
2439 * messed with our I/O quite a bit already) */
2441 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2443 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2444 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2445 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2448 NIR_PASS_V(nir
, nir_lower_var_copies
);
2449 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2450 NIR_PASS_V(nir
, nir_split_var_copies
);
2451 NIR_PASS_V(nir
, nir_lower_var_copies
);
2452 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2453 NIR_PASS_V(nir
, nir_lower_var_copies
);
2454 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2456 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2458 /* Optimisation passes */
2462 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2463 nir_print_shader(nir
, stdout
);
2466 /* Assign sysvals and counts, now that we're sure
2467 * (post-optimisation) */
2469 midgard_nir_assign_sysvals(ctx
, nir
);
2471 program
->uniform_count
= nir
->num_uniforms
;
2472 program
->sysval_count
= ctx
->sysval_count
;
2473 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2475 nir_foreach_function(func
, nir
) {
2479 list_inithead(&ctx
->blocks
);
2480 ctx
->block_count
= 0;
2483 emit_cf_list(ctx
, &func
->impl
->body
);
2485 /* Emit empty exit block with successor */
2487 struct midgard_block
*semi_end
= ctx
->current_block
;
2489 struct midgard_block
*end
=
2490 emit_block(ctx
, func
->impl
->end_block
);
2492 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2493 emit_fragment_epilogue(ctx
);
2495 midgard_block_add_successor(semi_end
, end
);
2497 break; /* TODO: Multi-function shaders */
2500 util_dynarray_init(compiled
, NULL
);
2502 /* Per-block lowering before opts */
2504 mir_foreach_block(ctx
, block
) {
2505 inline_alu_constants(ctx
, block
);
2506 midgard_opt_promote_fmov(ctx
, block
);
2507 embedded_to_inline_constant(ctx
, block
);
2509 /* MIR-level optimizations */
2511 bool progress
= false;
2516 mir_foreach_block(ctx
, block
) {
2517 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2518 progress
|= midgard_opt_copy_prop(ctx
, block
);
2519 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2520 progress
|= midgard_opt_combine_projection(ctx
, block
);
2521 progress
|= midgard_opt_varying_projection(ctx
, block
);
2522 progress
|= midgard_opt_not_propagate(ctx
, block
);
2523 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2524 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2525 progress
|= midgard_opt_csel_invert(ctx
, block
);
2529 mir_foreach_block(ctx
, block
) {
2530 midgard_lower_invert(ctx
, block
);
2531 midgard_lower_derivatives(ctx
, block
);
2534 /* Nested control-flow can result in dead branches at the end of the
2535 * block. This messes with our analysis and is just dead code, so cull
2537 mir_foreach_block(ctx
, block
) {
2538 midgard_opt_cull_dead_branch(ctx
, block
);
2541 /* Ensure we were lowered */
2542 mir_foreach_instr_global(ctx
, ins
) {
2543 assert(!ins
->invert
);
2547 schedule_program(ctx
);
2549 /* Now that all the bundles are scheduled and we can calculate block
2550 * sizes, emit actual branch instructions rather than placeholders */
2552 int br_block_idx
= 0;
2554 mir_foreach_block(ctx
, block
) {
2555 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2556 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2557 midgard_instruction
*ins
= bundle
->instructions
[c
];
2559 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2561 if (ins
->prepacked_branch
) continue;
2563 /* Parse some basic branch info */
2564 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2565 bool is_conditional
= ins
->branch
.conditional
;
2566 bool is_inverted
= ins
->branch
.invert_conditional
;
2567 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2569 /* Determine the block we're jumping to */
2570 int target_number
= ins
->branch
.target_block
;
2572 /* Report the destination tag */
2573 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2575 /* Count up the number of quadwords we're
2576 * jumping over = number of quadwords until
2577 * (br_block_idx, target_number) */
2579 int quadword_offset
= 0;
2583 } else if (target_number
> br_block_idx
) {
2586 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2587 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2590 quadword_offset
+= blk
->quadword_count
;
2593 /* Jump backwards */
2595 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2596 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2599 quadword_offset
-= blk
->quadword_count
;
2603 /* Unconditional extended branches (far jumps)
2604 * have issues, so we always use a conditional
2605 * branch, setting the condition to always for
2606 * unconditional. For compact unconditional
2607 * branches, cond isn't used so it doesn't
2608 * matter what we pick. */
2610 midgard_condition cond
=
2611 !is_conditional
? midgard_condition_always
:
2612 is_inverted
? midgard_condition_false
:
2613 midgard_condition_true
;
2615 midgard_jmp_writeout_op op
=
2616 is_discard
? midgard_jmp_writeout_op_discard
:
2617 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2618 midgard_jmp_writeout_op_branch_cond
;
2621 midgard_branch_extended branch
=
2622 midgard_create_branch_extended(
2627 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2628 } else if (is_conditional
|| is_discard
) {
2629 midgard_branch_cond branch
= {
2631 .dest_tag
= dest_tag
,
2632 .offset
= quadword_offset
,
2636 assert(branch
.offset
== quadword_offset
);
2638 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2640 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2642 midgard_branch_uncond branch
= {
2644 .dest_tag
= dest_tag
,
2645 .offset
= quadword_offset
,
2649 assert(branch
.offset
== quadword_offset
);
2651 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2659 /* Emit flat binary from the instruction arrays. Iterate each block in
2660 * sequence. Save instruction boundaries such that lookahead tags can
2661 * be assigned easily */
2663 /* Cache _all_ bundles in source order for lookahead across failed branches */
2665 int bundle_count
= 0;
2666 mir_foreach_block(ctx
, block
) {
2667 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2669 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2671 mir_foreach_block(ctx
, block
) {
2672 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2673 source_order_bundles
[bundle_idx
++] = bundle
;
2677 int current_bundle
= 0;
2679 /* Midgard prefetches instruction types, so during emission we
2680 * need to lookahead. Unless this is the last instruction, in
2681 * which we return 1. Or if this is the second to last and the
2682 * last is an ALU, then it's also 1... */
2684 mir_foreach_block(ctx
, block
) {
2685 mir_foreach_bundle_in_block(block
, bundle
) {
2688 if (current_bundle
+ 1 < bundle_count
) {
2689 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2691 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2698 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2702 /* TODO: Free deeper */
2703 //util_dynarray_fini(&block->instructions);
2706 free(source_order_bundles
);
2708 /* Report the very first tag executed */
2709 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2711 /* Deal with off-by-one related to the fencepost problem */
2712 program
->work_register_count
= ctx
->work_registers
+ 1;
2713 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2715 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2716 program
->tls_size
= ctx
->tls_size
;
2718 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2719 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2721 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2722 unsigned nr_bundles
= 0, nr_ins
= 0;
2724 /* Count instructions and bundles */
2726 mir_foreach_block(ctx
, block
) {
2727 nr_bundles
+= util_dynarray_num_elements(
2728 &block
->bundles
, midgard_bundle
);
2730 mir_foreach_bundle_in_block(block
, bun
)
2731 nr_ins
+= bun
->instruction_count
;
2734 /* Calculate thread count. There are certain cutoffs by
2735 * register count for thread count */
2737 unsigned nr_registers
= program
->work_register_count
;
2739 unsigned nr_threads
=
2740 (nr_registers
<= 4) ? 4 :
2741 (nr_registers
<= 8) ? 2 :
2746 fprintf(stderr
, "shader%d - %s shader: "
2747 "%u inst, %u bundles, %u quadwords, "
2748 "%u registers, %u threads, %u loops, "
2749 "%u:%u spills:fills\n",
2751 gl_shader_stage_name(ctx
->stage
),
2752 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2753 nr_registers
, nr_threads
,
2755 ctx
->spills
, ctx
->fills
);