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pan/mdg: Drop nir_lower_to_source_mods
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 if (broadcast_count && src) {
143 uint8_t last_component = src->swizzle[broadcast_count - 1];
144
145 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
146 src->swizzle[c] = last_component;
147 }
148 }
149
150 midgard_vector_alu_src alu_src = {
151 .rep_low = 0,
152 .rep_high = 0,
153 .half = half
154 };
155
156 if (is_int) {
157 alu_src.mod = midgard_int_normal;
158
159 /* Sign/zero-extend if needed */
160
161 if (half) {
162 alu_src.mod = sext ?
163 midgard_int_sign_extend
164 : midgard_int_zero_extend;
165 }
166
167 /* These should have been lowered away */
168 if (src)
169 assert(!(src->abs || src->negate));
170 } else {
171 if (src)
172 alu_src.mod = (src->abs << 0) | (src->negate << 1);
173 }
174
175 return alu_src;
176 }
177
178 M_LOAD(ld_attr_32, nir_type_uint32);
179 M_LOAD(ld_vary_32, nir_type_uint32);
180 M_LOAD(ld_ubo_int4, nir_type_uint32);
181 M_LOAD(ld_int4, nir_type_uint32);
182 M_STORE(st_int4, nir_type_uint32);
183 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
184 M_STORE(st_vary_32, nir_type_uint32);
185 M_LOAD(ld_cubemap_coords, nir_type_uint32);
186 M_LOAD(ld_compute_id, nir_type_uint32);
187
188 static midgard_instruction
189 v_branch(bool conditional, bool invert)
190 {
191 midgard_instruction ins = {
192 .type = TAG_ALU_4,
193 .unit = ALU_ENAB_BRANCH,
194 .compact_branch = true,
195 .branch = {
196 .conditional = conditional,
197 .invert_conditional = invert
198 },
199 .dest = ~0,
200 .src = { ~0, ~0, ~0, ~0 },
201 };
202
203 return ins;
204 }
205
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond,
208 midgard_jmp_writeout_op op,
209 unsigned dest_tag,
210 signed quadword_offset)
211 {
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
215 * times. */
216
217 uint16_t duplicated_cond =
218 (cond << 14) |
219 (cond << 12) |
220 (cond << 10) |
221 (cond << 8) |
222 (cond << 6) |
223 (cond << 4) |
224 (cond << 2) |
225 (cond << 0);
226
227 midgard_branch_extended branch = {
228 .op = op,
229 .dest_tag = dest_tag,
230 .offset = quadword_offset,
231 .cond = duplicated_cond
232 };
233
234 return branch;
235 }
236
237 static void
238 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
239 {
240 ins->has_constants = true;
241 memcpy(&ins->constants, constants, 16);
242 }
243
244 static int
245 glsl_type_size(const struct glsl_type *type, bool bindless)
246 {
247 return glsl_count_attribute_slots(type, false);
248 }
249
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
251 static void
252 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
253 {
254 if (alu->op != nir_op_fdot2)
255 return;
256
257 b->cursor = nir_before_instr(&alu->instr);
258
259 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
260 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
261
262 nir_ssa_def *product = nir_fmul(b, src0, src1);
263
264 nir_ssa_def *sum = nir_fadd(b,
265 nir_channel(b, product, 0),
266 nir_channel(b, product, 1));
267
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
270 }
271
272 static bool
273 midgard_nir_lower_fdot2(nir_shader *shader)
274 {
275 bool progress = false;
276
277 nir_foreach_function(function, shader) {
278 if (!function->impl) continue;
279
280 nir_builder _b;
281 nir_builder *b = &_b;
282 nir_builder_init(b, function->impl);
283
284 nir_foreach_block(block, function->impl) {
285 nir_foreach_instr_safe(instr, block) {
286 if (instr->type != nir_instr_type_alu) continue;
287
288 nir_alu_instr *alu = nir_instr_as_alu(instr);
289 midgard_nir_lower_fdot2_body(b, alu);
290
291 progress |= true;
292 }
293 }
294
295 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
296
297 }
298
299 return progress;
300 }
301
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
305 * one.
306 */
307 static bool
308 midgard_nir_lower_zs_store(nir_shader *nir)
309 {
310 if (nir->info.stage != MESA_SHADER_FRAGMENT)
311 return false;
312
313 nir_variable *z_var = NULL, *s_var = NULL;
314
315 nir_foreach_variable(var, &nir->outputs) {
316 if (var->data.location == FRAG_RESULT_DEPTH)
317 z_var = var;
318 else if (var->data.location == FRAG_RESULT_STENCIL)
319 s_var = var;
320 }
321
322 if (!z_var && !s_var)
323 return false;
324
325 bool progress = false;
326
327 nir_foreach_function(function, nir) {
328 if (!function->impl) continue;
329
330 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
331
332 nir_foreach_block(block, function->impl) {
333 nir_foreach_instr_safe(instr, block) {
334 if (instr->type != nir_instr_type_intrinsic)
335 continue;
336
337 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
338 if (intr->intrinsic != nir_intrinsic_store_output)
339 continue;
340
341 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
342 assert(!z_store);
343 z_store = intr;
344 last_store = intr;
345 }
346
347 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
348 assert(!s_store);
349 s_store = intr;
350 last_store = intr;
351 }
352 }
353 }
354
355 if (!z_store && !s_store) continue;
356
357 nir_builder b;
358 nir_builder_init(&b, function->impl);
359
360 b.cursor = nir_before_instr(&last_store->instr);
361
362 nir_ssa_def *zs_store_src;
363
364 if (z_store && s_store) {
365 nir_ssa_def *srcs[2] = {
366 nir_ssa_for_src(&b, z_store->src[0], 1),
367 nir_ssa_for_src(&b, s_store->src[0], 1),
368 };
369
370 zs_store_src = nir_vec(&b, srcs, 2);
371 } else {
372 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
373 }
374
375 nir_intrinsic_instr *zs_store;
376
377 zs_store = nir_intrinsic_instr_create(b.shader,
378 nir_intrinsic_store_zs_output_pan);
379 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
380 zs_store->num_components = z_store && s_store ? 2 : 1;
381 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
382
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b, &zs_store->instr);
385
386 if (z_store)
387 nir_instr_remove(&z_store->instr);
388
389 if (s_store)
390 nir_instr_remove(&s_store->instr);
391
392 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
393 progress = true;
394 }
395
396 return progress;
397 }
398
399 /* Flushes undefined values to zero */
400
401 static void
402 optimise_nir(nir_shader *nir, unsigned quirks)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
412
413 nir_lower_tex_options lower_tex_options = {
414 .lower_txs_lod = true,
415 .lower_txp = ~0,
416 .lower_tex_without_implicit_lod =
417 (quirks & MIDGARD_EXPLICIT_LOD),
418
419 /* TODO: we have native gradient.. */
420 .lower_txd = true,
421 };
422
423 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
424
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
427
428 /* T720 is broken. */
429
430 if (quirks & MIDGARD_BROKEN_LOD)
431 NIR_PASS_V(nir, midgard_nir_lod_errata);
432
433 do {
434 progress = false;
435
436 NIR_PASS(progress, nir, nir_lower_var_copies);
437 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
438
439 NIR_PASS(progress, nir, nir_copy_prop);
440 NIR_PASS(progress, nir, nir_opt_remove_phis);
441 NIR_PASS(progress, nir, nir_opt_dce);
442 NIR_PASS(progress, nir, nir_opt_dead_cf);
443 NIR_PASS(progress, nir, nir_opt_cse);
444 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447
448 if (lower_flrp != 0) {
449 bool lower_flrp_progress = false;
450 NIR_PASS(lower_flrp_progress,
451 nir,
452 nir_lower_flrp,
453 lower_flrp,
454 false /* always_precise */,
455 nir->options->lower_ffma);
456 if (lower_flrp_progress) {
457 NIR_PASS(progress, nir,
458 nir_opt_constant_folding);
459 progress = true;
460 }
461
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
464 */
465 lower_flrp = 0;
466 }
467
468 NIR_PASS(progress, nir, nir_opt_undef);
469 NIR_PASS(progress, nir, nir_undef_to_zero);
470
471 NIR_PASS(progress, nir, nir_opt_loop_unroll,
472 nir_var_shader_in |
473 nir_var_shader_out |
474 nir_var_function_temp);
475
476 NIR_PASS(progress, nir, nir_opt_vectorize);
477 } while (progress);
478
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress, nir, midgard_nir_scale_trig);
481
482 do {
483 progress = false;
484
485 NIR_PASS(progress, nir, nir_opt_dce);
486 NIR_PASS(progress, nir, nir_opt_algebraic);
487 NIR_PASS(progress, nir, nir_opt_constant_folding);
488 NIR_PASS(progress, nir, nir_copy_prop);
489 } while (progress);
490
491 NIR_PASS(progress, nir, nir_opt_algebraic_late);
492 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
493
494 /* We implement booleans as 32-bit 0/~0 */
495 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
496
497 /* Now that booleans are lowered, we can run out late opts */
498 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
499
500 NIR_PASS(progress, nir, nir_copy_prop);
501 NIR_PASS(progress, nir, nir_opt_dce);
502
503 /* Take us out of SSA */
504 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
505 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
506
507 /* We are a vector architecture; write combine where possible */
508 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
509 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
510
511 NIR_PASS(progress, nir, nir_opt_dce);
512 }
513
514 /* Do not actually emit a load; instead, cache the constant for inlining */
515
516 static void
517 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
518 {
519 nir_ssa_def def = instr->def;
520
521 midgard_constants *consts = rzalloc(NULL, midgard_constants);
522
523 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
524
525 #define RAW_CONST_COPY(bits) \
526 nir_const_value_to_array(consts->u##bits, instr->value, \
527 instr->def.num_components, u##bits)
528
529 switch (instr->def.bit_size) {
530 case 64:
531 RAW_CONST_COPY(64);
532 break;
533 case 32:
534 RAW_CONST_COPY(32);
535 break;
536 case 16:
537 RAW_CONST_COPY(16);
538 break;
539 case 8:
540 RAW_CONST_COPY(8);
541 break;
542 default:
543 unreachable("Invalid bit_size for load_const instruction\n");
544 }
545
546 /* Shifted for SSA, +1 for off-by-one */
547 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
548 }
549
550 /* Normally constants are embedded implicitly, but for I/O and such we have to
551 * explicitly emit a move with the constant source */
552
553 static void
554 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
555 {
556 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
557
558 if (constant_value) {
559 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
560 attach_constants(ctx, &ins, constant_value, node + 1);
561 emit_mir_instruction(ctx, ins);
562 }
563 }
564
565 static bool
566 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
567 {
568 unsigned comp = src->swizzle[0];
569
570 for (unsigned c = 1; c < nr_components; ++c) {
571 if (src->swizzle[c] != comp)
572 return true;
573 }
574
575 return false;
576 }
577
578 #define ALU_CASE(nir, _op) \
579 case nir_op_##nir: \
580 op = midgard_alu_op_##_op; \
581 assert(src_bitsize == dst_bitsize); \
582 break;
583
584 #define ALU_CASE_BCAST(nir, _op, count) \
585 case nir_op_##nir: \
586 op = midgard_alu_op_##_op; \
587 broadcast_swizzle = count; \
588 assert(src_bitsize == dst_bitsize); \
589 break;
590 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
591 * special treatment override this anyway. */
592
593 static midgard_reg_mode
594 reg_mode_for_nir(nir_alu_instr *instr)
595 {
596 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
597
598 switch (src_bitsize) {
599 case 8:
600 return midgard_reg_mode_8;
601 case 16:
602 return midgard_reg_mode_16;
603 case 32:
604 return midgard_reg_mode_32;
605 case 64:
606 return midgard_reg_mode_64;
607 default:
608 unreachable("Invalid bit size");
609 }
610 }
611
612 static void
613 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
614 {
615 unsigned bits = nir_src_bit_size(instr->src[i].src);
616
617 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
618 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
619 }
620
621 static void
622 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
623 {
624 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
625 * is handled elsewhere */
626
627 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
628 midgard_emit_derivatives(ctx, instr);
629 return;
630 }
631
632 bool is_ssa = instr->dest.dest.is_ssa;
633
634 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
635 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
636 unsigned op = 0;
637
638 /* Number of components valid to check for the instruction (the rest
639 * will be forced to the last), or 0 to use as-is. Relevant as
640 * ball-type instructions have a channel count in NIR but are all vec4
641 * in Midgard */
642
643 unsigned broadcast_swizzle = 0;
644
645 /* What register mode should we operate in? */
646 midgard_reg_mode reg_mode =
647 reg_mode_for_nir(instr);
648
649 /* Do we need a destination override? Used for inline
650 * type conversion */
651
652 midgard_dest_override dest_override =
653 midgard_dest_override_none;
654
655 /* Should we use a smaller respective source and sign-extend? */
656
657 bool half_1 = false, sext_1 = false;
658 bool half_2 = false, sext_2 = false;
659
660 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
661 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
662
663 switch (instr->op) {
664 ALU_CASE(fadd, fadd);
665 ALU_CASE(fmul, fmul);
666 ALU_CASE(fmin, fmin);
667 ALU_CASE(fmax, fmax);
668 ALU_CASE(imin, imin);
669 ALU_CASE(imax, imax);
670 ALU_CASE(umin, umin);
671 ALU_CASE(umax, umax);
672 ALU_CASE(ffloor, ffloor);
673 ALU_CASE(fround_even, froundeven);
674 ALU_CASE(ftrunc, ftrunc);
675 ALU_CASE(fceil, fceil);
676 ALU_CASE(fdot3, fdot3);
677 ALU_CASE(fdot4, fdot4);
678 ALU_CASE(iadd, iadd);
679 ALU_CASE(isub, isub);
680 ALU_CASE(imul, imul);
681
682 /* Zero shoved as second-arg */
683 ALU_CASE(iabs, iabsdiff);
684
685 ALU_CASE(mov, imov);
686
687 ALU_CASE(feq32, feq);
688 ALU_CASE(fne32, fne);
689 ALU_CASE(flt32, flt);
690 ALU_CASE(ieq32, ieq);
691 ALU_CASE(ine32, ine);
692 ALU_CASE(ilt32, ilt);
693 ALU_CASE(ult32, ult);
694
695 /* We don't have a native b2f32 instruction. Instead, like many
696 * GPUs, we exploit booleans as 0/~0 for false/true, and
697 * correspondingly AND
698 * by 1.0 to do the type conversion. For the moment, prime us
699 * to emit:
700 *
701 * iand [whatever], #0
702 *
703 * At the end of emit_alu (as MIR), we'll fix-up the constant
704 */
705
706 ALU_CASE(b2f32, iand);
707 ALU_CASE(b2i32, iand);
708
709 /* Likewise, we don't have a dedicated f2b32 instruction, but
710 * we can do a "not equal to 0.0" test. */
711
712 ALU_CASE(f2b32, fne);
713 ALU_CASE(i2b32, ine);
714
715 ALU_CASE(frcp, frcp);
716 ALU_CASE(frsq, frsqrt);
717 ALU_CASE(fsqrt, fsqrt);
718 ALU_CASE(fexp2, fexp2);
719 ALU_CASE(flog2, flog2);
720
721 ALU_CASE(f2i64, f2i_rtz);
722 ALU_CASE(f2u64, f2u_rtz);
723 ALU_CASE(i2f64, i2f_rtz);
724 ALU_CASE(u2f64, u2f_rtz);
725
726 ALU_CASE(f2i32, f2i_rtz);
727 ALU_CASE(f2u32, f2u_rtz);
728 ALU_CASE(i2f32, i2f_rtz);
729 ALU_CASE(u2f32, u2f_rtz);
730
731 ALU_CASE(f2i16, f2i_rtz);
732 ALU_CASE(f2u16, f2u_rtz);
733 ALU_CASE(i2f16, i2f_rtz);
734 ALU_CASE(u2f16, u2f_rtz);
735
736 ALU_CASE(fsin, fsin);
737 ALU_CASE(fcos, fcos);
738
739 /* We'll set invert */
740 ALU_CASE(inot, imov);
741 ALU_CASE(iand, iand);
742 ALU_CASE(ior, ior);
743 ALU_CASE(ixor, ixor);
744 ALU_CASE(ishl, ishl);
745 ALU_CASE(ishr, iasr);
746 ALU_CASE(ushr, ilsr);
747
748 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
749 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
750 ALU_CASE(b32all_fequal4, fball_eq);
751
752 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
753 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
754 ALU_CASE(b32any_fnequal4, fbany_neq);
755
756 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
757 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
758 ALU_CASE(b32all_iequal4, iball_eq);
759
760 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
761 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
762 ALU_CASE(b32any_inequal4, ibany_neq);
763
764 /* Source mods will be shoved in later */
765 ALU_CASE(fabs, fmov);
766 ALU_CASE(fneg, fmov);
767 ALU_CASE(fsat, fmov);
768
769 /* For size conversion, we use a move. Ideally though we would squash
770 * these ops together; maybe that has to happen after in NIR as part of
771 * propagation...? An earlier algebraic pass ensured we step down by
772 * only / exactly one size. If stepping down, we use a dest override to
773 * reduce the size; if stepping up, we use a larger-sized move with a
774 * half source and a sign/zero-extension modifier */
775
776 case nir_op_i2i8:
777 case nir_op_i2i16:
778 case nir_op_i2i32:
779 case nir_op_i2i64:
780 /* If we end up upscale, we'll need a sign-extend on the
781 * operand (the second argument) */
782
783 sext_2 = true;
784 /* fallthrough */
785 case nir_op_u2u8:
786 case nir_op_u2u16:
787 case nir_op_u2u32:
788 case nir_op_u2u64:
789 case nir_op_f2f16:
790 case nir_op_f2f32:
791 case nir_op_f2f64: {
792 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
793 instr->op == nir_op_f2f64)
794 op = midgard_alu_op_fmov;
795 else
796 op = midgard_alu_op_imov;
797
798 if (dst_bitsize == (src_bitsize * 2)) {
799 /* Converting up */
800 half_2 = true;
801
802 /* Use a greater register mode */
803 reg_mode++;
804 } else if (src_bitsize == (dst_bitsize * 2)) {
805 /* Converting down */
806 dest_override = midgard_dest_override_lower;
807 }
808
809 break;
810 }
811
812 /* For greater-or-equal, we lower to less-or-equal and flip the
813 * arguments */
814
815 case nir_op_fge:
816 case nir_op_fge32:
817 case nir_op_ige32:
818 case nir_op_uge32: {
819 op =
820 instr->op == nir_op_fge ? midgard_alu_op_fle :
821 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
822 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
823 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
824 0;
825
826 /* Swap via temporary */
827 nir_alu_src temp = instr->src[1];
828 instr->src[1] = instr->src[0];
829 instr->src[0] = temp;
830
831 break;
832 }
833
834 case nir_op_b32csel: {
835 /* Midgard features both fcsel and icsel, depending on
836 * the type of the arguments/output. However, as long
837 * as we're careful we can _always_ use icsel and
838 * _never_ need fcsel, since the latter does additional
839 * floating-point-specific processing whereas the
840 * former just moves bits on the wire. It's not obvious
841 * why these are separate opcodes, save for the ability
842 * to do things like sat/pos/abs/neg for free */
843
844 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
845 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
846
847 /* The condition is the first argument; move the other
848 * arguments up one to be a binary instruction for
849 * Midgard with the condition last */
850
851 nir_alu_src temp = instr->src[2];
852
853 instr->src[2] = instr->src[0];
854 instr->src[0] = instr->src[1];
855 instr->src[1] = temp;
856
857 break;
858 }
859
860 default:
861 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
862 assert(0);
863 return;
864 }
865
866 /* Midgard can perform certain modifiers on output of an ALU op */
867 unsigned outmod;
868
869 if (midgard_is_integer_out_op(op)) {
870 outmod = midgard_outmod_int_wrap;
871 } else {
872 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
873 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
874 }
875
876
877 /* Fetch unit, quirks, etc information */
878 unsigned opcode_props = alu_opcode_props[op].props;
879 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
880
881 midgard_instruction ins = {
882 .type = TAG_ALU_4,
883 .dest = nir_dest_index(&instr->dest.dest),
884 .dest_type = nir_op_infos[instr->op].output_type
885 | nir_dest_bit_size(instr->dest.dest),
886 };
887
888 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
889 ins.src[i] = ~0;
890
891 if (quirk_flipped_r24) {
892 ins.src[0] = ~0;
893 mir_copy_src(&ins, instr, 0, 1);
894 } else {
895 for (unsigned i = 0; i < nr_inputs; ++i)
896 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
897 }
898
899 nir_alu_src *nirmods[3] = { NULL };
900
901 if (nr_inputs >= 2) {
902 nirmods[0] = &instr->src[0];
903 nirmods[1] = &instr->src[1];
904 } else if (nr_inputs == 1) {
905 nirmods[quirk_flipped_r24] = &instr->src[0];
906 } else {
907 assert(0);
908 }
909
910 if (nr_inputs == 3)
911 nirmods[2] = &instr->src[2];
912
913 /* These were lowered to a move, so apply the corresponding mod */
914
915 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
916 nir_alu_src *s = nirmods[quirk_flipped_r24];
917
918 if (instr->op == nir_op_fneg)
919 s->negate = !s->negate;
920
921 if (instr->op == nir_op_fabs)
922 s->abs = !s->abs;
923 }
924
925 bool is_int = midgard_is_integer_op(op);
926
927 ins.mask = mask_of(nr_components);
928
929 midgard_vector_alu alu = {
930 .op = op,
931 .reg_mode = reg_mode,
932 .dest_override = dest_override,
933 .outmod = outmod,
934
935 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
936 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
937 };
938
939 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
940
941 if (!is_ssa)
942 ins.mask &= instr->dest.write_mask;
943
944 for (unsigned m = 0; m < 3; ++m) {
945 if (!nirmods[m])
946 continue;
947
948 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
949 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
950
951 /* Replicate. TODO: remove when vec16 lands */
952 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
953 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
954 }
955
956 if (nr_inputs == 3) {
957 /* Conditions can't have mods */
958 assert(!nirmods[2]->abs);
959 assert(!nirmods[2]->negate);
960 }
961
962 ins.alu = alu;
963
964 /* Late fixup for emulated instructions */
965
966 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
967 /* Presently, our second argument is an inline #0 constant.
968 * Switch over to an embedded 1.0 constant (that can't fit
969 * inline, since we're 32-bit, not 16-bit like the inline
970 * constants) */
971
972 ins.has_inline_constant = false;
973 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
974 ins.src_types[1] = nir_type_float32;
975 ins.has_constants = true;
976
977 if (instr->op == nir_op_b2f32)
978 ins.constants.f32[0] = 1.0f;
979 else
980 ins.constants.i32[0] = 1;
981
982 for (unsigned c = 0; c < 16; ++c)
983 ins.swizzle[1][c] = 0;
984 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
985 /* Lots of instructions need a 0 plonked in */
986 ins.has_inline_constant = false;
987 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
988 ins.src_types[1] = nir_type_uint32;
989 ins.has_constants = true;
990 ins.constants.u32[0] = 0;
991
992 for (unsigned c = 0; c < 16; ++c)
993 ins.swizzle[1][c] = 0;
994 } else if (instr->op == nir_op_inot) {
995 ins.invert = true;
996 }
997
998 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
999 /* To avoid duplicating the lookup tables (probably), true LUT
1000 * instructions can only operate as if they were scalars. Lower
1001 * them here by changing the component. */
1002
1003 unsigned orig_mask = ins.mask;
1004
1005 for (int i = 0; i < nr_components; ++i) {
1006 /* Mask the associated component, dropping the
1007 * instruction if needed */
1008
1009 ins.mask = 1 << i;
1010 ins.mask &= orig_mask;
1011
1012 if (!ins.mask)
1013 continue;
1014
1015 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1016 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1017
1018 emit_mir_instruction(ctx, ins);
1019 }
1020 } else {
1021 emit_mir_instruction(ctx, ins);
1022 }
1023 }
1024
1025 #undef ALU_CASE
1026
1027 static void
1028 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1029 {
1030 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1031 unsigned nir_mask = 0;
1032 unsigned dsize = 0;
1033
1034 if (is_read) {
1035 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1036 dsize = nir_dest_bit_size(intr->dest);
1037 } else {
1038 nir_mask = nir_intrinsic_write_mask(intr);
1039 dsize = 32;
1040 }
1041
1042 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1043 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1044 mir_set_bytemask(ins, bytemask);
1045
1046 if (dsize == 64)
1047 ins->load_64 = true;
1048 }
1049
1050 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1051 * optimized) versions of UBO #0 */
1052
1053 static midgard_instruction *
1054 emit_ubo_read(
1055 compiler_context *ctx,
1056 nir_instr *instr,
1057 unsigned dest,
1058 unsigned offset,
1059 nir_src *indirect_offset,
1060 unsigned indirect_shift,
1061 unsigned index)
1062 {
1063 /* TODO: half-floats */
1064
1065 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1066 ins.constants.u32[0] = offset;
1067
1068 if (instr->type == nir_instr_type_intrinsic)
1069 mir_set_intr_mask(instr, &ins, true);
1070
1071 if (indirect_offset) {
1072 ins.src[2] = nir_src_index(ctx, indirect_offset);
1073 ins.src_types[2] = nir_type_uint32;
1074 ins.load_store.arg_2 = (indirect_shift << 5);
1075 } else {
1076 ins.load_store.arg_2 = 0x1E;
1077 }
1078
1079 ins.load_store.arg_1 = index;
1080
1081 return emit_mir_instruction(ctx, ins);
1082 }
1083
1084 /* Globals are like UBOs if you squint. And shared memory is like globals if
1085 * you squint even harder */
1086
1087 static void
1088 emit_global(
1089 compiler_context *ctx,
1090 nir_instr *instr,
1091 bool is_read,
1092 unsigned srcdest,
1093 nir_src *offset,
1094 bool is_shared)
1095 {
1096 /* TODO: types */
1097
1098 midgard_instruction ins;
1099
1100 if (is_read)
1101 ins = m_ld_int4(srcdest, 0);
1102 else
1103 ins = m_st_int4(srcdest, 0);
1104
1105 mir_set_offset(ctx, &ins, offset, is_shared);
1106 mir_set_intr_mask(instr, &ins, is_read);
1107
1108 emit_mir_instruction(ctx, ins);
1109 }
1110
1111 static void
1112 emit_varying_read(
1113 compiler_context *ctx,
1114 unsigned dest, unsigned offset,
1115 unsigned nr_comp, unsigned component,
1116 nir_src *indirect_offset, nir_alu_type type, bool flat)
1117 {
1118 /* XXX: Half-floats? */
1119 /* TODO: swizzle, mask */
1120
1121 midgard_instruction ins = m_ld_vary_32(dest, offset);
1122 ins.mask = mask_of(nr_comp);
1123
1124 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1125 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1126
1127 midgard_varying_parameter p = {
1128 .is_varying = 1,
1129 .interpolation = midgard_interp_default,
1130 .flat = flat,
1131 };
1132
1133 unsigned u;
1134 memcpy(&u, &p, sizeof(p));
1135 ins.load_store.varying_parameters = u;
1136
1137 if (indirect_offset) {
1138 ins.src[2] = nir_src_index(ctx, indirect_offset);
1139 ins.src_types[2] = nir_type_uint32;
1140 } else
1141 ins.load_store.arg_2 = 0x1E;
1142
1143 ins.load_store.arg_1 = 0x9E;
1144
1145 /* Use the type appropriate load */
1146 switch (type) {
1147 case nir_type_uint:
1148 case nir_type_bool:
1149 ins.load_store.op = midgard_op_ld_vary_32u;
1150 break;
1151 case nir_type_int:
1152 ins.load_store.op = midgard_op_ld_vary_32i;
1153 break;
1154 case nir_type_float:
1155 ins.load_store.op = midgard_op_ld_vary_32;
1156 break;
1157 default:
1158 unreachable("Attempted to load unknown type");
1159 break;
1160 }
1161
1162 emit_mir_instruction(ctx, ins);
1163 }
1164
1165 static void
1166 emit_attr_read(
1167 compiler_context *ctx,
1168 unsigned dest, unsigned offset,
1169 unsigned nr_comp, nir_alu_type t)
1170 {
1171 midgard_instruction ins = m_ld_attr_32(dest, offset);
1172 ins.load_store.arg_1 = 0x1E;
1173 ins.load_store.arg_2 = 0x1E;
1174 ins.mask = mask_of(nr_comp);
1175
1176 /* Use the type appropriate load */
1177 switch (t) {
1178 case nir_type_uint:
1179 case nir_type_bool:
1180 ins.load_store.op = midgard_op_ld_attr_32u;
1181 break;
1182 case nir_type_int:
1183 ins.load_store.op = midgard_op_ld_attr_32i;
1184 break;
1185 case nir_type_float:
1186 ins.load_store.op = midgard_op_ld_attr_32;
1187 break;
1188 default:
1189 unreachable("Attempted to load unknown type");
1190 break;
1191 }
1192
1193 emit_mir_instruction(ctx, ins);
1194 }
1195
1196 static void
1197 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1198 unsigned nr_components, unsigned offset)
1199 {
1200 nir_dest nir_dest;
1201
1202 /* Figure out which uniform this is */
1203 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1204 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1205
1206 unsigned dest = nir_dest_index(&nir_dest);
1207
1208 /* Sysvals are prefix uniforms */
1209 unsigned uniform = ((uintptr_t) val) - 1;
1210
1211 /* Emit the read itself -- this is never indirect */
1212 midgard_instruction *ins =
1213 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1214
1215 ins->mask = mask_of(nr_components);
1216 }
1217
1218 static unsigned
1219 compute_builtin_arg(nir_op op)
1220 {
1221 switch (op) {
1222 case nir_intrinsic_load_work_group_id:
1223 return 0x14;
1224 case nir_intrinsic_load_local_invocation_id:
1225 return 0x10;
1226 default:
1227 unreachable("Invalid compute paramater loaded");
1228 }
1229 }
1230
1231 static void
1232 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1233 {
1234 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1235
1236 midgard_instruction *br = ctx->writeout_branch[rt];
1237
1238 assert(!br);
1239
1240 emit_explicit_constant(ctx, src, src);
1241
1242 struct midgard_instruction ins =
1243 v_branch(false, false);
1244
1245 ins.writeout = true;
1246
1247 /* Add dependencies */
1248 ins.src[0] = src;
1249 ins.src_types[0] = nir_type_uint32;
1250 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1251 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1252
1253 /* Emit the branch */
1254 br = emit_mir_instruction(ctx, ins);
1255 schedule_barrier(ctx);
1256 ctx->writeout_branch[rt] = br;
1257
1258 /* Push our current location = current block count - 1 = where we'll
1259 * jump to. Maybe a bit too clever for my own good */
1260
1261 br->branch.target_block = ctx->block_count - 1;
1262 }
1263
1264 static void
1265 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1266 {
1267 unsigned reg = nir_dest_index(&instr->dest);
1268 midgard_instruction ins = m_ld_compute_id(reg, 0);
1269 ins.mask = mask_of(3);
1270 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1271 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1272 emit_mir_instruction(ctx, ins);
1273 }
1274
1275 static unsigned
1276 vertex_builtin_arg(nir_op op)
1277 {
1278 switch (op) {
1279 case nir_intrinsic_load_vertex_id:
1280 return PAN_VERTEX_ID;
1281 case nir_intrinsic_load_instance_id:
1282 return PAN_INSTANCE_ID;
1283 default:
1284 unreachable("Invalid vertex builtin");
1285 }
1286 }
1287
1288 static void
1289 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1290 {
1291 unsigned reg = nir_dest_index(&instr->dest);
1292 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1293 }
1294
1295 static void
1296 emit_control_barrier(compiler_context *ctx)
1297 {
1298 midgard_instruction ins = {
1299 .type = TAG_TEXTURE_4,
1300 .src = { ~0, ~0, ~0, ~0 },
1301 .texture = {
1302 .op = TEXTURE_OP_BARRIER,
1303
1304 /* TODO: optimize */
1305 .barrier_buffer = 1,
1306 .barrier_shared = 1
1307 }
1308 };
1309
1310 emit_mir_instruction(ctx, ins);
1311 }
1312
1313 static const nir_variable *
1314 search_var(struct exec_list *vars, unsigned driver_loc)
1315 {
1316 nir_foreach_variable(var, vars) {
1317 if (var->data.driver_location == driver_loc)
1318 return var;
1319 }
1320
1321 return NULL;
1322 }
1323
1324 static void
1325 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1326 {
1327 unsigned offset = 0, reg;
1328
1329 switch (instr->intrinsic) {
1330 case nir_intrinsic_discard_if:
1331 case nir_intrinsic_discard: {
1332 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1333 struct midgard_instruction discard = v_branch(conditional, false);
1334 discard.branch.target_type = TARGET_DISCARD;
1335
1336 if (conditional) {
1337 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1338 discard.src_types[0] = nir_type_uint32;
1339 }
1340
1341 emit_mir_instruction(ctx, discard);
1342 schedule_barrier(ctx);
1343
1344 break;
1345 }
1346
1347 case nir_intrinsic_load_uniform:
1348 case nir_intrinsic_load_ubo:
1349 case nir_intrinsic_load_global:
1350 case nir_intrinsic_load_shared:
1351 case nir_intrinsic_load_input:
1352 case nir_intrinsic_load_interpolated_input: {
1353 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1354 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1355 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1356 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1357 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1358 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1359
1360 /* Get the base type of the intrinsic */
1361 /* TODO: Infer type? Does it matter? */
1362 nir_alu_type t =
1363 (is_ubo || is_global || is_shared) ? nir_type_uint :
1364 (is_interp) ? nir_type_float :
1365 nir_intrinsic_type(instr);
1366
1367 t = nir_alu_type_get_base_type(t);
1368
1369 if (!(is_ubo || is_global)) {
1370 offset = nir_intrinsic_base(instr);
1371 }
1372
1373 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1374
1375 nir_src *src_offset = nir_get_io_offset_src(instr);
1376
1377 bool direct = nir_src_is_const(*src_offset);
1378 nir_src *indirect_offset = direct ? NULL : src_offset;
1379
1380 if (direct)
1381 offset += nir_src_as_uint(*src_offset);
1382
1383 /* We may need to apply a fractional offset */
1384 int component = (is_flat || is_interp) ?
1385 nir_intrinsic_component(instr) : 0;
1386 reg = nir_dest_index(&instr->dest);
1387
1388 if (is_uniform && !ctx->is_blend) {
1389 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1390 } else if (is_ubo) {
1391 nir_src index = instr->src[0];
1392
1393 /* TODO: Is indirect block number possible? */
1394 assert(nir_src_is_const(index));
1395
1396 uint32_t uindex = nir_src_as_uint(index) + 1;
1397 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1398 } else if (is_global || is_shared) {
1399 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1400 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1401 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1402 } else if (ctx->is_blend) {
1403 /* For blend shaders, load the input color, which is
1404 * preloaded to r0 */
1405
1406 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1407 emit_mir_instruction(ctx, move);
1408 schedule_barrier(ctx);
1409 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1410 emit_attr_read(ctx, reg, offset, nr_comp, t);
1411 } else {
1412 DBG("Unknown load\n");
1413 assert(0);
1414 }
1415
1416 break;
1417 }
1418
1419 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1420 case nir_intrinsic_load_barycentric_pixel:
1421 case nir_intrinsic_load_barycentric_centroid:
1422 break;
1423
1424 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1425
1426 case nir_intrinsic_load_raw_output_pan:
1427 case nir_intrinsic_load_output_u8_as_fp16_pan:
1428 reg = nir_dest_index(&instr->dest);
1429 assert(ctx->is_blend);
1430
1431 /* T720 and below use different blend opcodes with slightly
1432 * different semantics than T760 and up */
1433
1434 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1435 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1436
1437 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1438 ld.load_store.op = old_blend ?
1439 midgard_op_ld_color_buffer_u8_as_fp16_old :
1440 midgard_op_ld_color_buffer_u8_as_fp16;
1441
1442 if (old_blend) {
1443 ld.load_store.address = 1;
1444 ld.load_store.arg_2 = 0x1E;
1445 }
1446
1447 for (unsigned c = 2; c < 16; ++c)
1448 ld.swizzle[0][c] = 0;
1449 }
1450
1451 emit_mir_instruction(ctx, ld);
1452 break;
1453
1454 case nir_intrinsic_load_blend_const_color_rgba: {
1455 assert(ctx->is_blend);
1456 reg = nir_dest_index(&instr->dest);
1457
1458 /* Blend constants are embedded directly in the shader and
1459 * patched in, so we use some magic routing */
1460
1461 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1462 ins.has_constants = true;
1463 ins.has_blend_constant = true;
1464 emit_mir_instruction(ctx, ins);
1465 break;
1466 }
1467
1468 case nir_intrinsic_store_zs_output_pan: {
1469 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1470 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1471 MIDGARD_ZS_RT);
1472
1473 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1474
1475 if (!nir_intrinsic_component(instr))
1476 br->writeout_depth = true;
1477 if (nir_intrinsic_component(instr) ||
1478 instr->num_components)
1479 br->writeout_stencil = true;
1480 assert(br->writeout_depth | br->writeout_stencil);
1481 break;
1482 }
1483
1484 case nir_intrinsic_store_output:
1485 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1486
1487 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1488
1489 reg = nir_src_index(ctx, &instr->src[0]);
1490
1491 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1492 const nir_variable *var;
1493 enum midgard_rt_id rt;
1494
1495 var = search_var(&ctx->nir->outputs,
1496 nir_intrinsic_base(instr));
1497 assert(var);
1498 if (var->data.location == FRAG_RESULT_COLOR)
1499 rt = MIDGARD_COLOR_RT0;
1500 else if (var->data.location >= FRAG_RESULT_DATA0)
1501 rt = MIDGARD_COLOR_RT0 + var->data.location -
1502 FRAG_RESULT_DATA0;
1503 else
1504 assert(0);
1505
1506 emit_fragment_store(ctx, reg, rt);
1507 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1508 /* We should have been vectorized, though we don't
1509 * currently check that st_vary is emitted only once
1510 * per slot (this is relevant, since there's not a mask
1511 * parameter available on the store [set to 0 by the
1512 * blob]). We do respect the component by adjusting the
1513 * swizzle. If this is a constant source, we'll need to
1514 * emit that explicitly. */
1515
1516 emit_explicit_constant(ctx, reg, reg);
1517
1518 unsigned dst_component = nir_intrinsic_component(instr);
1519 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1520
1521 midgard_instruction st = m_st_vary_32(reg, offset);
1522 st.load_store.arg_1 = 0x9E;
1523 st.load_store.arg_2 = 0x1E;
1524
1525 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1526 case nir_type_uint:
1527 case nir_type_bool:
1528 st.load_store.op = midgard_op_st_vary_32u;
1529 break;
1530 case nir_type_int:
1531 st.load_store.op = midgard_op_st_vary_32i;
1532 break;
1533 case nir_type_float:
1534 st.load_store.op = midgard_op_st_vary_32;
1535 break;
1536 default:
1537 unreachable("Attempted to store unknown type");
1538 break;
1539 }
1540
1541 /* nir_intrinsic_component(store_intr) encodes the
1542 * destination component start. Source component offset
1543 * adjustment is taken care of in
1544 * install_registers_instr(), when offset_swizzle() is
1545 * called.
1546 */
1547 unsigned src_component = COMPONENT_X;
1548
1549 assert(nr_comp > 0);
1550 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1551 st.swizzle[0][i] = src_component;
1552 if (i >= dst_component && i < dst_component + nr_comp - 1)
1553 src_component++;
1554 }
1555
1556 emit_mir_instruction(ctx, st);
1557 } else {
1558 DBG("Unknown store\n");
1559 assert(0);
1560 }
1561
1562 break;
1563
1564 /* Special case of store_output for lowered blend shaders */
1565 case nir_intrinsic_store_raw_output_pan:
1566 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1567 reg = nir_src_index(ctx, &instr->src[0]);
1568
1569 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1570 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1571 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1572 * of:
1573 *
1574 * imov r0.xyzw, r0.xxxx
1575 */
1576
1577 unsigned expanded = make_compiler_temp(ctx);
1578
1579 midgard_instruction splatter = v_mov(reg, expanded);
1580
1581 for (unsigned c = 0; c < 16; ++c)
1582 splatter.swizzle[1][c] = 0;
1583
1584 emit_mir_instruction(ctx, splatter);
1585 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1586 } else
1587 emit_fragment_store(ctx, reg, ctx->blend_rt);
1588
1589 break;
1590
1591 case nir_intrinsic_store_global:
1592 case nir_intrinsic_store_shared:
1593 reg = nir_src_index(ctx, &instr->src[0]);
1594 emit_explicit_constant(ctx, reg, reg);
1595
1596 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1597 break;
1598
1599 case nir_intrinsic_load_ssbo_address:
1600 emit_sysval_read(ctx, &instr->instr, 1, 0);
1601 break;
1602
1603 case nir_intrinsic_get_buffer_size:
1604 emit_sysval_read(ctx, &instr->instr, 1, 8);
1605 break;
1606
1607 case nir_intrinsic_load_viewport_scale:
1608 case nir_intrinsic_load_viewport_offset:
1609 case nir_intrinsic_load_num_work_groups:
1610 case nir_intrinsic_load_sampler_lod_parameters_pan:
1611 emit_sysval_read(ctx, &instr->instr, 3, 0);
1612 break;
1613
1614 case nir_intrinsic_load_work_group_id:
1615 case nir_intrinsic_load_local_invocation_id:
1616 emit_compute_builtin(ctx, instr);
1617 break;
1618
1619 case nir_intrinsic_load_vertex_id:
1620 case nir_intrinsic_load_instance_id:
1621 emit_vertex_builtin(ctx, instr);
1622 break;
1623
1624 case nir_intrinsic_memory_barrier_buffer:
1625 case nir_intrinsic_memory_barrier_shared:
1626 break;
1627
1628 case nir_intrinsic_control_barrier:
1629 schedule_barrier(ctx);
1630 emit_control_barrier(ctx);
1631 schedule_barrier(ctx);
1632 break;
1633
1634 default:
1635 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1636 assert(0);
1637 break;
1638 }
1639 }
1640
1641 static unsigned
1642 midgard_tex_format(enum glsl_sampler_dim dim)
1643 {
1644 switch (dim) {
1645 case GLSL_SAMPLER_DIM_1D:
1646 case GLSL_SAMPLER_DIM_BUF:
1647 return MALI_TEX_1D;
1648
1649 case GLSL_SAMPLER_DIM_2D:
1650 case GLSL_SAMPLER_DIM_EXTERNAL:
1651 case GLSL_SAMPLER_DIM_RECT:
1652 return MALI_TEX_2D;
1653
1654 case GLSL_SAMPLER_DIM_3D:
1655 return MALI_TEX_3D;
1656
1657 case GLSL_SAMPLER_DIM_CUBE:
1658 return MALI_TEX_CUBE;
1659
1660 default:
1661 DBG("Unknown sampler dim type\n");
1662 assert(0);
1663 return 0;
1664 }
1665 }
1666
1667 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1668 * was successful */
1669
1670 static bool
1671 pan_attach_constant_bias(
1672 compiler_context *ctx,
1673 nir_src lod,
1674 midgard_texture_word *word)
1675 {
1676 /* To attach as constant, it has to *be* constant */
1677
1678 if (!nir_src_is_const(lod))
1679 return false;
1680
1681 float f = nir_src_as_float(lod);
1682
1683 /* Break into fixed-point */
1684 signed lod_int = f;
1685 float lod_frac = f - lod_int;
1686
1687 /* Carry over negative fractions */
1688 if (lod_frac < 0.0) {
1689 lod_int--;
1690 lod_frac += 1.0;
1691 }
1692
1693 /* Encode */
1694 word->bias = float_to_ubyte(lod_frac);
1695 word->bias_int = lod_int;
1696
1697 return true;
1698 }
1699
1700 static void
1701 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1702 unsigned midgard_texop)
1703 {
1704 /* TODO */
1705 //assert (!instr->sampler);
1706
1707 int texture_index = instr->texture_index;
1708 int sampler_index = texture_index;
1709
1710 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1711 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1712
1713 midgard_instruction ins = {
1714 .type = TAG_TEXTURE_4,
1715 .mask = 0xF,
1716 .dest = nir_dest_index(&instr->dest),
1717 .src = { ~0, ~0, ~0, ~0 },
1718 .dest_type = dest_type,
1719 .swizzle = SWIZZLE_IDENTITY_4,
1720 .texture = {
1721 .op = midgard_texop,
1722 .format = midgard_tex_format(instr->sampler_dim),
1723 .texture_handle = texture_index,
1724 .sampler_handle = sampler_index,
1725 .shadow = instr->is_shadow,
1726 }
1727 };
1728
1729 if (instr->is_shadow && !instr->is_new_style_shadow)
1730 for (int i = 0; i < 4; ++i)
1731 ins.swizzle[0][i] = COMPONENT_X;
1732
1733 /* We may need a temporary for the coordinate */
1734
1735 bool needs_temp_coord =
1736 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1737 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1738 (instr->is_shadow);
1739
1740 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1741
1742 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1743 int index = nir_src_index(ctx, &instr->src[i].src);
1744 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1745 unsigned sz = nir_src_bit_size(instr->src[i].src);
1746 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1747
1748 switch (instr->src[i].src_type) {
1749 case nir_tex_src_coord: {
1750 emit_explicit_constant(ctx, index, index);
1751
1752 unsigned coord_mask = mask_of(instr->coord_components);
1753
1754 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1755
1756 if (flip_zw)
1757 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1758
1759 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1760 /* texelFetch is undefined on samplerCube */
1761 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1762
1763 /* For cubemaps, we use a special ld/st op to
1764 * select the face and copy the xy into the
1765 * texture register */
1766
1767 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1768 ld.src[1] = index;
1769 ld.src_types[1] = T;
1770 ld.mask = 0x3; /* xy */
1771 ld.load_store.arg_1 = 0x20;
1772 ld.swizzle[1][3] = COMPONENT_X;
1773 emit_mir_instruction(ctx, ld);
1774
1775 /* xyzw -> xyxx */
1776 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1777 ins.swizzle[1][3] = COMPONENT_X;
1778 } else if (needs_temp_coord) {
1779 /* mov coord_temp, coords */
1780 midgard_instruction mov = v_mov(index, coords);
1781 mov.mask = coord_mask;
1782
1783 if (flip_zw)
1784 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1785
1786 emit_mir_instruction(ctx, mov);
1787 } else {
1788 coords = index;
1789 }
1790
1791 ins.src[1] = coords;
1792 ins.src_types[1] = T;
1793
1794 /* Texelfetch coordinates uses all four elements
1795 * (xyz/index) regardless of texture dimensionality,
1796 * which means it's necessary to zero the unused
1797 * components to keep everything happy */
1798
1799 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1800 /* mov index.zw, #0, or generalized */
1801 midgard_instruction mov =
1802 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1803 mov.has_constants = true;
1804 mov.mask = coord_mask ^ 0xF;
1805 emit_mir_instruction(ctx, mov);
1806 }
1807
1808 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1809 /* Array component in w but NIR wants it in z,
1810 * but if we have a temp coord we already fixed
1811 * that up */
1812
1813 if (nr_components == 3) {
1814 ins.swizzle[1][2] = COMPONENT_Z;
1815 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1816 } else if (nr_components == 2) {
1817 ins.swizzle[1][2] =
1818 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1819 ins.swizzle[1][3] = COMPONENT_X;
1820 } else
1821 unreachable("Invalid texture 2D components");
1822 }
1823
1824 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1825 /* We zeroed */
1826 ins.swizzle[1][2] = COMPONENT_Z;
1827 ins.swizzle[1][3] = COMPONENT_W;
1828 }
1829
1830 break;
1831 }
1832
1833 case nir_tex_src_bias:
1834 case nir_tex_src_lod: {
1835 /* Try as a constant if we can */
1836
1837 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1838 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1839 break;
1840
1841 ins.texture.lod_register = true;
1842 ins.src[2] = index;
1843 ins.src_types[2] = T;
1844
1845 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1846 ins.swizzle[2][c] = COMPONENT_X;
1847
1848 emit_explicit_constant(ctx, index, index);
1849
1850 break;
1851 };
1852
1853 case nir_tex_src_offset: {
1854 ins.texture.offset_register = true;
1855 ins.src[3] = index;
1856 ins.src_types[3] = T;
1857
1858 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1859 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1860
1861 emit_explicit_constant(ctx, index, index);
1862 break;
1863 };
1864
1865 case nir_tex_src_comparator: {
1866 unsigned comp = COMPONENT_Z;
1867
1868 /* mov coord_temp.foo, coords */
1869 midgard_instruction mov = v_mov(index, coords);
1870 mov.mask = 1 << comp;
1871
1872 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1873 mov.swizzle[1][i] = COMPONENT_X;
1874
1875 emit_mir_instruction(ctx, mov);
1876 break;
1877 }
1878
1879 default: {
1880 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1881 assert(0);
1882 }
1883 }
1884 }
1885
1886 emit_mir_instruction(ctx, ins);
1887 }
1888
1889 static void
1890 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1891 {
1892 switch (instr->op) {
1893 case nir_texop_tex:
1894 case nir_texop_txb:
1895 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1896 break;
1897 case nir_texop_txl:
1898 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1899 break;
1900 case nir_texop_txf:
1901 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1902 break;
1903 case nir_texop_txs:
1904 emit_sysval_read(ctx, &instr->instr, 4, 0);
1905 break;
1906 default: {
1907 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1908 assert(0);
1909 }
1910 }
1911 }
1912
1913 static void
1914 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1915 {
1916 switch (instr->type) {
1917 case nir_jump_break: {
1918 /* Emit a branch out of the loop */
1919 struct midgard_instruction br = v_branch(false, false);
1920 br.branch.target_type = TARGET_BREAK;
1921 br.branch.target_break = ctx->current_loop_depth;
1922 emit_mir_instruction(ctx, br);
1923 break;
1924 }
1925
1926 default:
1927 DBG("Unknown jump type %d\n", instr->type);
1928 break;
1929 }
1930 }
1931
1932 static void
1933 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1934 {
1935 switch (instr->type) {
1936 case nir_instr_type_load_const:
1937 emit_load_const(ctx, nir_instr_as_load_const(instr));
1938 break;
1939
1940 case nir_instr_type_intrinsic:
1941 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1942 break;
1943
1944 case nir_instr_type_alu:
1945 emit_alu(ctx, nir_instr_as_alu(instr));
1946 break;
1947
1948 case nir_instr_type_tex:
1949 emit_tex(ctx, nir_instr_as_tex(instr));
1950 break;
1951
1952 case nir_instr_type_jump:
1953 emit_jump(ctx, nir_instr_as_jump(instr));
1954 break;
1955
1956 case nir_instr_type_ssa_undef:
1957 /* Spurious */
1958 break;
1959
1960 default:
1961 DBG("Unhandled instruction type\n");
1962 break;
1963 }
1964 }
1965
1966
1967 /* ALU instructions can inline or embed constants, which decreases register
1968 * pressure and saves space. */
1969
1970 #define CONDITIONAL_ATTACH(idx) { \
1971 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1972 \
1973 if (entry) { \
1974 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1975 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1976 } \
1977 }
1978
1979 static void
1980 inline_alu_constants(compiler_context *ctx, midgard_block *block)
1981 {
1982 mir_foreach_instr_in_block(block, alu) {
1983 /* Other instructions cannot inline constants */
1984 if (alu->type != TAG_ALU_4) continue;
1985 if (alu->compact_branch) continue;
1986
1987 /* If there is already a constant here, we can do nothing */
1988 if (alu->has_constants) continue;
1989
1990 CONDITIONAL_ATTACH(0);
1991
1992 if (!alu->has_constants) {
1993 CONDITIONAL_ATTACH(1)
1994 } else if (!alu->inline_constant) {
1995 /* Corner case: _two_ vec4 constants, for instance with a
1996 * csel. For this case, we can only use a constant
1997 * register for one, we'll have to emit a move for the
1998 * other. */
1999
2000 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2001 unsigned scratch = make_compiler_temp(ctx);
2002
2003 if (entry) {
2004 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2005 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2006
2007 /* Set the source */
2008 alu->src[1] = scratch;
2009
2010 /* Inject us -before- the last instruction which set r31 */
2011 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2012 }
2013 }
2014 }
2015 }
2016
2017 /* Midgard supports two types of constants, embedded constants (128-bit) and
2018 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2019 * constants can be demoted to inline constants, for space savings and
2020 * sometimes a performance boost */
2021
2022 static void
2023 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2024 {
2025 mir_foreach_instr_in_block(block, ins) {
2026 if (!ins->has_constants) continue;
2027 if (ins->has_inline_constant) continue;
2028
2029 /* Blend constants must not be inlined by definition */
2030 if (ins->has_blend_constant) continue;
2031
2032 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2033 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2034 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2035
2036 if (!(is_16 || is_32))
2037 continue;
2038
2039 /* src1 cannot be an inline constant due to encoding
2040 * restrictions. So, if possible we try to flip the arguments
2041 * in that case */
2042
2043 int op = ins->alu.op;
2044
2045 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2046 alu_opcode_props[op].props & OP_COMMUTES) {
2047 mir_flip(ins);
2048 }
2049
2050 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2051 /* Extract the source information */
2052
2053 midgard_vector_alu_src *src;
2054 int q = ins->alu.src2;
2055 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2056 src = m;
2057
2058 /* Component is from the swizzle. Take a nonzero component */
2059 assert(ins->mask);
2060 unsigned first_comp = ffs(ins->mask) - 1;
2061 unsigned component = ins->swizzle[1][first_comp];
2062
2063 /* Scale constant appropriately, if we can legally */
2064 uint16_t scaled_constant = 0;
2065
2066 if (is_16) {
2067 scaled_constant = ins->constants.u16[component];
2068 } else if (midgard_is_integer_op(op)) {
2069 scaled_constant = ins->constants.u32[component];
2070
2071 /* Constant overflow after resize */
2072 if (scaled_constant != ins->constants.u32[component])
2073 continue;
2074 } else {
2075 float original = ins->constants.f32[component];
2076 scaled_constant = _mesa_float_to_half(original);
2077
2078 /* Check for loss of precision. If this is
2079 * mediump, we don't care, but for a highp
2080 * shader, we need to pay attention. NIR
2081 * doesn't yet tell us which mode we're in!
2082 * Practically this prevents most constants
2083 * from being inlined, sadly. */
2084
2085 float fp32 = _mesa_half_to_float(scaled_constant);
2086
2087 if (fp32 != original)
2088 continue;
2089 }
2090
2091 /* We don't know how to handle these with a constant */
2092
2093 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2094 DBG("Bailing inline constant...\n");
2095 continue;
2096 }
2097
2098 /* Make sure that the constant is not itself a vector
2099 * by checking if all accessed values are the same. */
2100
2101 const midgard_constants *cons = &ins->constants;
2102 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2103
2104 bool is_vector = false;
2105 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2106
2107 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2108 /* We only care if this component is actually used */
2109 if (!(mask & (1 << c)))
2110 continue;
2111
2112 uint32_t test = is_16 ?
2113 cons->u16[ins->swizzle[1][c]] :
2114 cons->u32[ins->swizzle[1][c]];
2115
2116 if (test != value) {
2117 is_vector = true;
2118 break;
2119 }
2120 }
2121
2122 if (is_vector)
2123 continue;
2124
2125 /* Get rid of the embedded constant */
2126 ins->has_constants = false;
2127 ins->src[1] = ~0;
2128 ins->has_inline_constant = true;
2129 ins->inline_constant = scaled_constant;
2130 }
2131 }
2132 }
2133
2134 /* Dead code elimination for branches at the end of a block - only one branch
2135 * per block is legal semantically */
2136
2137 static void
2138 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2139 {
2140 bool branched = false;
2141
2142 mir_foreach_instr_in_block_safe(block, ins) {
2143 if (!midgard_is_branch_unit(ins->unit)) continue;
2144
2145 if (branched)
2146 mir_remove_instruction(ins);
2147
2148 branched = true;
2149 }
2150 }
2151
2152 static unsigned
2153 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2154 {
2155 /* Loop to ourselves */
2156 midgard_instruction *br = ctx->writeout_branch[rt];
2157 struct midgard_instruction ins = v_branch(false, false);
2158 ins.writeout = true;
2159 ins.writeout_depth = br->writeout_depth;
2160 ins.writeout_stencil = br->writeout_stencil;
2161 ins.branch.target_block = ctx->block_count - 1;
2162 ins.constants.u32[0] = br->constants.u32[0];
2163 emit_mir_instruction(ctx, ins);
2164
2165 ctx->current_block->epilogue = true;
2166 schedule_barrier(ctx);
2167 return ins.branch.target_block;
2168 }
2169
2170 static midgard_block *
2171 emit_block(compiler_context *ctx, nir_block *block)
2172 {
2173 midgard_block *this_block = ctx->after_block;
2174 ctx->after_block = NULL;
2175
2176 if (!this_block)
2177 this_block = create_empty_block(ctx);
2178
2179 list_addtail(&this_block->base.link, &ctx->blocks);
2180
2181 this_block->scheduled = false;
2182 ++ctx->block_count;
2183
2184 /* Set up current block */
2185 list_inithead(&this_block->base.instructions);
2186 ctx->current_block = this_block;
2187
2188 nir_foreach_instr(instr, block) {
2189 emit_instr(ctx, instr);
2190 ++ctx->instruction_count;
2191 }
2192
2193 return this_block;
2194 }
2195
2196 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2197
2198 static void
2199 emit_if(struct compiler_context *ctx, nir_if *nif)
2200 {
2201 midgard_block *before_block = ctx->current_block;
2202
2203 /* Speculatively emit the branch, but we can't fill it in until later */
2204 EMIT(branch, true, true);
2205 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2206 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2207 then_branch->src_types[0] = nir_type_uint32;
2208
2209 /* Emit the two subblocks. */
2210 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2211 midgard_block *end_then_block = ctx->current_block;
2212
2213 /* Emit a jump from the end of the then block to the end of the else */
2214 EMIT(branch, false, false);
2215 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2216
2217 /* Emit second block, and check if it's empty */
2218
2219 int else_idx = ctx->block_count;
2220 int count_in = ctx->instruction_count;
2221 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2222 midgard_block *end_else_block = ctx->current_block;
2223 int after_else_idx = ctx->block_count;
2224
2225 /* Now that we have the subblocks emitted, fix up the branches */
2226
2227 assert(then_block);
2228 assert(else_block);
2229
2230 if (ctx->instruction_count == count_in) {
2231 /* The else block is empty, so don't emit an exit jump */
2232 mir_remove_instruction(then_exit);
2233 then_branch->branch.target_block = after_else_idx;
2234 } else {
2235 then_branch->branch.target_block = else_idx;
2236 then_exit->branch.target_block = after_else_idx;
2237 }
2238
2239 /* Wire up the successors */
2240
2241 ctx->after_block = create_empty_block(ctx);
2242
2243 pan_block_add_successor(&before_block->base, &then_block->base);
2244 pan_block_add_successor(&before_block->base, &else_block->base);
2245
2246 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2247 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2248 }
2249
2250 static void
2251 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2252 {
2253 /* Remember where we are */
2254 midgard_block *start_block = ctx->current_block;
2255
2256 /* Allocate a loop number, growing the current inner loop depth */
2257 int loop_idx = ++ctx->current_loop_depth;
2258
2259 /* Get index from before the body so we can loop back later */
2260 int start_idx = ctx->block_count;
2261
2262 /* Emit the body itself */
2263 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2264
2265 /* Branch back to loop back */
2266 struct midgard_instruction br_back = v_branch(false, false);
2267 br_back.branch.target_block = start_idx;
2268 emit_mir_instruction(ctx, br_back);
2269
2270 /* Mark down that branch in the graph. */
2271 pan_block_add_successor(&start_block->base, &loop_block->base);
2272 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2273
2274 /* Find the index of the block about to follow us (note: we don't add
2275 * one; blocks are 0-indexed so we get a fencepost problem) */
2276 int break_block_idx = ctx->block_count;
2277
2278 /* Fix up the break statements we emitted to point to the right place,
2279 * now that we can allocate a block number for them */
2280 ctx->after_block = create_empty_block(ctx);
2281
2282 mir_foreach_block_from(ctx, start_block, _block) {
2283 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2284 if (ins->type != TAG_ALU_4) continue;
2285 if (!ins->compact_branch) continue;
2286
2287 /* We found a branch -- check the type to see if we need to do anything */
2288 if (ins->branch.target_type != TARGET_BREAK) continue;
2289
2290 /* It's a break! Check if it's our break */
2291 if (ins->branch.target_break != loop_idx) continue;
2292
2293 /* Okay, cool, we're breaking out of this loop.
2294 * Rewrite from a break to a goto */
2295
2296 ins->branch.target_type = TARGET_GOTO;
2297 ins->branch.target_block = break_block_idx;
2298
2299 pan_block_add_successor(_block, &ctx->after_block->base);
2300 }
2301 }
2302
2303 /* Now that we've finished emitting the loop, free up the depth again
2304 * so we play nice with recursion amid nested loops */
2305 --ctx->current_loop_depth;
2306
2307 /* Dump loop stats */
2308 ++ctx->loop_count;
2309 }
2310
2311 static midgard_block *
2312 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2313 {
2314 midgard_block *start_block = NULL;
2315
2316 foreach_list_typed(nir_cf_node, node, node, list) {
2317 switch (node->type) {
2318 case nir_cf_node_block: {
2319 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2320
2321 if (!start_block)
2322 start_block = block;
2323
2324 break;
2325 }
2326
2327 case nir_cf_node_if:
2328 emit_if(ctx, nir_cf_node_as_if(node));
2329 break;
2330
2331 case nir_cf_node_loop:
2332 emit_loop(ctx, nir_cf_node_as_loop(node));
2333 break;
2334
2335 case nir_cf_node_function:
2336 assert(0);
2337 break;
2338 }
2339 }
2340
2341 return start_block;
2342 }
2343
2344 /* Due to lookahead, we need to report the first tag executed in the command
2345 * stream and in branch targets. An initial block might be empty, so iterate
2346 * until we find one that 'works' */
2347
2348 static unsigned
2349 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2350 {
2351 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2352
2353 mir_foreach_block_from(ctx, initial_block, _v) {
2354 midgard_block *v = (midgard_block *) _v;
2355 if (v->quadword_count) {
2356 midgard_bundle *initial_bundle =
2357 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2358
2359 return initial_bundle->tag;
2360 }
2361 }
2362
2363 /* Default to a tag 1 which will break from the shader, in case we jump
2364 * to the exit block (i.e. `return` in a compute shader) */
2365
2366 return 1;
2367 }
2368
2369 /* For each fragment writeout instruction, generate a writeout loop to
2370 * associate with it */
2371
2372 static void
2373 mir_add_writeout_loops(compiler_context *ctx)
2374 {
2375 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2376 midgard_instruction *br = ctx->writeout_branch[rt];
2377 if (!br) continue;
2378
2379 unsigned popped = br->branch.target_block;
2380 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2381 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2382 br->branch.target_type = TARGET_GOTO;
2383
2384 /* If we have more RTs, we'll need to restore back after our
2385 * loop terminates */
2386
2387 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2388 midgard_instruction uncond = v_branch(false, false);
2389 uncond.branch.target_block = popped;
2390 uncond.branch.target_type = TARGET_GOTO;
2391 emit_mir_instruction(ctx, uncond);
2392 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2393 schedule_barrier(ctx);
2394 } else {
2395 /* We're last, so we can terminate here */
2396 br->last_writeout = true;
2397 }
2398 }
2399 }
2400
2401 int
2402 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2403 {
2404 struct util_dynarray *compiled = &program->compiled;
2405
2406 midgard_debug = debug_get_option_midgard_debug();
2407
2408 /* TODO: Bound against what? */
2409 compiler_context *ctx = rzalloc(NULL, compiler_context);
2410
2411 ctx->nir = nir;
2412 ctx->stage = nir->info.stage;
2413 ctx->is_blend = is_blend;
2414 ctx->alpha_ref = program->alpha_ref;
2415 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2416 ctx->quirks = midgard_get_quirks(gpu_id);
2417
2418 /* Start off with a safe cutoff, allowing usage of all 16 work
2419 * registers. Later, we'll promote uniform reads to uniform registers
2420 * if we determine it is beneficial to do so */
2421 ctx->uniform_cutoff = 8;
2422
2423 /* Initialize at a global (not block) level hash tables */
2424
2425 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2426 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2427
2428 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2429 * (so we don't accidentally duplicate the epilogue since mesa/st has
2430 * messed with our I/O quite a bit already) */
2431
2432 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2433
2434 if (ctx->stage == MESA_SHADER_VERTEX) {
2435 NIR_PASS_V(nir, nir_lower_viewport_transform);
2436 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2437 }
2438
2439 NIR_PASS_V(nir, nir_lower_var_copies);
2440 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2441 NIR_PASS_V(nir, nir_split_var_copies);
2442 NIR_PASS_V(nir, nir_lower_var_copies);
2443 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2444 NIR_PASS_V(nir, nir_lower_var_copies);
2445 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2446
2447 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2448 NIR_PASS_V(nir, nir_lower_ssbo);
2449 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2450
2451 /* Optimisation passes */
2452
2453 optimise_nir(nir, ctx->quirks);
2454
2455 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2456 nir_print_shader(nir, stdout);
2457 }
2458
2459 /* Assign sysvals and counts, now that we're sure
2460 * (post-optimisation) */
2461
2462 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2463 program->sysval_count = ctx->sysvals.sysval_count;
2464 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2465
2466 nir_foreach_function(func, nir) {
2467 if (!func->impl)
2468 continue;
2469
2470 list_inithead(&ctx->blocks);
2471 ctx->block_count = 0;
2472 ctx->func = func;
2473
2474 emit_cf_list(ctx, &func->impl->body);
2475 break; /* TODO: Multi-function shaders */
2476 }
2477
2478 util_dynarray_init(compiled, NULL);
2479
2480 /* Per-block lowering before opts */
2481
2482 mir_foreach_block(ctx, _block) {
2483 midgard_block *block = (midgard_block *) _block;
2484 inline_alu_constants(ctx, block);
2485 midgard_opt_promote_fmov(ctx, block);
2486 embedded_to_inline_constant(ctx, block);
2487 }
2488 /* MIR-level optimizations */
2489
2490 bool progress = false;
2491
2492 do {
2493 progress = false;
2494
2495 mir_foreach_block(ctx, _block) {
2496 midgard_block *block = (midgard_block *) _block;
2497 progress |= midgard_opt_copy_prop(ctx, block);
2498 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2499 progress |= midgard_opt_combine_projection(ctx, block);
2500 progress |= midgard_opt_varying_projection(ctx, block);
2501 progress |= midgard_opt_not_propagate(ctx, block);
2502 progress |= midgard_opt_fuse_src_invert(ctx, block);
2503 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2504 progress |= midgard_opt_csel_invert(ctx, block);
2505 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2506 progress |= midgard_opt_invert_branch(ctx, block);
2507 }
2508 } while (progress);
2509
2510 mir_foreach_block(ctx, _block) {
2511 midgard_block *block = (midgard_block *) _block;
2512 midgard_lower_invert(ctx, block);
2513 midgard_lower_derivatives(ctx, block);
2514 }
2515
2516 /* Nested control-flow can result in dead branches at the end of the
2517 * block. This messes with our analysis and is just dead code, so cull
2518 * them */
2519 mir_foreach_block(ctx, _block) {
2520 midgard_block *block = (midgard_block *) _block;
2521 midgard_cull_dead_branch(ctx, block);
2522 }
2523
2524 /* Ensure we were lowered */
2525 mir_foreach_instr_global(ctx, ins) {
2526 assert(!ins->invert);
2527 }
2528
2529 if (ctx->stage == MESA_SHADER_FRAGMENT)
2530 mir_add_writeout_loops(ctx);
2531
2532 /* Analyze now that the code is known but before scheduling creates
2533 * pipeline registers which are harder to track */
2534 mir_analyze_helper_terminate(ctx);
2535 mir_analyze_helper_requirements(ctx);
2536
2537 /* Schedule! */
2538 midgard_schedule_program(ctx);
2539 mir_ra(ctx);
2540
2541 /* Now that all the bundles are scheduled and we can calculate block
2542 * sizes, emit actual branch instructions rather than placeholders */
2543
2544 int br_block_idx = 0;
2545
2546 mir_foreach_block(ctx, _block) {
2547 midgard_block *block = (midgard_block *) _block;
2548 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2549 for (int c = 0; c < bundle->instruction_count; ++c) {
2550 midgard_instruction *ins = bundle->instructions[c];
2551
2552 if (!midgard_is_branch_unit(ins->unit)) continue;
2553
2554 /* Parse some basic branch info */
2555 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2556 bool is_conditional = ins->branch.conditional;
2557 bool is_inverted = ins->branch.invert_conditional;
2558 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2559 bool is_writeout = ins->writeout;
2560
2561 /* Determine the block we're jumping to */
2562 int target_number = ins->branch.target_block;
2563
2564 /* Report the destination tag */
2565 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2566
2567 /* Count up the number of quadwords we're
2568 * jumping over = number of quadwords until
2569 * (br_block_idx, target_number) */
2570
2571 int quadword_offset = 0;
2572
2573 if (is_discard) {
2574 /* Ignored */
2575 } else if (target_number > br_block_idx) {
2576 /* Jump forward */
2577
2578 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2579 midgard_block *blk = mir_get_block(ctx, idx);
2580 assert(blk);
2581
2582 quadword_offset += blk->quadword_count;
2583 }
2584 } else {
2585 /* Jump backwards */
2586
2587 for (int idx = br_block_idx; idx >= target_number; --idx) {
2588 midgard_block *blk = mir_get_block(ctx, idx);
2589 assert(blk);
2590
2591 quadword_offset -= blk->quadword_count;
2592 }
2593 }
2594
2595 /* Unconditional extended branches (far jumps)
2596 * have issues, so we always use a conditional
2597 * branch, setting the condition to always for
2598 * unconditional. For compact unconditional
2599 * branches, cond isn't used so it doesn't
2600 * matter what we pick. */
2601
2602 midgard_condition cond =
2603 !is_conditional ? midgard_condition_always :
2604 is_inverted ? midgard_condition_false :
2605 midgard_condition_true;
2606
2607 midgard_jmp_writeout_op op =
2608 is_discard ? midgard_jmp_writeout_op_discard :
2609 is_writeout ? midgard_jmp_writeout_op_writeout :
2610 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2611 midgard_jmp_writeout_op_branch_cond;
2612
2613 if (!is_compact) {
2614 midgard_branch_extended branch =
2615 midgard_create_branch_extended(
2616 cond, op,
2617 dest_tag,
2618 quadword_offset);
2619
2620 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2621 } else if (is_conditional || is_discard) {
2622 midgard_branch_cond branch = {
2623 .op = op,
2624 .dest_tag = dest_tag,
2625 .offset = quadword_offset,
2626 .cond = cond
2627 };
2628
2629 assert(branch.offset == quadword_offset);
2630
2631 memcpy(&ins->br_compact, &branch, sizeof(branch));
2632 } else {
2633 assert(op == midgard_jmp_writeout_op_branch_uncond);
2634
2635 midgard_branch_uncond branch = {
2636 .op = op,
2637 .dest_tag = dest_tag,
2638 .offset = quadword_offset,
2639 .unknown = 1
2640 };
2641
2642 assert(branch.offset == quadword_offset);
2643
2644 memcpy(&ins->br_compact, &branch, sizeof(branch));
2645 }
2646 }
2647 }
2648
2649 ++br_block_idx;
2650 }
2651
2652 /* Emit flat binary from the instruction arrays. Iterate each block in
2653 * sequence. Save instruction boundaries such that lookahead tags can
2654 * be assigned easily */
2655
2656 /* Cache _all_ bundles in source order for lookahead across failed branches */
2657
2658 int bundle_count = 0;
2659 mir_foreach_block(ctx, _block) {
2660 midgard_block *block = (midgard_block *) _block;
2661 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2662 }
2663 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2664 int bundle_idx = 0;
2665 mir_foreach_block(ctx, _block) {
2666 midgard_block *block = (midgard_block *) _block;
2667 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2668 source_order_bundles[bundle_idx++] = bundle;
2669 }
2670 }
2671
2672 int current_bundle = 0;
2673
2674 /* Midgard prefetches instruction types, so during emission we
2675 * need to lookahead. Unless this is the last instruction, in
2676 * which we return 1. */
2677
2678 mir_foreach_block(ctx, _block) {
2679 midgard_block *block = (midgard_block *) _block;
2680 mir_foreach_bundle_in_block(block, bundle) {
2681 int lookahead = 1;
2682
2683 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2684 lookahead = source_order_bundles[current_bundle + 1]->tag;
2685
2686 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2687 ++current_bundle;
2688 }
2689
2690 /* TODO: Free deeper */
2691 //util_dynarray_fini(&block->instructions);
2692 }
2693
2694 free(source_order_bundles);
2695
2696 /* Report the very first tag executed */
2697 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2698
2699 /* Deal with off-by-one related to the fencepost problem */
2700 program->work_register_count = ctx->work_registers + 1;
2701 program->uniform_cutoff = ctx->uniform_cutoff;
2702
2703 program->blend_patch_offset = ctx->blend_constant_offset;
2704 program->tls_size = ctx->tls_size;
2705
2706 if (midgard_debug & MIDGARD_DBG_SHADERS)
2707 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2708
2709 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2710 unsigned nr_bundles = 0, nr_ins = 0;
2711
2712 /* Count instructions and bundles */
2713
2714 mir_foreach_block(ctx, _block) {
2715 midgard_block *block = (midgard_block *) _block;
2716 nr_bundles += util_dynarray_num_elements(
2717 &block->bundles, midgard_bundle);
2718
2719 mir_foreach_bundle_in_block(block, bun)
2720 nr_ins += bun->instruction_count;
2721 }
2722
2723 /* Calculate thread count. There are certain cutoffs by
2724 * register count for thread count */
2725
2726 unsigned nr_registers = program->work_register_count;
2727
2728 unsigned nr_threads =
2729 (nr_registers <= 4) ? 4 :
2730 (nr_registers <= 8) ? 2 :
2731 1;
2732
2733 /* Dump stats */
2734
2735 fprintf(stderr, "shader%d - %s shader: "
2736 "%u inst, %u bundles, %u quadwords, "
2737 "%u registers, %u threads, %u loops, "
2738 "%u:%u spills:fills\n",
2739 SHADER_DB_COUNT++,
2740 gl_shader_stage_name(ctx->stage),
2741 nr_ins, nr_bundles, ctx->quadword_count,
2742 nr_registers, nr_threads,
2743 ctx->loop_count,
2744 ctx->spills, ctx->fills);
2745 }
2746
2747 ralloc_free(ctx);
2748
2749 return 0;
2750 }