cb560c1a29f2c802c22affdf72950d9a99c18784
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
4 from nmutil
.latch
import SRLatch
7 class DependenceCell(Elaboratable
):
8 """ implements 11.4.7 mitch alsup dependence cell, p27
12 self
.dest_i
= Signal(reset_less
=True) # Dest in (top)
13 self
.src1_i
= Signal(reset_less
=True) # oper1 in (top)
14 self
.src2_i
= Signal(reset_less
=True) # oper2 in (top)
15 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
17 self
.go_wr_i
= Signal(reset_less
=True) # Go Write in (left)
18 self
.go_rd_i
= Signal(reset_less
=True) # Go Read in (left)
20 # for Register File Select Lines (vertical)
21 self
.dest_rsel_o
= Signal(reset_less
=True) # dest reg sel (bottom)
22 self
.src1_rsel_o
= Signal(reset_less
=True) # src1 reg sel (bottom)
23 self
.src2_rsel_o
= Signal(reset_less
=True) # src2 reg sel (bottom)
25 # for Function Unit "forward progress" (horizontal)
26 self
.dest_fwd_o
= Signal(reset_less
=True) # dest FU fw (right)
27 self
.src1_fwd_o
= Signal(reset_less
=True) # src1 FU fw (right)
28 self
.src2_fwd_o
= Signal(reset_less
=True) # src2 FU fw (right)
30 def elaborate(self
, platform
):
32 m
.submodules
.dest_l
= dest_l
= SRLatch() # clock-sync'd
33 m
.submodules
.src1_l
= src1_l
= SRLatch() # clock-sync'd
34 m
.submodules
.src2_l
= src2_l
= SRLatch() # clock-sync'd
36 # destination latch: reset on go_wr HI, set on dest and issue
37 m
.d
.comb
+= dest_l
.s
.eq(self
.issue_i
& self
.dest_i
)
38 m
.d
.comb
+= dest_l
.r
.eq(self
.go_wr_i
)
40 # src1 latch: reset on go_rd HI, set on src1_i and issue
41 m
.d
.comb
+= src1_l
.s
.eq(self
.issue_i
& self
.src1_i
)
42 m
.d
.comb
+= src1_l
.r
.eq(self
.go_rd_i
)
44 # src2 latch: reset on go_rd HI, set on op2_i and issue
45 m
.d
.sync
+= src2_l
.s
.eq(self
.issue_i
& self
.src2_i
)
46 m
.d
.sync
+= src2_l
.r
.eq(self
.go_rd_i
)
48 # FU "Forward Progress" (read out horizontally)
49 m
.d
.comb
+= self
.dest_fwd_o
.eq(dest_l
.q
& self
.dest_i
)
50 m
.d
.comb
+= self
.src1_fwd_o
.eq(src1_l
.q
& self
.src1_i
)
51 m
.d
.comb
+= self
.src2_fwd_o
.eq(src2_l
.q
& self
.src2_i
)
53 # Register File Select (read out vertically)
54 m
.d
.comb
+= self
.dest_rsel_o
.eq(dest_l
.q
& self
.go_wr_i
)
55 m
.d
.comb
+= self
.src1_rsel_o
.eq(src1_l
.q
& self
.go_rd_i
)
56 m
.d
.comb
+= self
.src2_rsel_o
.eq(src2_l
.q
& self
.go_rd_i
)
67 yield self
.dest_rsel_o
68 yield self
.src1_rsel_o
69 yield self
.src2_rsel_o
79 yield dut
.dest_i
.eq(1)
80 yield dut
.issue_i
.eq(1)
82 yield dut
.issue_i
.eq(0)
84 yield dut
.src1_i
.eq(1)
85 yield dut
.issue_i
.eq(1)
89 yield dut
.issue_i
.eq(0)
91 yield dut
.go_rd_i
.eq(1)
93 yield dut
.go_rd_i
.eq(0)
95 yield dut
.go_wr_i
.eq(1)
97 yield dut
.go_wr_i
.eq(0)
101 dut
= DependenceCell()
102 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
103 with
open("test_dcell.il", "w") as f
:
106 run_simulation(dut
, dcell_sim(dut
), vcd_name
='test_dcell.vcd')
108 if __name__
== '__main__':