84aaeb89b325c59154b64ebd0cc060521cdcf932
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
, Array
, Cat
5 from scoreboard
.dependence_cell
import DependencyRow
6 from scoreboard
.fu_wr_pending
import FU_RW_Pend
7 from scoreboard
.reg_select
import Reg_Rsv
8 from scoreboard
.global_pending
import GlobalPending
12 6600 Dependency Table Matrix inputs / outputs
13 ---------------------------------------------
15 d s1 s2 i d s1 s2 i d s1 s2 i d s1 s2 i
16 | | | | | | | | | | | | | | | |
17 v v v v v v v v v v v v v v v v
18 go_rd/go_wr -> dm-r0-fu0 dm-r1-fu0 dm-r2-fu0 dm-r3-fu0 -> wr/rd-pend
19 go_rd/go_wr -> dm-r0-fu1 dm-r1-fu1 dm-r2-fu1 dm-r3-fu1 -> wr/rd-pend
20 go_rd/go_wr -> dm-r0-fu2 dm-r1-fu2 dm-r2-fu2 dm-r3-fu2 -> wr/rd-pend
21 | | | | | | | | | | | |
22 v v v v v v v v v v v v
23 d s1 s2 d s1 s2 d s1 s2 d s1 s2
24 reg sel reg sel reg sel reg sel
28 class FURegDepMatrix(Elaboratable
):
29 """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
31 def __init__(self
, n_fu_row
, n_reg_col
, n_src
):
33 self
.n_fu_row
= nf
= n_fu_row
# Y (FUs) ^v
34 self
.n_reg_col
= n_reg
= n_reg_col
# X (Regs) <>
39 for i
in range(n_src
):
40 j
= i
+ 1 # name numbering to match src1/src2
41 src
.append(Signal(n_reg
, name
="src%d" % j
, reset_less
=True))
42 rsel
.append(Signal(n_reg
, name
="src%d_rsel_o" % j
, reset_less
=True))
45 j
= i
+ 1 # name numbering to match src1/src2
46 pend
.append(Signal(nf
, name
="rd_src%d_pend_o" % j
, reset_less
=True))
48 self
.dest_i
= Signal(n_reg_col
, reset_less
=True) # Dest in (top)
49 self
.src_i
= Array(src
) # oper in (top)
51 # Register "Global" vectors for determining RaW and WaR hazards
52 self
.wr_pend_i
= Signal(n_reg_col
, reset_less
=True) # wr pending (top)
53 self
.rd_pend_i
= Signal(n_reg_col
, reset_less
=True) # rd pending (top)
54 self
.v_wr_rsel_o
= Signal(n_reg_col
, reset_less
=True) # wr pending (bot)
55 self
.v_rd_rsel_o
= Signal(n_reg_col
, reset_less
=True) # rd pending (bot)
57 self
.issue_i
= Signal(n_fu_row
, reset_less
=True) # Issue in (top)
58 self
.go_wr_i
= Signal(n_fu_row
, reset_less
=True) # Go Write in (left)
59 self
.go_rd_i
= Signal(n_fu_row
, reset_less
=True) # Go Read in (left)
60 self
.go_die_i
= Signal(n_fu_row
, reset_less
=True) # Go Die in (left)
62 # for Register File Select Lines (horizontal), per-reg
63 self
.dest_rsel_o
= Signal(n_reg_col
, reset_less
=True) # dest reg (bot)
64 self
.src_rsel_o
= Array(rsel
) # src reg (bot)
66 # for Function Unit "forward progress" (vertical), per-FU
67 self
.wr_pend_o
= Signal(n_fu_row
, reset_less
=True) # wr pending (right)
68 self
.rd_pend_o
= Signal(n_fu_row
, reset_less
=True) # rd pending (right)
69 self
.rd_src_pend_o
= Array(pend
) # src1 pending
71 def elaborate(self
, platform
):
75 # matrix of dependency cells
77 dm
= Array(DependencyRow(self
.n_reg_col
, self
.n_src
) \
78 for r
in range(self
.n_fu_row
))
79 for fu
in range(self
.n_fu_row
):
80 setattr(m
.submodules
, "dr_fu%d" % fu
, dm
[fu
])
83 # array of Function Unit Pending vectors
85 fupend
= Array(FU_RW_Pend(self
.n_reg_col
, self
.n_src
) \
86 for f
in range(self
.n_fu_row
))
87 for fu
in range(self
.n_fu_row
):
88 setattr(m
.submodules
, "fu_fu%d" % (fu
), fupend
[fu
])
91 # array of Register Reservation vectors
93 regrsv
= Array(Reg_Rsv(self
.n_fu_row
) for r
in range(self
.n_reg_col
))
94 for rn
in range(self
.n_reg_col
):
95 setattr(m
.submodules
, "rr_r%d" % (rn
), regrsv
[rn
])
98 # connect Function Unit vector
104 for fu
in range(self
.n_fu_row
):
110 for rn
in range(self
.n_reg_col
):
111 # accumulate cell fwd outputs for dest/src1/src2
112 dest_fwd_o
.append(dc
.dest_fwd_o
[rn
])
113 src1_fwd_o
.append(dc
.src_fwd_o
[0][rn
])
114 src2_fwd_o
.append(dc
.src_fwd_o
[1][rn
])
115 # connect cell fwd outputs to FU Vector in [Cat is gooood]
116 m
.d
.comb
+= [fup
.dest_fwd_i
.eq(Cat(*dest_fwd_o
)),
117 fup
.src_fwd_i
[0].eq(Cat(*src1_fwd_o
)),
118 fup
.src_fwd_i
[1].eq(Cat(*src2_fwd_o
))
120 # accumulate FU Vector outputs
121 wr_pend
.append(fup
.reg_wr_pend_o
)
122 rd_pend
.append(fup
.reg_rd_pend_o
)
123 rd_src1_pend
.append(fup
.reg_rd_src_pend_o
[0])
124 rd_src2_pend
.append(fup
.reg_rd_src_pend_o
[1])
126 # ... and output them from this module (vertical, width=FUs)
127 m
.d
.comb
+= self
.wr_pend_o
.eq(Cat(*wr_pend
))
128 m
.d
.comb
+= self
.rd_pend_o
.eq(Cat(*rd_pend
))
129 m
.d
.comb
+= self
.rd_src_pend_o
[0].eq(Cat(*rd_src1_pend
))
130 m
.d
.comb
+= self
.rd_src_pend_o
[1].eq(Cat(*rd_src2_pend
))
133 # connect Reg Selection vector
138 for rn
in range(self
.n_reg_col
):
143 for fu
in range(self
.n_fu_row
):
145 # accumulate cell reg-select outputs dest/src1/src2
146 dest_rsel_o
.append(dc
.dest_rsel_o
[rn
])
147 src1_rsel_o
.append(dc
.src_rsel_o
[0][rn
])
148 src2_rsel_o
.append(dc
.src_rsel_o
[1][rn
])
149 # connect cell reg-select outputs to Reg Vector In
150 m
.d
.comb
+= [rsv
.dest_rsel_i
.eq(Cat(*dest_rsel_o
)),
151 rsv
.src1_rsel_i
.eq(Cat(*src1_rsel_o
)),
152 rsv
.src2_rsel_i
.eq(Cat(*src2_rsel_o
)),
154 # accumulate Reg-Sel Vector outputs
155 dest_rsel
.append(rsv
.dest_rsel_o
)
156 src1_rsel
.append(rsv
.src1_rsel_o
)
157 src2_rsel
.append(rsv
.src2_rsel_o
)
159 # ... and output them from this module (horizontal, width=REGs)
160 m
.d
.comb
+= self
.dest_rsel_o
.eq(Cat(*dest_rsel
))
161 m
.d
.comb
+= self
.src_rsel_o
[0].eq(Cat(*src1_rsel
))
162 m
.d
.comb
+= self
.src_rsel_o
[1].eq(Cat(*src2_rsel
))
165 # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
167 for fu
in range(self
.n_fu_row
):
169 # wire up inputs from module to row cell inputs (Cat is gooood)
170 m
.d
.comb
+= [dc
.dest_i
.eq(self
.dest_i
),
171 dc
.src_i
[0].eq(self
.src_i
[0]),
172 dc
.src_i
[1].eq(self
.src_i
[1]),
173 dc
.rd_pend_i
.eq(self
.rd_pend_i
),
174 dc
.wr_pend_i
.eq(self
.wr_pend_i
),
177 # accumulate rsel bits into read/write pending vectors.
180 for fu
in range(self
.n_fu_row
):
182 rd_pend_v
.append(dc
.v_rd_rsel_o
)
183 wr_pend_v
.append(dc
.v_wr_rsel_o
)
184 rd_v
= GlobalPending(self
.n_reg_col
, rd_pend_v
)
185 wr_v
= GlobalPending(self
.n_reg_col
, wr_pend_v
)
186 m
.submodules
.rd_v
= rd_v
187 m
.submodules
.wr_v
= wr_v
189 m
.d
.comb
+= self
.v_rd_rsel_o
.eq(rd_v
.g_pend_o
)
190 m
.d
.comb
+= self
.v_wr_rsel_o
.eq(wr_v
.g_pend_o
)
193 # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
199 for fu
in range(self
.n_fu_row
):
201 # accumulate cell fwd outputs for dest/src1/src2
202 go_rd_i
.append(dc
.go_rd_i
)
203 go_wr_i
.append(dc
.go_wr_i
)
204 go_die_i
.append(dc
.go_die_i
)
205 issue_i
.append(dc
.issue_i
)
206 # wire up inputs from module to row cell inputs (Cat is gooood)
207 m
.d
.comb
+= [Cat(*go_rd_i
).eq(self
.go_rd_i
),
208 Cat(*go_wr_i
).eq(self
.go_wr_i
),
209 Cat(*go_die_i
).eq(self
.go_die_i
),
210 Cat(*issue_i
).eq(self
.issue_i
),
217 yield from self
.src_i
222 yield self
.dest_rsel_o
223 yield from self
.src_rsel_o
228 yield self
.v_wr_rsel_o
229 yield self
.v_rd_rsel_o
230 yield from self
.rd_src_pend_o
235 def d_matrix_sim(dut
):
238 yield dut
.dest_i
.eq(1)
239 yield dut
.issue_i
.eq(1)
241 yield dut
.issue_i
.eq(0)
243 yield dut
.src1_i
.eq(1)
244 yield dut
.issue_i
.eq(1)
246 yield dut
.issue_i
.eq(0)
248 yield dut
.go_rd_i
.eq(1)
250 yield dut
.go_rd_i
.eq(0)
252 yield dut
.go_wr_i
.eq(1)
254 yield dut
.go_wr_i
.eq(0)
258 dut
= FURegDepMatrix(n_fu_row
=3, n_reg_col
=4, n_src
=2)
259 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
260 with
open("test_fu_reg_matrix.il", "w") as f
:
263 run_simulation(dut
, d_matrix_sim(dut
), vcd_name
='test_fu_reg_matrix.vcd')
265 if __name__
== '__main__':