5a865640cb93f8bf400f32f963a594cb48042704
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Elaboratable
6 class PriorityPicker(Elaboratable
):
7 """ implements a priority-picker. input: N bits, output: N bits
9 def __init__(self
, wid
):
12 self
.i
= Signal(wid
, reset_less
=True)
13 self
.o
= Signal(wid
, reset_less
=True)
15 def elaborate(self
, platform
):
19 ni
= Signal(self
.wid
, reset_less
= True)
20 m
.d
.comb
+= ni
.eq(~self
.i
)
21 for i
in range(0, self
.wid
):
22 t
= Signal(reset_less
= True)
25 m
.d
.comb
+= t
.eq(self
.i
[i
])
27 m
.d
.comb
+= t
.eq(~
Cat(ni
[i
], *self
.i
[:i
]).bool())
29 # we like Cat(*xxx). turn lists into concatenated bits
30 m
.d
.comb
+= self
.o
.eq(Cat(*res
))
42 class GroupPicker(Elaboratable
):
43 """ implements 10.5 mitch alsup group picker, p27
45 def __init__(self
, wid
):
48 self
.readable_i
= Signal(wid
, reset_less
=True) # readable in (top)
49 self
.writable_i
= Signal(wid
, reset_less
=True) # writable in (top)
50 self
.go_rd_i
= Signal(wid
, reset_less
=True) # go read in (top)
51 self
.req_rel_i
= Signal(wid
, reset_less
=True) # release request in (top)
54 self
.go_rd_o
= Signal(wid
, reset_less
=True) # go read (bottom)
55 self
.go_wr_o
= Signal(wid
, reset_less
=True) # go write (bottom)
57 def elaborate(self
, platform
):
60 m
.submodules
.rpick
= rpick
= PriorityPicker(self
.gp_wid
)
61 m
.submodules
.wpick
= wpick
= PriorityPicker(self
.gp_wid
)
63 # combine release (output ready signal) with writeable
64 m
.d
.comb
+= wpick
.i
.eq(self
.writable_i
& self
.req_rel_i
)
65 m
.d
.comb
+= self
.go_wr_o
.eq(wpick
.o
)
67 m
.d
.comb
+= rpick
.i
.eq(self
.readable_i
) #& self.go_rd_i)
68 m
.d
.comb
+= self
.go_rd_o
.eq(rpick
.o
)
83 def grp_pick_sim(dut
):
84 yield dut
.dest_i
.eq(1)
85 yield dut
.issue_i
.eq(1)
87 yield dut
.issue_i
.eq(0)
89 yield dut
.src1_i
.eq(1)
90 yield dut
.issue_i
.eq(1)
94 yield dut
.issue_i
.eq(0)
96 yield dut
.go_rd_i
.eq(1)
98 yield dut
.go_rd_i
.eq(0)
100 yield dut
.go_wr_i
.eq(1)
102 yield dut
.go_wr_i
.eq(0)
107 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
108 with
open("test_grp_pick.il", "w") as f
:
111 run_simulation(dut
, grp_pick_sim(dut
), vcd_name
='test_grp_pick.vcd')
113 if __name__
== '__main__':