d1f58d111420aaf681062d7a8767454d003f6683
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Array
, Const
, Record
, Elaboratable
4 from nmutil
.latch
import SRLatch
5 from nmigen
.lib
.coding
import Decoder
7 from shadow_fn
import ShadowFn
10 class IssueUnit(Elaboratable
):
11 """ implements 11.4.14 issue unit, p50
15 * :wid: register file width
16 * :n_insns: number of instructions in this issue unit.
18 def __init__(self
, wid
, n_insns
):
20 self
.n_insns
= n_insns
23 self
.store_i
= Signal(reset_less
=True) # instruction is a store
24 self
.dest_i
= Signal(max=wid
, reset_less
=True) # Dest R# in
25 self
.src1_i
= Signal(max=wid
, reset_less
=True) # oper1 R# in
26 self
.src2_i
= Signal(max=wid
, reset_less
=True) # oper2 R# in
28 self
.g_wr_pend_i
= Signal(wid
, reset_less
=True) # write pending vector
30 self
.insn_i
= Array(Signal(reset_less
=True, name
="insn_i") \
31 for i
in range(n_insns
))
32 self
.busy_i
= Array(Signal(reset_less
=True, name
="busy_i") \
33 for i
in range(n_insns
))
36 self
.fn_issue_o
= Array(Signal(reset_less
=True, name
="fn_issue_o") \
37 for i
in range(n_insns
))
38 self
.g_issue_o
= Signal(reset_less
=True)
40 def elaborate(self
, platform
):
42 m
.submodules
.dest_d
= dest_d
= Decoder(self
.reg_width
)
45 waw_stall
= Signal(reset_less
=True)
46 fu_stall
= Signal(reset_less
=True)
47 pend
= Signal(self
.reg_width
, reset_less
=True)
49 # dest decoder: write-pending
50 m
.d
.comb
+= dest_d
.i
.eq(self
.dest_i
)
51 m
.d
.comb
+= dest_d
.n
.eq(~self
.store_i
) # decode is inverted
52 m
.d
.comb
+= pend
.eq(dest_d
.o
& self
.g_wr_pend_i
)
53 m
.d
.comb
+= waw_stall
.eq(pend
.bool())
56 for i
in range(self
.n_insns
):
57 ib_l
.append(self
.insn_i
[i
] & self
.busy_i
[i
])
58 m
.d
.comb
+= fu_stall
.eq(Cat(*ib_l
).bool())
59 m
.d
.comb
+= self
.g_issue_o
.eq(~
(waw_stall | fu_stall
))
60 for i
in range(self
.n_insns
):
61 m
.d
.comb
+= self
.fn_issue_o
[i
].eq(self
.g_issue_o
& self
.insn_i
[i
])
70 yield self
.g_wr_pend_i
71 yield from self
.insn_i
72 yield from self
.busy_i
73 yield from self
.fn_issue_o
80 class IntFPIssueUnit(Elaboratable
):
81 def __init__(self
, wid
, n_int_insns
, n_fp_insns
):
82 self
.i
= IssueUnit(wid
, n_int_insns
)
83 self
.f
= IssueUnit(wid
, n_fp_insns
)
84 self
.issue_o
= Signal(reset_less
=True)
87 self
.int_write_pending_i
= self
.i
.g_wr_pend_i
88 self
.fp_write_pending_i
= self
.f
.g_wr_pend_i
89 self
.int_write_pending_i
.name
= 'int_write_pending_i'
90 self
.fp_write_pending_i
.name
= 'fp_write_pending_i'
92 def elaborate(self
, platform
):
94 m
.submodules
.intissue
= self
.i
95 m
.submodules
.fpissue
= self
.f
97 m
.d
.comb
+= self
.issue_o
.eq(self
.i
.g_issue_o | self
.f
.g_issue_o
)
107 def issue_unit_sim(dut
):
108 yield dut
.dest_i
.eq(1)
109 yield dut
.issue_i
.eq(1)
111 yield dut
.issue_i
.eq(0)
113 yield dut
.src1_i
.eq(1)
114 yield dut
.issue_i
.eq(1)
118 yield dut
.issue_i
.eq(0)
120 yield dut
.go_read_i
.eq(1)
122 yield dut
.go_read_i
.eq(0)
124 yield dut
.go_write_i
.eq(1)
126 yield dut
.go_write_i
.eq(0)
129 def test_issue_unit():
130 dut
= IssueUnit(32, 3)
131 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
132 with
open("test_issue_unit.il", "w") as f
:
135 dut
= IntFPIssueUnit(32, 3, 3)
136 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
137 with
open("test_intfp_issue_unit.il", "w") as f
:
140 run_simulation(dut
, issue_unit_sim(dut
), vcd_name
='test_issue_unit.vcd')
142 if __name__
== '__main__':