3919cce313c25527c2755f3714ec1e58b83c32e6
1 from nmigen
import Elaboratable
, Module
, Signal
, Array
4 class Reg_Rsv(Elaboratable
):
5 """ these are allocated per-Register (vertically),
6 and are each of length fu_count
8 def __init__(self
, fu_count
, n_src
):
10 self
.fu_count
= fu_count
11 self
.dest_rsel_i
= Signal(fu_count
, reset_less
=True)
12 self
.src_rsel_i
= Array(Signal(fu_count
, name
="src_rsel_i",
14 for i
in range(n_src
))
15 self
.dest_rsel_o
= Signal(reset_less
=True)
16 self
.src_rsel_o
= Signal(n_src
, reset_less
=True)
18 def elaborate(self
, platform
):
20 m
.d
.comb
+= self
.dest_rsel_o
.eq(self
.dest_rsel_i
.bool())
21 for i
in range(self
.n_src
):
22 m
.d
.comb
+= self
.src_rsel_o
[i
].eq(self
.src_rsel_i
[i
].bool())