1 // Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
2 // Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 // GSR & PUR init requires for Lattice models
21 // Generate 100 Mhz clock
38 inout wire [1:0] dram_dqs;
39 inout wire [1:0] dram_dqs_n;
44 wire [1:0] dram_tdqs_n;
48 .check_strict_timing(0)
68 assign dram_dqs_n = (dram_dqs != 2'hz) ? ~dram_dqs : 2'hz;
70 // uart, LEDs, switches
93 .ddr3_0__rst__io(dram_rst),
94 .ddr3_0__dq__io(dram_dq),
95 .ddr3_0__dqs__p(dram_dqs),
96 .ddr3_0__clk__p(dram_ck),
97 .ddr3_0__clk_en__io(dram_cke),
98 .ddr3_0__cs__io(dram_cs_n),
99 .ddr3_0__we__io(dram_we_n),
100 .ddr3_0__ras__io(dram_ras_n),
101 .ddr3_0__cas__io(dram_cas_n),
102 .ddr3_0__a__io(dram_a),
103 .ddr3_0__ba__io(dram_ba),
104 .ddr3_0__dm__io(dram_dm),
105 .ddr3_0__odt__io(dram_odt),
106 .uart_0__rx__io(uart_rx),
107 .uart_0__tx__io(uart_tx),
116 .switch_0__io(switch_0),
117 .switch_1__io(switch_1),
118 .switch_2__io(switch_2),
119 .switch_3__io(switch_3),
120 .switch_4__io(switch_4),
121 .switch_5__io(switch_5),
122 .switch_6__io(switch_6),
123 .switch_7__io(switch_7),
130 $dumpfile("simsoc.fst");
132 $dumpvars(0, dram_rst);
133 $dumpvars(0, dram_dq);
134 $dumpvars(0, dram_dqs);
135 $dumpvars(0, dram_ck);
136 $dumpvars(0, dram_cke);
137 $dumpvars(0, dram_we_n);
138 $dumpvars(0, dram_ras_n);
139 $dumpvars(0, dram_cas_n);
140 $dumpvars(0, dram_a);
141 $dumpvars(0, dram_ba);
142 $dumpvars(0, dram_dm);
143 $dumpvars(0, dram_odt);
144 $dumpvars(0, uart_tx);
145 $dumpvars(0, uart_rx);
146 $dumpvars(0, simsoctop);
147 $dumpvars(0, ram_chip);
152 // run for a set time period then exit