src/soc/alu/main_stage.py

   1 from nmigen import (Module, Signal)
   2 from nmutil.pipemodbase import PipeModBase
   3 from soc.alu.pipe_data import ALUInputData, ALUOutputData
   4 from ieee754.part.partsig import PartitionedSignal
   5 from soc.decoder.power_enums import InternalOp
   6
   7
   8 class ALUMainStage(PipeModBase):
   9     def __init__(self, pspec):
  10         super().__init__(pspec, "main")
  11
  12     def ispec(self):
  13         return ALUInputData(self.pspec)
  14
  15     def ospec(self):
  16         return ALUOutputData(self.pspec)
  17
  18     def elaborate(self, platform):
  19         m = Module()
  20         comb = m.d.comb
  21
  22         add_output = Signal(self.i.a.width + 1, reset_less=True)
  23         comb += add_output.eq(self.i.a + self.i.b)
  24
  25
  26         with m.Switch(self.i.ctx.op.insn_type):
  27             with m.Case(InternalOp.OP_ADD):
  28                 comb += self.o.o.eq(add_output[0:64])
  29
  30         comb += self.o.ctx.eq(self.i.ctx)
  31
  32         return m