src/soc/clock/dummypll.py

   1 """a Dummy PLL module to be replaced by a real one
   2 """
   3
   4 from nmigen import (Module, Signal, Elaboratable, Const, Cat, Instance)
   5 from nmigen.cli import rtlil
   6
   7 class DummyPLL(Elaboratable):
   8     def __init__(self, instance):
   9         self.instance = instance
  10         self.clk_24_i = Signal(reset_less=True) # external incoming
  11         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
  12         self.sel_a1_i = Signal(reset_less=True) # PLL selection
  13         self.clk_pll_o = Signal(reset_less=True)  # output clock
  14         self.pll_test_o = Signal(reset_less=True)  # test out
  15         self.pll_vco_o = Signal(reset_less=True) # analog
  16
  17     def elaborate(self, platform):
  18         m = Module()
  19
  20         if self.instance:
  21             pll = Instance("pll", i_ref=self.clk_24_i,
  22                                   i_a0=self.clk_sel_i[0],
  23                                   i_a1=self.clk_sel_i[1],
  24                                   o_out_v=self.clk_pll_o,
  25                                   o_div_out_test=self.pll_test_o,
  26                                   o_vco_test_ana=self.pll_vco_o,
  27                            )
  28             m.submodules['real_pll'] = pll
  29             #pll.attrs['blackbox'] = 1
  30         else:
  31             m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
  32             # just get something, stops yosys destroying (optimising) these out
  33             with m.If(self.clk_sel_i == 0):
  34                 m.d.comb += self.pll_test_o.eq(self.clk_24_i)
  35                 m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
  36
  37
  38         return m
  39
  40     def ports(self):
  41         return [self.clk_24_i, self.clk_sel_i, self.clk_pll_o,
  42                 self.pll_test_o, self.pll_vco_o]
  43
  44
  45 if __name__ == '__main__':
  46     dut = DummyPLL()
  47
  48     vl = rtlil.convert(dut, ports=dut.ports())
  49     with open("test_dummy_pll.il", "w") as f:
  50         f.write(vl)
  51