src/soc/cr/main_stage.py

   1 # This stage is intended to do Condition Register instructions
   2 # and output, as well as carry and overflow generation.
   3 # NOTE: with the exception of mtcrf and mfcr, we really should be doing
   4 # the field decoding which
   5 # selects which bits of CR are to be read / written, back in the
   6 # decoder / insn-isue, have both self.i.cr and self.o.cr
   7 # be broken down into 4-bit-wide "registers", with their
   8 # own "Register File" (indexed by bt, ba and bb),
   9 # exactly how INT regs are done (by RA, RB, RS and RT)
  10 # however we are pushed for time so do it as *one* register.
  11
  12 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
  13 from nmutil.pipemodbase import PipeModBase
  14 from soc.cr.pipe_data import CRInputData, CROutputData
  15 from soc.decoder.power_enums import InternalOp
  16
  17 from soc.decoder.power_fields import DecodeFields
  18 from soc.decoder.power_fieldsn import SignalBitRange
  19
  20
  21 class CRMainStage(PipeModBase):
  22     def __init__(self, pspec):
  23         super().__init__(pspec, "main")
  24         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  25         self.fields.create_specs()
  26
  27     def ispec(self):
  28         return CRInputData(self.pspec)
  29
  30     def ospec(self):
  31         return CROutputData(self.pspec)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35         comb = m.d.comb
  36         op = self.i.ctx.op
  37         xl_fields = self.fields.FormXL
  38         xfx_fields = self.fields.FormXFX
  39
  40         # default: cr_o remains same as cr input unless modified, below
  41         cr_o = Signal.like(self.i.cr)
  42         comb += cr_o.eq(self.i.cr)
  43
  44         ##### prepare inputs / temp #####
  45
  46         # Generate array for cr input so bits can be selected
  47         cr_arr = Array([Signal(name=f"cr_arr_{i}") for i in range(32)])
  48         for i in range(32):
  49             comb += cr_arr[i].eq(self.i.cr[31-i])
  50
  51         # Generate array for cr output so the bit to write to can be
  52         # selected by a signal
  53         cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])
  54         for i in range(32):
  55             comb += cr_o[31-i].eq(cr_out_arr[i])
  56             comb += cr_out_arr[i].eq(cr_arr[i])
  57
  58         # Ugh. mtocrf and mtcrf have one random bit differentiating
  59         # them. This bit is not in any particular field, so this
  60         # extracts that bit from the instruction
  61         move_one = Signal(reset_less=True)
  62         comb += move_one.eq(self.i.ctx.op.insn[20])
  63
  64         # crand/cror and friends get decoded to the same opcode, but
  65         # one of the fields inside the instruction is a 4 bit lookup
  66         # table. This lookup table gets indexed by bits a and b from
  67         # the CR to determine what the resulting bit should be.
  68
  69         # Grab the lookup table for cr_op type instructions
  70         lut = Array([Signal(name=f"lut{i}") for i in range(4)])
  71         # There's no field, just have to grab it directly from the insn
  72         for i in range(4):
  73             comb += lut[i].eq(self.i.ctx.op.insn[6+i])
  74
  75         # Generate the mask for mtcrf, mtocrf, and mfocrf
  76         fxm = Signal(xfx_fields.FXM[0:-1].shape())
  77         comb += fxm.eq(xfx_fields.FXM[0:-1])
  78
  79         # replicate every fxm field in the insn to 4-bit, as a mask
  80         mask = Signal(32, reset_less=True)
  81         comb += mask.eq(Cat(*[Repl(fxm[i], 4) for i in range(8)]))
  82
  83         #################################
  84         ##### main switch statement #####
  85
  86         with m.Switch(op.insn_type):
  87             ##### mcrf #####
  88             with m.Case(InternalOp.OP_MCRF):
  89                 # MCRF copies the 4 bits of crA to crB (for instance
  90                 # copying cr2 to cr1)
  91
  92                 # The destination CR
  93                 print ("xl", xl_fields)
  94                 bf = Signal(xl_fields.BF[0:-1].shape())
  95                 comb += bf.eq(xl_fields.BF[0:-1])
  96                 # the source CR
  97                 bfa = Signal(xl_fields.BFA[0:-1].shape())
  98                 comb += bfa.eq(xl_fields.BFA[0:-1])
  99
 100                 for i in range(4):
 101                     comb += cr_out_arr[bf*4 + i].eq(cr_arr[bfa*4 + i])
 102
 103             ##### crand, cror, crnor etc. #####
 104             with m.Case(InternalOp.OP_CROP):
 105                 # Get the bit selector fields from the instruction
 106                 bt = Signal(xl_fields.BT[0:-1].shape())
 107                 ba = Signal(xl_fields.BA[0:-1].shape())
 108                 bb = Signal(xl_fields.BB[0:-1].shape())
 109                 comb += bt.eq(xl_fields.BT[0:-1])
 110                 comb += ba.eq(xl_fields.BA[0:-1])
 111                 comb += bb.eq(xl_fields.BB[0:-1])
 112
 113                 # Use the two input bits to look up the result in the LUT
 114                 comb += cr_out_arr[bt].eq(lut[Cat(cr_arr[bb], cr_arr[ba])])
 115
 116             ##### mtcrf #####
 117             with m.Case(InternalOp.OP_MTCRF):
 118                 # mtocrf and mtcrf are essentially identical
 119                 # put input (RA) - mask-selected - into output CR, leave
 120                 # rest of CR alone.
 121                 comb += cr_o.eq((self.i.a[0:32] & mask) | (self.i.cr & ~mask))
 122
 123             ##### mfcr #####
 124             with m.Case(InternalOp.OP_MFCR):
 125                 # mfocrf
 126                 with m.If(move_one):
 127                     comb += self.o.o.eq(self.i.cr & mask)
 128                 # mfcrf
 129                 with m.Else():
 130                     comb += self.o.o.eq(self.i.cr)
 131
 132         # output and context
 133         comb += self.o.cr.eq(cr_o)
 134         comb += self.o.ctx.eq(self.i.ctx)
 135
 136         return m