fa08fb66a2613c494bda4715fd5d77c8290f2e31
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.cr
.pipeline
import CRBasePipe
16 from soc
.alu
.alu_input_record
import CompALUOpSubset
17 from soc
.alu
.pipe_data
import ALUPipeSpec
22 def __init__(self
, program
, regs
, sprs
, cr
, name
):
23 self
.program
= program
29 def get_rec_width(rec
):
31 # Setup random inputs for dut.op
38 # This test bench is a bit different than is usual. Initially when I
39 # was writing it, I had all of the tests call a function to create a
40 # device under test and simulator, initialize the dut, run the
41 # simulation for ~2 cycles, and assert that the dut output what it
42 # should have. However, this was really slow, since it needed to
43 # create and tear down the dut and simulator for every test case.
45 # Now, instead of doing that, every test case in ALUTestCase puts some
46 # data into the test_data list below, describing the instructions to
47 # be tested and the initial state. Once all the tests have been run,
48 # test_data gets passed to TestRunner which then sets up the DUT and
49 # simulator once, runs all the data through it, and asserts that the
50 # results match the pseudocode sim at every cycle.
52 # By doing this, I've reduced the time it takes to run the test suite
53 # massively. Before, it took around 1 minute on my computer, now it
54 # takes around 3 seconds
59 class CRTestCase(FHDLTestCase
):
60 def __init__(self
, name
):
61 super().__init
__(name
)
63 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_sprs
={},
65 tc
= TestCase(prog
, initial_regs
, initial_sprs
, initial_cr
,
70 insns
= ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
73 choice
= random
.choice(insns
)
74 ba
= random
.randint(0, 31)
75 bb
= random
.randint(0, 31)
76 bt
= random
.randint(0, 31)
77 lst
= [f
"{choice} {ba}, {bb}, {bt}"]
78 cr
= random
.randint(0, 7)
79 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
84 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
88 mask
= random
.randint(0, 255)
89 lst
= [f
"mtcrf {mask}, 2"]
90 cr
= random
.randint(0, (1<<32)-1)
91 initial_regs
= [0] * 32
92 initial_regs
[2] = random
.randint(0, (1<<32)-1)
93 self
.run_tst_program(Program(lst
), initial_regs
=initial_regs
,
95 def test_mtocrf(self
):
97 mask
= 1<<random
.randint(0, 7)
98 lst
= [f
"mtocrf {mask}, 2"]
99 cr
= random
.randint(0, (1<<32)-1)
100 initial_regs
= [0] * 32
101 initial_regs
[2] = random
.randint(0, (1<<32)-1)
102 self
.run_tst_program(Program(lst
), initial_regs
=initial_regs
,
108 cr
= random
.randint(0, (1<<32)-1)
109 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
111 def test_mfocrf(self
):
113 mask
= 1<<random
.randint(0, 7)
114 lst
= [f
"mfocrf 2, {mask}"]
115 cr
= random
.randint(0, (1<<32)-1)
116 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
119 def test_ilang(self
):
120 rec
= CompALUOpSubset()
122 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
123 alu
= CRBasePipe(pspec
)
125 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
126 with
open("logical_pipeline.il", "w") as f
:
130 class TestRunner(FHDLTestCase
):
131 def __init__(self
, test_data
):
132 super().__init
__("run_all")
133 self
.test_data
= test_data
135 def set_inputs(self
, alu
, dec2
, simulator
):
136 yield alu
.p
.data_i
.cr
.eq(simulator
.cr
.get_range().value
)
138 reg3_ok
= yield dec2
.e
.read_reg3
.ok
140 reg3_sel
= yield dec2
.e
.read_reg3
.data
141 reg3
= simulator
.gpr(reg3_sel
).value
142 yield alu
.p
.data_i
.a
.eq(reg3
)
147 instruction
= Signal(32)
149 pdecode
= create_pdecode()
151 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
153 rec
= CompALUOpSubset()
155 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
156 m
.submodules
.alu
= alu
= CRBasePipe(pspec
)
158 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
159 comb
+= alu
.p
.valid_i
.eq(1)
160 comb
+= alu
.n
.ready_i
.eq(1)
161 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
166 for test
in self
.test_data
:
168 program
= test
.program
169 self
.subTest(test
.name
)
170 simulator
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
)
171 gen
= program
.generate_instructions()
172 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
174 index
= simulator
.pc
.CIA
.value
//4
175 while index
< len(instructions
):
176 ins
, code
= instructions
[index
]
178 print("0x{:X}".format(ins
& 0xffffffff))
181 # ask the decoder to decode this binary data (endian'd)
182 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
183 yield instruction
.eq(ins
) # raw binary instr.
185 yield from self
.set_inputs(alu
, pdecode2
, simulator
)
186 fn_unit
= yield pdecode2
.e
.fn_unit
187 self
.assertEqual(fn_unit
, Function
.CR
.value
, code
)
189 opname
= code
.split(' ')[0]
190 yield from simulator
.call(opname
)
191 index
= simulator
.pc
.CIA
.value
//4
193 vld
= yield alu
.n
.valid_o
196 vld
= yield alu
.n
.valid_o
198 cr_out
= yield pdecode2
.e
.output_cr
200 cr_expected
= simulator
.cr
.get_range().value
201 cr_real
= yield alu
.n
.data_o
.cr
202 msg
= f
"real: {cr_expected:x}, actual: {cr_real:x}"
203 msg
+= " code: %s" % code
204 self
.assertEqual(cr_expected
, cr_real
, msg
)
206 reg_out
= yield pdecode2
.e
.write_reg
.ok
208 reg_sel
= yield pdecode2
.e
.write_reg
.data
209 reg_data
= simulator
.gpr(reg_sel
).value
210 output
= yield alu
.n
.data_o
.o
211 msg
= f
"real: {reg_data:x}, actual: {output:x}"
212 self
.assertEqual(reg_data
, output
)
214 sim
.add_sync_process(process
)
215 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
218 def check_extra_alu_outputs(self
, alu
, dec2
, sim
):
219 rc
= yield dec2
.e
.rc
.data
221 cr_expected
= sim
.crl
[0].get_range().value
222 cr_actual
= yield alu
.n
.data_o
.cr0
223 self
.assertEqual(cr_expected
, cr_actual
)
226 if __name__
== "__main__":
227 unittest
.main(exit
=False)
228 suite
= unittest
.TestSuite()
229 suite
.addTest(TestRunner(test_data
))
231 runner
= unittest
.TextTestRunner()