c2a6f0958a86ce1f94ec6a539e9ca08f3b16b8ba
3 using Staf Verhaegen (Chips4Makers) wishbone TAP
6 from collections
import OrderedDict
7 from nmigen
import (Module
, Signal
, Elaboratable
, Cat
)
8 from nmigen
.cli
import rtlil
9 from c4m
.nmigen
.jtag
.tap
import IOType
10 from soc
.debug
.dmi
import DMIInterface
, DBGCore
11 from soc
.debug
.dmi2jtag
import DMITAP
13 # map from pinmux to c4m jtag iotypes
14 iotypes
= {'-': IOType
.In
,
20 scanlens
= {IOType
.In
: 1,
27 # sigh this needs to come from pinmux.
30 gpios
.append("%d*" % i
)
31 return {'uart': ['tx+', 'rx-'],
33 'i2c': ['sda*', 'scl+']}
35 # TODO: move to suitable location
37 """declare a list of pins, including name and direction. grouped by fn
38 the pin dictionary needs to be in a reliable order so that the JTAG
39 Boundary Scan is also in a reliable order
41 def __init__(self
, pindict
):
42 self
.io_names
= OrderedDict()
43 if isinstance(pindict
, OrderedDict
):
44 self
.io_names
.update(pindict
)
46 keys
= list(pindict
.keys())
49 self
.io_names
[k
] = pindict
[k
]
52 # start parsing io_names and enumerate them to return pin specs
54 for fn
, pins
in self
.io_names
.items():
56 # decode the pin name and determine the c4m jtag io type
57 name
, pin_type
= pin
[:-1], pin
[-1]
58 iotype
= iotypes
[pin_type
]
59 pin_name
= "%s_%s" % (fn
, name
)
60 yield (fn
, name
, iotype
, pin_name
, scan_idx
)
61 scan_idx
+= scanlens
[iotype
] # inc boundary reg scan offset
64 class JTAG(DMITAP
, Pins
):
65 def __init__(self
, pinset
, wb_data_wid
=64):
66 DMITAP
.__init
__(self
, ir_width
=4)
67 Pins
.__init
__(self
, pinset
)
69 # enumerate pin specs and create IOConn Records.
70 # we store the boundary scan register offset in the IOConn record
71 self
.ios
= [] # these are enumerated in external_ports
73 for fn
, pin
, iotype
, pin_name
, scan_idx
in list(self
):
74 io
= self
.add_io(iotype
=iotype
, name
=pin_name
)
75 io
._scan
_idx
= scan_idx
# hmm shouldn't really do this
76 self
.scan_len
+= scan_idx
# record full length of boundary scan
79 # this is redundant. or maybe part of testing, i don't know.
80 self
.sr
= self
.add_shiftreg(ircode
=4, length
=3)
82 # create and connect wishbone
83 self
.wb
= self
.add_wishbone(ircodes
=[5, 6, 7], features
={'err'},
84 address_width
=29, data_width
=wb_data_wid
,
85 granularity
=8, # 8-bit wide
88 # create DMI2JTAG (goes through to dmi_sim())
89 self
.dmi
= self
.add_dmi(ircodes
=[8, 9, 10])
91 # use this for enable/disable of parts of the ASIC.
92 # NOTE: increase length parameter when adding new enable signals
93 self
.sr_en
= self
.add_shiftreg(ircode
=11, length
=3)
94 self
.wb_icache_en
= Signal(reset
=1)
95 self
.wb_dcache_en
= Signal(reset
=1)
96 self
.wb_sram_en
= Signal(reset
=1)
98 def elaborate(self
, platform
):
99 m
= super().elaborate(platform
)
100 m
.d
.comb
+= self
.sr
.i
.eq(self
.sr
.o
) # loopback as part of test?
102 # provide way to enable/disable wishbone caches and SRAM
103 # just in case of issues
104 # see https://bugs.libre-soc.org/show_bug.cgi?id=520
105 en_sigs
= Cat(self
.wb_icache_en
, self
.wb_dcache_en
,
107 with m
.If(self
.sr_en
.oe
):
108 m
.d
.sync
+= en_sigs
.eq(self
.sr_en
.o
)
109 # also make it possible to read the enable/disable current state
110 with m
.If(self
.sr_en
.ie
):
111 m
.d
.comb
+= self
.sr_en
.i
.eq(en_sigs
)
115 def external_ports(self
):
116 """create a list of ports that goes into the top level il (or verilog)
118 ports
= super().external_ports() # gets JTAG signal names
119 ports
+= list(self
.wb
.fields
.values()) # wishbone signals
121 ports
+= list(io
.core
.fields
.values()) # io "core" signals
122 ports
+= list(io
.pad
.fields
.values()) # io "pad" signals"
126 if __name__
== '__main__':
127 pinset
= dummy_pinset()
130 vl
= rtlil
.convert(dut
)
131 with
open("test_jtag.il", "w") as f
: