d36ec447dadb966a004bc628b21ba82538ed0427
1 from nmigen
import Module
, Signal
, Elaboratable
, Cat
, Repl
2 from nmigen
.asserts
import Assert
, AnyConst
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import create_pdecode
, PowerOp
6 from soc
.decoder
.power_enums
import (In1Sel
, In2Sel
, In3Sel
,
9 from soc
.decoder
.power_decoder2
import (PowerDecode2
,
10 Decode2ToExecute1Type
)
13 class Driver(Elaboratable
):
17 self
.instruction
= None
19 def elaborate(self
, platform
):
21 self
.comb
= self
.m
.d
.comb
22 self
.instruction
= Signal(32)
24 self
.comb
+= self
.instruction
.eq(AnyConst(32))
26 pdecode
= create_pdecode()
28 self
.m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
29 self
.comb
+= pdecode2
.dec
.bigendian
.eq(1) # XXX TODO: bigendian=0
30 self
.comb
+= pdecode2
.dec
.raw_opcode_in
.eq(self
.instruction
)
32 self
.test_in1(pdecode2
, pdecode
)
34 self
.test_in2_fields()
38 self
.test_single_bits()
42 def test_in1(self
, pdecode2
, pdecode
):
45 ra
= self
.instr_bits(11, 15)
46 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA
):
47 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
48 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
49 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA_OR_ZERO
):
51 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 0)
53 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
54 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
55 op
= pdecode
.op
.internal_op
56 with m
.If((op
== InternalOp
.OP_BC
) |
57 (op
== InternalOp
.OP_BCREG
)):
58 with m
.If(~self
.instr_bits(8)):
59 comb
+= Assert(pdecode2
.e
.read_spr1
.data
== SPR
.CTR
)
60 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
61 with m
.If((op
== InternalOp
.OP_MFSPR
) |
62 (op
== InternalOp
.OP_MTSPR
)):
63 comb
+= Assert(pdecode2
.e
.read_spr1
.data
==
64 self
.instr_bits(11, 20))
65 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
70 pdecode2
= m
.submodules
.pdecode2
72 with m
.If(dec
.op
.in2_sel
== In2Sel
.RB
):
73 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 1)
74 comb
+= Assert(pdecode2
.e
.read_reg2
.data
==
76 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.NONE
):
77 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
78 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
79 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.SPR
):
80 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
81 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
82 comb
+= Assert(pdecode2
.e
.read_spr2
.ok
== 1)
83 with m
.If(dec
.fields
.FormXL
.XO
[9]):
84 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.CTR
)
86 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.LR
)
88 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 1)
89 with m
.Switch(dec
.op
.in2_sel
):
90 with m
.Case(In2Sel
.CONST_UI
):
91 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.UI
)
92 with m
.Case(In2Sel
.CONST_SI
):
93 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
94 self
.exts(dec
.SI
, 16, 64))
95 with m
.Case(In2Sel
.CONST_UI_HI
):
96 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
98 with m
.Case(In2Sel
.CONST_SI_HI
):
99 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
100 self
.exts(dec
.SI
<< 16, 32, 64))
101 with m
.Case(In2Sel
.CONST_LI
):
102 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
104 with m
.Case(In2Sel
.CONST_BD
):
105 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
107 with m
.Case(In2Sel
.CONST_DS
):
108 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
110 with m
.Case(In2Sel
.CONST_M1
):
111 comb
+= Assert(pdecode2
.e
.imm_data
.data
== ~
0)
112 with m
.Case(In2Sel
.CONST_SH
):
113 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.sh
)
114 with m
.Case(In2Sel
.CONST_SH32
):
115 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.SH32
)
119 def exts(self
, exts_data
, width
, fullwidth
):
120 exts_data
= exts_data
[0:width
]
121 topbit
= exts_data
[-1]
122 signbits
= Repl(topbit
, fullwidth
-width
)
123 return Cat(exts_data
, signbits
)
125 def test_in2_fields(self
):
128 dec
= m
.submodules
.pdecode2
.dec
130 comb
+= Assert(dec
.RB
== self
.instr_bits(16, 20))
131 comb
+= Assert(dec
.UI
== self
.instr_bits(16, 31))
132 comb
+= Assert(dec
.SI
== self
.instr_bits(16, 31))
133 comb
+= Assert(dec
.LI
== self
.instr_bits(6, 29))
134 comb
+= Assert(dec
.BD
== self
.instr_bits(16, 29))
135 comb
+= Assert(dec
.DS
== self
.instr_bits(16, 29))
136 comb
+= Assert(dec
.sh
== Cat(self
.instr_bits(16, 20),
137 self
.instr_bits(30)))
138 comb
+= Assert(dec
.SH32
== self
.instr_bits(16, 20))
143 pdecode2
= m
.submodules
.pdecode2
144 with m
.If(pdecode2
.dec
.op
.in3_sel
== In3Sel
.RS
):
145 comb
+= Assert(pdecode2
.e
.read_reg3
.ok
== 1)
146 comb
+= Assert(pdecode2
.e
.read_reg3
.data
==
147 self
.instr_bits(6,10))
152 pdecode2
= m
.submodules
.pdecode2
153 sel
= pdecode2
.dec
.op
.out_sel
155 with m
.If(sel
== OutSel
.SPR
):
156 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 1)
157 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
158 with m
.Elif(sel
== OutSel
.NONE
):
159 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
160 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
162 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
163 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 1)
164 data
= pdecode2
.e
.write_reg
.data
165 with m
.If(sel
== OutSel
.RT
):
166 comb
+= Assert(data
== self
.instr_bits(6, 10))
167 with m
.If(sel
== OutSel
.RA
):
168 comb
+= Assert(data
==
169 self
.instr_bits(11, 15))
174 pdecode2
= m
.submodules
.pdecode2
175 sel
= pdecode2
.dec
.op
.rc_sel
177 comb
+= Assert(pdecode2
.e
.rc
.ok
== 1)
178 with m
.If(sel
== RC
.NONE
):
179 comb
+= Assert(pdecode2
.e
.rc
.data
== 0)
180 with m
.If(sel
== RC
.ONE
):
181 comb
+= Assert(pdecode2
.e
.rc
.data
== 1)
182 with m
.If(sel
== RC
.RC
):
183 comb
+= Assert(pdecode2
.e
.rc
.data
==
185 comb
+= Assert(pdecode2
.e
.oe
.ok
== 1)
186 comb
+= Assert(pdecode2
.e
.oe
.data
==
189 def test_single_bits(self
):
192 pdecode2
= m
.submodules
.pdecode2
195 comb
+= Assert(e
.invert_a
== dec
.op
.inv_a
)
196 comb
+= Assert(e
.invert_out
== dec
.op
.inv_out
)
197 comb
+= Assert(e
.input_carry
== dec
.op
.cry_in
)
198 comb
+= Assert(e
.output_carry
== dec
.op
.cry_out
)
199 comb
+= Assert(e
.is_32bit
== dec
.op
.is_32b
)
200 comb
+= Assert(e
.is_signed
== dec
.op
.sgn
)
201 with m
.If(dec
.op
.lk
):
202 comb
+= Assert(e
.lk
== self
.instr_bits(31))
203 comb
+= Assert(e
.byte_reverse
== dec
.op
.br
)
204 comb
+= Assert(e
.sign_extend
== dec
.op
.sgn_ext
)
205 comb
+= Assert(e
.update
== dec
.op
.upd
)
206 comb
+= Assert(e
.input_cr
== dec
.op
.cr_in
)
207 comb
+= Assert(e
.output_cr
== dec
.op
.cr_out
)
209 def instr_bits(self
, start
, end
=None):
212 return self
.instruction
[::-1][start
:end
+1][::-1]
215 class Decoder2TestCase(FHDLTestCase
):
216 def test_decoder2(self
):
218 self
.assertFormal(module
, mode
="bmc", depth
=4)
220 if __name__
== '__main__':