projects / soc.git / blob
? search:


34e5d4bbd8f362e57b358c41adf1ee0efbf153c7
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
35 # MSB is indexed **LOWEST** (sigh)
36 # from gem5 radixwalk.hh
37 # Bitfield<63> valid; 64 - (63 + 1) = 0
38 # Bitfield<62> leaf; 64 - (62 + 1) = 1
39
40 def rpte_valid(r):
41 return bool(r[0])
42
43 def rpte_leaf(r):
44 return bool(r[1])
45
46 """
47 Get Root Page
48
49 //Accessing 2nd double word of partition table (pate1)
50 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
51 // PTCR Layout
52 // ====================================================
53 // -----------------------------------------------
54 // | /// | PATB | /// | PATS |
55 // -----------------------------------------------
56 // 0 4 51 52 58 59 63
57 // PATB[4:51] holds the base address of the Partition Table,
58 // right shifted by 12 bits.
59 // This is because the address of the Partition base is
60 // 4k aligned. Hence, the lower 12bits, which are always
61 // 0 are ommitted from the PTCR.
62 //
63 // Thus, The Partition Table Base is obtained by (PATB << 12)
64 //
65 // PATS represents the partition table size right-shifted by 12 bits.
66 // The minimal size of the partition table is 4k.
67 // Thus partition table size = (1 << PATS + 12).
68 //
69 // Partition Table
70 // ====================================================
71 // 0 PATE0 63 PATE1 127
72 // |----------------------|----------------------|
73 // | | |
74 // |----------------------|----------------------|
75 // | | |
76 // |----------------------|----------------------|
77 // | | | <-- effLPID
78 // |----------------------|----------------------|
79 // .
80 // .
81 // .
82 // |----------------------|----------------------|
83 // | | |
84 // |----------------------|----------------------|
85 //
86 // The effective LPID forms the index into the Partition Table.
87 //
88 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
89 // corresponding to that partition.
90 //
91 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
92 //
93 // PATE0 Layout
94 // -----------------------------------------------
95 // |1|RTS1|/| RPDB | RTS2 | RPDS |
96 // -----------------------------------------------
97 // 0 1 2 3 4 55 56 58 59 63
98 //
99 // HR[0] : For Radix Page table, first bit should be 1.
100 // RTS1[1:2] : Gives one fragment of the Radix treesize
101 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
102 // RTS = (RTS1 << 3 + RTS2) + 31.
103 //
104 // RPDB[4:55] = Root Page Directory Base.
105 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
106 // Thus, Root page directory size = 1 << (RPDS + 3).
107 // Note: RPDS >= 5.
108 //
109 // PATE1 Layout
110 // -----------------------------------------------
111 // |///| PRTB | // | PRTS |
112 // -----------------------------------------------
113 // 0 3 4 51 52 58 59 63
114 //
115 // PRTB[4:51] = Process Table Base. This is aligned to size.
116 // PRTS[59: 63] = Process Table Size right shifted by 12.
117 // Minimal size of the process table is 4k.
118 // Process Table Size = (1 << PRTS + 12).
119 // Note: PRTS <= 24.
120 //
121 // Computing the size aligned Process Table Base:
122 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
123 // Thus, the lower 12+PRTS bits of table_base will
124 // be zero.
125
126
127 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
128 //
129 // Process Table
130 // ==========================
131 // 0 PRTE0 63 PRTE1 127
132 // |----------------------|----------------------|
133 // | | |
134 // |----------------------|----------------------|
135 // | | |
136 // |----------------------|----------------------|
137 // | | | <-- effPID
138 // |----------------------|----------------------|
139 // .
140 // .
141 // .
142 // |----------------------|----------------------|
143 // | | |
144 // |----------------------|----------------------|
145 //
146 // The effective Process id (PID) forms the index into the Process Table.
147 //
148 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
149 // corresponding to that process
150 //
151 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
152 //
153 // PRTE0 Layout
154 // -----------------------------------------------
155 // |/|RTS1|/| RPDB | RTS2 | RPDS |
156 // -----------------------------------------------
157 // 0 1 2 3 4 55 56 58 59 63
158 //
159 // RTS1[1:2] : Gives one fragment of the Radix treesize
160 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
161 // RTS = (RTS1 << 3 + RTS2) << 31,
162 // since minimal Radix Tree size is 4G.
163 //
164 // RPDB = Root Page Directory Base.
165 // RPDS = Root Page Directory Size right shifted by 3.
166 // Thus, Root page directory size = RPDS << 3.
167 // Note: RPDS >= 5.
168 //
169 // PRTE1 Layout
170 // -----------------------------------------------
171 // | /// |
172 // -----------------------------------------------
173 // 0 63
174 // All bits are reserved.
175
176
177 """
178
179 # see qemu/target/ppc/mmu-radix64.c for reference
180 class RADIX:
181 def __init__(self, mem, caller):
182 self.mem = mem
183 self.caller = caller
184 #TODO move to lookup
185 self.dsisr = self.caller.spr["DSISR"]
186 self.dar = self.caller.spr["DAR"]
187 self.pidr = self.caller.spr["PIDR"]
188 self.prtbl = self.caller.spr["PRTBL"]
189
190 # cached page table stuff
191 self.pgtbl0 = 0
192 self.pt0_valid = False
193 self.pgtbl3 = 0
194 self.pt3_valid = False
195
196 def __call__(self, addr, sz):
197 val = self.ld(addr.value, sz, swap=False)
198 print("RADIX memread", addr, sz, val)
199 return SelectableInt(val, sz*8)
200
201 def ld(self, address, width=8, swap=True, check_in_mem=False):
202 print("RADIX: ld from addr 0x%x width %d" % (address, width))
203
204 mode = 'LOAD' # XXX TODO: executable load (icache)
205 addr = SelectableInt(address, 64)
206 (shift, mbits, pgbase) = self._decode_prte(addr)
207 #shift = SelectableInt(0, 32)
208
209 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
210 # use pte to caclculate phys address
211 return self.mem.ld(address, width, swap, check_in_mem)
212
213 # XXX set SPRs on error
214
215 # TODO implement
216 def st(self, address, v, width=8, swap=True):
217 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
218
219 mode = 'STORE'
220 addr = SelectableInt(address, 64)
221 (shift, mbits, pgbase) = self._decode_prte(addr)
222 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
223
224 # use pte to caclculate phys address (addr)
225 return self.mem.st(addr.value, v, width, swap)
226
227 # XXX set SPRs on error
228
229 def memassign(self, addr, sz, val):
230 print("memassign", addr, sz, val)
231 self.st(addr.value, val.value, sz, swap=False)
232
233 def _next_level(self):
234 return True
235 ## DSISR_R_BADCONFIG
236 ## read_entry
237 ## DSISR_NOPTE
238 ## Prepare for next iteration
239
240 def _walk_tree(self, addr, pgbase, mode, mbits, shift):
241 """walk tree
242
243 // vaddr 64 Bit
244 // vaddr |-----------------------------------------------------|
245 // | Unused | Used |
246 // |-----------|-----------------------------------------|
247 // | 0000000 | usefulBits = X bits (typically 52) |
248 // |-----------|-----------------------------------------|
249 // | |<--Cursize---->| |
250 // | | Index | |
251 // | | into Page | |
252 // | | Directory | |
253 // |-----------------------------------------------------|
254 // | |
255 // V |
256 // PDE |---------------------------| |
257 // |V|L|//| NLB |///|NLS| |
258 // |---------------------------| |
259 // PDE = Page Directory Entry |
260 // [0] = V = Valid Bit |
261 // [1] = L = Leaf bit. If 0, then |
262 // [4:55] = NLB = Next Level Base |
263 // right shifted by 8 |
264 // [59:63] = NLS = Next Level Size |
265 // | NLS >= 5 |
266 // | V
267 // | |--------------------------|
268 // | | usfulBits = X-Cursize |
269 // | |--------------------------|
270 // |---------------------><--NLS-->| |
271 // | Index | |
272 // | into | |
273 // | PDE | |
274 // |--------------------------|
275 // |
276 // If the next PDE obtained by |
277 // (NLB << 8 + 8 * index) is a |
278 // nonleaf, then repeat the above. |
279 // |
280 // If the next PDE is a leaf, |
281 // then Leaf PDE structure is as |
282 // follows |
283 // |
284 // |
285 // Leaf PDE |
286 // |------------------------------| |----------------|
287 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
288 // |------------------------------| |----------------|
289 // [0] = V = Valid Bit |
290 // [1] = L = Leaf Bit = 1 if leaf |
291 // PDE |
292 // [2] = Sw = Sw bit 0. |
293 // [7:51] = RPN = Real Page Number, V
294 // real_page = RPN << 12 -------------> Logical OR
295 // [52:54] = Sw Bits 1:3 |
296 // [55] = R = Reference |
297 // [56] = C = Change V
298 // [58:59] = Att = Physical Address
299 // 0b00 = Normal Memory
300 // 0b01 = SAO
301 // 0b10 = Non Idenmpotent
302 // 0b11 = Tolerant I/O
303 // [60:63] = Encoded Access
304 // Authority
305 //
306 """
307 # get sprs
308 print("_walk_tree")
309 pidr = self.caller.spr["PIDR"]
310 prtbl = self.caller.spr["PRTBL"]
311 print(pidr)
312 print(prtbl)
313
314 # get address of root entry
315 prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
316 print("prtable_addr",prtable_addr)
317
318 # read root entry - imcomplete
319 swap = False
320 check_in_mem = False
321 entry_width = 8
322 value = self.mem.ld(prtable_addr.value, entry_width, swap, check_in_mem)
323 print("value",value)
324
325
326 # walk tree starts on prtbl
327 while True:
328 ret = self._next_level()
329 if ret: return ret
330 # TODO fix AttributeError: 'RADIX' object has no attribute 'pid'
331
332 def _decode_prte(self, data):
333 """PRTE0 Layout
334 -----------------------------------------------
335 |/|RTS1|/| RPDB | RTS2 | RPDS |
336 -----------------------------------------------
337 0 1 2 3 4 55 56 58 59 63
338 """
339 # note that SelectableInt does big-endian! so the indices
340 # below *directly* match the spec, unlike microwatt which
341 # has to turn them around (to LE)
342 zero = SelectableInt(0, 1)
343 rts = selectconcat(zero,
344 data[56:59], # RTS2
345 data[1:3], # RTS1
346 )
347 masksize = data[59:64] # RPDS
348 mbits = selectconcat(zero, masksize)
349 pgbase = selectconcat(data[8:56], # part of RPDB
350 SelectableInt(0, 16),)
351
352 return (rts, mbits, pgbase)
353
354 def _segment_check(self, addr, mbits, shift):
355 """checks segment valid
356 mbits := '0' & r.mask_size;
357 v.shift := r.shift + (31 - 12) - mbits;
358 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
359 if r.addr(63) /= r.addr(62) or nonzero = '1' then
360 v.state := RADIX_FINISH;
361 v.segerror := '1';
362 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
363 v.state := RADIX_FINISH;
364 v.badtree := '1';
365 else
366 v.state := RADIX_LOOKUP;
367 """
368 # note that SelectableInt does big-endian! so the indices
369 # below *directly* match the spec, unlike microwatt which
370 # has to turn them around (to LE)
371 mask = genmask(shift, 44)
372 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
373 print ("RADIX _segment_check nonzero", bin(nonzero.value))
374 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
375 if addr[0] != addr[1] or nonzero == 1:
376 return "segerror"
377 limit = shift + (31 - 12)
378 if mbits < 5 or mbits > 16 or mbits > limit:
379 return "badtree"
380 new_shift = shift + (31 - 12) - mbits
381 return new_shift
382
383 def _check_perms(self, data, priv, iside, store):
384 """check page permissions
385 // Leaf PDE |
386 // |------------------------------| |----------------|
387 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
388 // |------------------------------| |----------------|
389 // [0] = V = Valid Bit |
390 // [1] = L = Leaf Bit = 1 if leaf |
391 // PDE |
392 // [2] = Sw = Sw bit 0. |
393 // [7:51] = RPN = Real Page Number, V
394 // real_page = RPN << 12 -------------> Logical OR
395 // [52:54] = Sw Bits 1:3 |
396 // [55] = R = Reference |
397 // [56] = C = Change V
398 // [58:59] = Att = Physical Address
399 // 0b00 = Normal Memory
400 // 0b01 = SAO
401 // 0b10 = Non Idenmpotent
402 // 0b11 = Tolerant I/O
403 // [60:63] = Encoded Access
404 // Authority
405 //
406 -- test leaf bit
407 -- check permissions and RC bits
408 perm_ok := '0';
409 if r.priv = '1' or data(3) = '0' then
410 if r.iside = '0' then
411 perm_ok := data(1) or (data(2) and not r.store);
412 else
413 -- no IAMR, so no KUEP support for now
414 -- deny execute permission if cache inhibited
415 perm_ok := data(0) and not data(5);
416 end if;
417 end if;
418 rc_ok := data(8) and (data(7) or not r.store);
419 if perm_ok = '1' and rc_ok = '1' then
420 v.state := RADIX_LOAD_TLB;
421 else
422 v.state := RADIX_FINISH;
423 v.perm_err := not perm_ok;
424 -- permission error takes precedence over RC error
425 v.rc_error := perm_ok;
426 end if;
427 """
428 # check permissions and RC bits
429 perm_ok = 0
430 if priv == 1 or data[60] == 0:
431 if iside == 0:
432 perm_ok = data[62] | (data[61] & (store == 0))
433 # no IAMR, so no KUEP support for now
434 # deny execute permission if cache inhibited
435 perm_ok = data[63] & ~data[58]
436 rc_ok = data[55] & (data[56] | (store == 0))
437 if perm_ok == 1 and rc_ok == 1:
438 return True
439 return "perm_err" if perm_ok == 0 else "rc_err"
440
441 def _get_prtable_addr(self, shift, prtbl, addr, pid):
442 """
443 if r.addr(63) = '1' then
444 effpid := x"00000000";
445 else
446 effpid := r.pid;
447 end if;
448 x"00" & r.prtbl(55 downto 36) &
449 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
450 (effpid(31 downto 8) and finalmask(23 downto 0))) &
451 effpid(7 downto 0) & "0000";
452 """
453 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
454 finalmask = genmask(shift, 44)
455 finalmask24 = finalmask[20:44]
456 if addr[0].value == 1:
457 effpid = SelectableInt(0, 32)
458 else:
459 effpid = pid #self.pid # TODO, check on this
460 zero16 = SelectableInt(0, 16)
461 zero4 = SelectableInt(0, 4)
462 res = selectconcat(zero16,
463 prtbl[8:28], #
464 (prtbl[28:52] & ~finalmask24) | #
465 (effpid[0:24] & finalmask24), #
466 effpid[24:32],
467 zero4
468 )
469 return res
470
471 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
472 """
473 x"00" & r.pgbase(55 downto 19) &
474 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
475 "000";
476 """
477 mask16 = genmask(mask_size+5, 16)
478 zero8 = SelectableInt(0, 8)
479 zero3 = SelectableInt(0, 3)
480 res = selectconcat(zero8,
481 pgbase[8:45], #
482 (prtbl[45:61] & ~mask16) | #
483 (addrsh & mask16), #
484 zero3
485 )
486 return res
487
488 def _get_pte(self, shift, addr, pde):
489 """
490 x"00" &
491 ((r.pde(55 downto 12) and not finalmask) or
492 (r.addr(55 downto 12) and finalmask))
493 & r.pde(11 downto 0);
494 """
495 finalmask = genmask(shift, 44)
496 zero8 = SelectableInt(0, 8)
497 res = selectconcat(zero8,
498 (pde[8:52] & ~finalmask) | #
499 (addr[8:52] & finalmask), #
500 pde[52:64],
501 )
502 return res
503
504
505 # very quick test of maskgen function (TODO, move to util later)
506 if __name__ == '__main__':
507 # set up dummy minimal ISACaller
508 spr = {'DSISR': SelectableInt(0, 64),
509 'DAR': SelectableInt(0, 64),
510 'PIDR': SelectableInt(0, 64),
511 'PRTBL': SelectableInt(0, 64)
512 }
513 class ISACaller: pass
514 caller = ISACaller()
515 caller.spr = spr
516
517 shift = SelectableInt(5, 6)
518 mask = genmask(shift, 43)
519 print (" mask", bin(mask.value))
520
521 mem = Mem(row_bytes=8)
522 mem = RADIX(mem, caller)
523 # -----------------------------------------------
524 # |/|RTS1|/| RPDB | RTS2 | RPDS |
525 # -----------------------------------------------
526 # |0|1 2|3|4 55|56 58|59 63|
527 data = SelectableInt(0, 64)
528 data[1:3] = 0b01
529 data[56:59] = 0b11
530 data[59:64] = 0b01101 # mask
531 data[55] = 1
532 (rts, mbits, pgbase) = mem._decode_prte(data)
533 print (" rts", bin(rts.value), rts.bits)
534 print (" mbits", bin(mbits.value), mbits.bits)
535 print (" pgbase", hex(pgbase.value), pgbase.bits)
536 addr = SelectableInt(0x1000, 64)
537 check = mem._segment_check(addr, mbits, shift)
538 print (" segment check", check)
539
540 print("walking tree")
541 # addr = unchanged
542 # pgbase = None
543 mode = None
544 #mbits = None
545 shift = rts
546 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
547 print(result)