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[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 # shift : unsigned(5 downto 0);
52 print("addrshift")
53 print("addr",addr)
54
55 sh1 = None # std_ulogic_vector(30 downto 0);
56 sh2 = None # std_ulogic_vector(18 downto 0);
57 result = None # std_ulogic_vector(15 downto 0);
58
59 n = 64
60 if shift[0:1].value==0:
61 print("s1==0")
62 sh1 = addr[n-42-1:n-12] # r.addr(42 downto 12);
63 elif shift[0:1].value==1:
64 print("s1==1")
65 sh1 = addr[n-58-1:n-28] # r.addr(58 downto 28);
66 else:
67 print("s1==else")
68 zero = SelectableInt(0,13) # "0000000000000"
69 sh1 = selectconcat(zero,addr[n-61-1:n-44]) # r.addr(61 downto 44);
70 print("sh1=",sh1)
71
72 n=31
73 assert(sh1.bits==n)
74
75 if shift[1:2].value==0:
76 print("s2==0")
77 sh2 = sh1[n-18-1:n] # sh1(18 downto 0);
78 elif shift[1:2].value==1:
79 print("s2==2")
80 sh2 = sh1[n-22-1:n-4] # sh1(22 downto 4);
81 elif shift[1:2].value==2:
82 print("s2==3")
83 sh2 = sh1[n-26-1:n-8] # sh1(26 downto 8);
84 else:
85 print("s2==else")
86 sh2 = sh1[n-30-1:n-12] # sh1(30 downto 12);
87 print("sh2=",sh2)
88
89 n=19
90 assert(sh2.bits==n)
91
92 if shift[3:4].value==0:
93 print("s3==0")
94 result = sh2[n-15-1:n] # sh2(15 downto 0);
95 print("xxx",result)
96 elif shift[3:4].value==1:
97 print("s3==2")
98 result = sh2[n-16-1:n-1] # sh2(16 downto 1);
99 elif shift[3:4].value==2:
100 print("s3==3")
101 result = sh2[n-17-1:n-2] # sh2(17 downto 2);
102 else:
103 print("s3==else")
104 result = sh2[n-18-1:n-3] # sh2(18 downto 3);
105
106 print("result of addrshift",result)
107
108 n=16
109 assert(result.bits==n)
110
111 return result
112
113 def NLB(x):
114 """
115 Next Level Base
116 right shifted by 8
117 """
118 return x[4:55]
119
120 def NLS(x):
121 """
122 Next Level Size
123 NLS >= 5
124 """
125 return x[59:63]
126
127 """
128 Get Root Page
129
130 //Accessing 2nd double word of partition table (pate1)
131 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
132 // PTCR Layout
133 // ====================================================
134 // -----------------------------------------------
135 // | /// | PATB | /// | PATS |
136 // -----------------------------------------------
137 // 0 4 51 52 58 59 63
138 // PATB[4:51] holds the base address of the Partition Table,
139 // right shifted by 12 bits.
140 // This is because the address of the Partition base is
141 // 4k aligned. Hence, the lower 12bits, which are always
142 // 0 are ommitted from the PTCR.
143 //
144 // Thus, The Partition Table Base is obtained by (PATB << 12)
145 //
146 // PATS represents the partition table size right-shifted by 12 bits.
147 // The minimal size of the partition table is 4k.
148 // Thus partition table size = (1 << PATS + 12).
149 //
150 // Partition Table
151 // ====================================================
152 // 0 PATE0 63 PATE1 127
153 // |----------------------|----------------------|
154 // | | |
155 // |----------------------|----------------------|
156 // | | |
157 // |----------------------|----------------------|
158 // | | | <-- effLPID
159 // |----------------------|----------------------|
160 // .
161 // .
162 // .
163 // |----------------------|----------------------|
164 // | | |
165 // |----------------------|----------------------|
166 //
167 // The effective LPID forms the index into the Partition Table.
168 //
169 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
170 // corresponding to that partition.
171 //
172 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
173 //
174 // PATE0 Layout
175 // -----------------------------------------------
176 // |1|RTS1|/| RPDB | RTS2 | RPDS |
177 // -----------------------------------------------
178 // 0 1 2 3 4 55 56 58 59 63
179 //
180 // HR[0] : For Radix Page table, first bit should be 1.
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) + 31.
184 //
185 // RPDB[4:55] = Root Page Directory Base.
186 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
187 // Thus, Root page directory size = 1 << (RPDS + 3).
188 // Note: RPDS >= 5.
189 //
190 // PATE1 Layout
191 // -----------------------------------------------
192 // |///| PRTB | // | PRTS |
193 // -----------------------------------------------
194 // 0 3 4 51 52 58 59 63
195 //
196 // PRTB[4:51] = Process Table Base. This is aligned to size.
197 // PRTS[59: 63] = Process Table Size right shifted by 12.
198 // Minimal size of the process table is 4k.
199 // Process Table Size = (1 << PRTS + 12).
200 // Note: PRTS <= 24.
201 //
202 // Computing the size aligned Process Table Base:
203 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
204 // Thus, the lower 12+PRTS bits of table_base will
205 // be zero.
206
207
208 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
209 //
210 // Process Table
211 // ==========================
212 // 0 PRTE0 63 PRTE1 127
213 // |----------------------|----------------------|
214 // | | |
215 // |----------------------|----------------------|
216 // | | |
217 // |----------------------|----------------------|
218 // | | | <-- effPID
219 // |----------------------|----------------------|
220 // .
221 // .
222 // .
223 // |----------------------|----------------------|
224 // | | |
225 // |----------------------|----------------------|
226 //
227 // The effective Process id (PID) forms the index into the Process Table.
228 //
229 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
230 // corresponding to that process
231 //
232 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
233 //
234 // PRTE0 Layout
235 // -----------------------------------------------
236 // |/|RTS1|/| RPDB | RTS2 | RPDS |
237 // -----------------------------------------------
238 // 0 1 2 3 4 55 56 58 59 63
239 //
240 // RTS1[1:2] : Gives one fragment of the Radix treesize
241 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
242 // RTS = (RTS1 << 3 + RTS2) << 31,
243 // since minimal Radix Tree size is 4G.
244 //
245 // RPDB = Root Page Directory Base.
246 // RPDS = Root Page Directory Size right shifted by 3.
247 // Thus, Root page directory size = RPDS << 3.
248 // Note: RPDS >= 5.
249 //
250 // PRTE1 Layout
251 // -----------------------------------------------
252 // | /// |
253 // -----------------------------------------------
254 // 0 63
255 // All bits are reserved.
256
257
258 """
259
260 testaddr = 0x10000
261 testmem = {
262
263 0x10000: # PARTITION_TABLE_2 (not implemented yet)
264 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
265 0x800000000100000b,
266
267 0x30000: # RADIX_ROOT_PTE
268 # V = 1 L = 0 NLB = 0x400 NLS = 9
269 0x8000000000040009,
270 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
271 0x40000: # RADIX_SECOND_LEVEL
272 # V = 1 L = 1 SW = 0 RPN = 0
273 # R = 1 C = 1 ATT = 0 EAA 0x7
274 0xc000000000000187,
275
276 0x1000000: # PROCESS_TABLE_3
277 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
278 0x40000000000300ad,
279 }
280
281
282
283 # see qemu/target/ppc/mmu-radix64.c for reference
284 class RADIX:
285 def __init__(self, mem, caller):
286 self.mem = mem
287 self.caller = caller
288 if caller is not None:
289 self.dsisr = self.caller.spr["DSISR"]
290 self.dar = self.caller.spr["DAR"]
291 self.pidr = self.caller.spr["PIDR"]
292 self.prtbl = self.caller.spr["PRTBL"]
293 self.msr = self.caller.msr
294
295 # cached page table stuff
296 self.pgtbl0 = 0
297 self.pt0_valid = False
298 self.pgtbl3 = 0
299 self.pt3_valid = False
300
301 def __call__(self, addr, sz):
302 val = self.ld(addr.value, sz, swap=False)
303 print("RADIX memread", addr, sz, val)
304 return SelectableInt(val, sz*8)
305
306 def ld(self, address, width=8, swap=True, check_in_mem=False,
307 instr_fetch=False):
308 print("RADIX: ld from addr 0x%x width %d" % (address, width))
309
310 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
311 if instr_fetch:
312 mode = 'EXECUTE'
313 else:
314 mode = 'LOAD'
315 addr = SelectableInt(address, 64)
316 (shift, mbits, pgbase) = self._decode_prte(addr)
317 #shift = SelectableInt(0, 32)
318
319 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
320 # use pte to caclculate phys address
321 return self.mem.ld(address, width, swap, check_in_mem)
322
323 # XXX set SPRs on error
324
325 # TODO implement
326 def st(self, address, v, width=8, swap=True):
327 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
328
329 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
330 mode = 'STORE'
331 addr = SelectableInt(address, 64)
332 (shift, mbits, pgbase) = self._decode_prte(addr)
333 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
334
335 # use pte to caclculate phys address (addr)
336 return self.mem.st(addr.value, v, width, swap)
337
338 # XXX set SPRs on error
339
340 def memassign(self, addr, sz, val):
341 print("memassign", addr, sz, val)
342 self.st(addr.value, val.value, sz, swap=False)
343
344 def _next_level(self, addr, entry_width, swap, check_in_mem):
345 # implement read access to mmu mem here
346
347 value = 0
348 if addr.value in testmem:
349 value = testmem[addr.value]
350 else:
351 print("not found")
352
353 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
354 print("addr", hex(addr.value))
355 data = SelectableInt(value, 64) # convert to SelectableInt
356 print("value", hex(value))
357 # index += 1
358 return data;
359
360 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
361 """walk tree
362
363 // vaddr 64 Bit
364 // vaddr |-----------------------------------------------------|
365 // | Unused | Used |
366 // |-----------|-----------------------------------------|
367 // | 0000000 | usefulBits = X bits (typically 52) |
368 // |-----------|-----------------------------------------|
369 // | |<--Cursize---->| |
370 // | | Index | |
371 // | | into Page | |
372 // | | Directory | |
373 // |-----------------------------------------------------|
374 // | |
375 // V |
376 // PDE |---------------------------| |
377 // |V|L|//| NLB |///|NLS| |
378 // |---------------------------| |
379 // PDE = Page Directory Entry |
380 // [0] = V = Valid Bit |
381 // [1] = L = Leaf bit. If 0, then |
382 // [4:55] = NLB = Next Level Base |
383 // right shifted by 8 |
384 // [59:63] = NLS = Next Level Size |
385 // | NLS >= 5 |
386 // | V
387 // | |--------------------------|
388 // | | usfulBits = X-Cursize |
389 // | |--------------------------|
390 // |---------------------><--NLS-->| |
391 // | Index | |
392 // | into | |
393 // | PDE | |
394 // |--------------------------|
395 // |
396 // If the next PDE obtained by |
397 // (NLB << 8 + 8 * index) is a |
398 // nonleaf, then repeat the above. |
399 // |
400 // If the next PDE is a leaf, |
401 // then Leaf PDE structure is as |
402 // follows |
403 // |
404 // |
405 // Leaf PDE |
406 // |------------------------------| |----------------|
407 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
408 // |------------------------------| |----------------|
409 // [0] = V = Valid Bit |
410 // [1] = L = Leaf Bit = 1 if leaf |
411 // PDE |
412 // [2] = Sw = Sw bit 0. |
413 // [7:51] = RPN = Real Page Number, V
414 // real_page = RPN << 12 -------------> Logical OR
415 // [52:54] = Sw Bits 1:3 |
416 // [55] = R = Reference |
417 // [56] = C = Change V
418 // [58:59] = Att = Physical Address
419 // 0b00 = Normal Memory
420 // 0b01 = SAO
421 // 0b10 = Non Idenmpotent
422 // 0b11 = Tolerant I/O
423 // [60:63] = Encoded Access
424 // Authority
425 //
426 """
427 # get sprs
428 print("_walk_tree")
429 pidr = self.caller.spr["PIDR"]
430 prtbl = self.caller.spr["PRTBL"]
431 print(pidr)
432 print(prtbl)
433 p = addr[55:63]
434 print("last 8 bits ----------")
435 print
436
437 # get address of root entry
438 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
439
440 addr_next = SelectableInt(0x30000,64) # radix root for testing
441
442 # walk tree starts on prtbl
443 while True:
444 print("nextlevel----------------------------")
445 # read an entry
446 swap = False
447 check_in_mem = False
448 entry_width = 8
449
450 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
451 valid = rpte_valid(data)
452 leaf = rpte_leaf(data)
453
454 print(" valid, leaf", valid, leaf)
455 if not valid:
456 return "invalid" # TODO: return error
457 if leaf:
458 ok = self._check_perms(data, priv, mode)
459 if ok == True: # data was ok, found phys address, return it?
460 return addr_next
461 return ok # return the error code
462 else:
463 newlookup = self._new_lookup(data, mbits, shift)
464 if newlookup == 'badtree':
465 return newlookup
466 shift, mask, pgbase = newlookup
467 print (" next level", shift, mask, pgbase)
468 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
469 print("calling _get_pgtable_addr")
470 print(mask) #SelectableInt(value=0x9, bits=4)
471 print(pgbase) #SelectableInt(value=0x40000, bits=56)
472 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
473 pgbase = SelectableInt(pgbase.value,64)
474 addrsh = addrshift(addr,shift)
475 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
476 print("addr_next",addr_next)
477 print("addrsh",addrsh)
478 assert(addr_next == 0x40000)
479 return "TODO verify next level"
480
481 def _new_lookup(self, data, mbits, shift):
482 """
483 mbits := unsigned('0' & data(4 downto 0));
484 if mbits < 5 or mbits > 16 or mbits > r.shift then
485 v.state := RADIX_FINISH;
486 v.badtree := '1'; -- throw error
487 else
488 v.shift := v.shift - mbits;
489 v.mask_size := mbits(4 downto 0);
490 v.pgbase := data(55 downto 8) & x"00"; NLB?
491 v.state := RADIX_LOOKUP; --> next level
492 end if;
493 """
494 mbits = data[59:64]
495 print("mbits=", mbits)
496 if mbits < 5 or mbits > 16: #fixme compare with r.shift
497 print("badtree")
498 return "badtree"
499 # reduce shift (has to be done at same bitwidth)
500 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
501 mask_size = mbits[1:5] # get 4 LSBs
502 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
503 return shift, mask_size, pgbase
504
505 def _decode_prte(self, data):
506 """PRTE0 Layout
507 -----------------------------------------------
508 |/|RTS1|/| RPDB | RTS2 | RPDS |
509 -----------------------------------------------
510 0 1 2 3 4 55 56 58 59 63
511 """
512 # note that SelectableInt does big-endian! so the indices
513 # below *directly* match the spec, unlike microwatt which
514 # has to turn them around (to LE)
515 zero = SelectableInt(0, 1)
516 rts = selectconcat(zero,
517 data[56:59], # RTS2
518 data[1:3], # RTS1
519 )
520 masksize = data[59:64] # RPDS
521 mbits = selectconcat(zero, masksize)
522 pgbase = selectconcat(data[8:56], # part of RPDB
523 SelectableInt(0, 16),)
524
525 return (rts, mbits, pgbase)
526
527 def _segment_check(self, addr, mbits, shift):
528 """checks segment valid
529 mbits := '0' & r.mask_size;
530 v.shift := r.shift + (31 - 12) - mbits;
531 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
532 if r.addr(63) /= r.addr(62) or nonzero = '1' then
533 v.state := RADIX_FINISH;
534 v.segerror := '1';
535 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
536 v.state := RADIX_FINISH;
537 v.badtree := '1';
538 else
539 v.state := RADIX_LOOKUP;
540 """
541 # note that SelectableInt does big-endian! so the indices
542 # below *directly* match the spec, unlike microwatt which
543 # has to turn them around (to LE)
544 mask = genmask(shift, 44)
545 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
546 print ("RADIX _segment_check nonzero", bin(nonzero.value))
547 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
548 if addr[0] != addr[1] or nonzero == 1:
549 return "segerror"
550 limit = shift + (31 - 12)
551 if mbits < 5 or mbits > 16 or mbits > limit:
552 return "badtree"
553 new_shift = shift + (31 - 12) - mbits
554 return new_shift
555
556 def _check_perms(self, data, priv, mode):
557 """check page permissions
558 // Leaf PDE |
559 // |------------------------------| |----------------|
560 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
561 // |------------------------------| |----------------|
562 // [0] = V = Valid Bit |
563 // [1] = L = Leaf Bit = 1 if leaf |
564 // PDE |
565 // [2] = Sw = Sw bit 0. |
566 // [7:51] = RPN = Real Page Number, V
567 // real_page = RPN << 12 -------------> Logical OR
568 // [52:54] = Sw Bits 1:3 |
569 // [55] = R = Reference |
570 // [56] = C = Change V
571 // [58:59] = Att = Physical Address
572 // 0b00 = Normal Memory
573 // 0b01 = SAO
574 // 0b10 = Non Idenmpotent
575 // 0b11 = Tolerant I/O
576 // [60:63] = Encoded Access
577 // Authority
578 //
579 -- test leaf bit
580 -- check permissions and RC bits
581 perm_ok := '0';
582 if r.priv = '1' or data(3) = '0' then
583 if r.iside = '0' then
584 perm_ok := data(1) or (data(2) and not r.store);
585 else
586 -- no IAMR, so no KUEP support for now
587 -- deny execute permission if cache inhibited
588 perm_ok := data(0) and not data(5);
589 end if;
590 end if;
591 rc_ok := data(8) and (data(7) or not r.store);
592 if perm_ok = '1' and rc_ok = '1' then
593 v.state := RADIX_LOAD_TLB;
594 else
595 v.state := RADIX_FINISH;
596 v.perm_err := not perm_ok;
597 -- permission error takes precedence over RC error
598 v.rc_error := perm_ok;
599 end if;
600 """
601 # decode mode into something that matches microwatt equivalent code
602 instr_fetch, store = 0, 0
603 if mode == 'STORE':
604 store = 1
605 if mode == 'EXECUTE':
606 inst_fetch = 1
607
608 # check permissions and RC bits
609 perm_ok = 0
610 if priv == 1 or data[60] == 0:
611 if instr_fetch == 0:
612 perm_ok = data[62] | (data[61] & (store == 0))
613 # no IAMR, so no KUEP support for now
614 # deny execute permission if cache inhibited
615 perm_ok = data[63] & ~data[58]
616 rc_ok = data[55] & (data[56] | (store == 0))
617 if perm_ok == 1 and rc_ok == 1:
618 return True
619
620 return "perm_err" if perm_ok == 0 else "rc_err"
621
622 def _get_prtable_addr(self, shift, prtbl, addr, pid):
623 """
624 if r.addr(63) = '1' then
625 effpid := x"00000000";
626 else
627 effpid := r.pid;
628 end if;
629 x"00" & r.prtbl(55 downto 36) &
630 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
631 (effpid(31 downto 8) and finalmask(23 downto 0))) &
632 effpid(7 downto 0) & "0000";
633 """
634 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
635 finalmask = genmask(shift, 44)
636 finalmask24 = finalmask[20:44]
637 if addr[0].value == 1:
638 effpid = SelectableInt(0, 32)
639 else:
640 effpid = pid #self.pid # TODO, check on this
641 zero16 = SelectableInt(0, 16)
642 zero4 = SelectableInt(0, 4)
643 res = selectconcat(zero16,
644 prtbl[8:28], #
645 (prtbl[28:52] & ~finalmask24) | #
646 (effpid[0:24] & finalmask24), #
647 effpid[24:32],
648 zero4
649 )
650 return res
651
652 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
653 """
654 x"00" & r.pgbase(55 downto 19) &
655 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
656 "000";
657 """
658 mask16 = genmask(mask_size+5, 16)
659 zero8 = SelectableInt(0, 8)
660 zero3 = SelectableInt(0, 3)
661 res = selectconcat(zero8,
662 pgbase[8:45], #
663 (pgbase[45:61] & ~mask16) | #
664 (addrsh & mask16), #
665 zero3
666 )
667 return res
668
669 def _get_pte(self, shift, addr, pde):
670 """
671 x"00" &
672 ((r.pde(55 downto 12) and not finalmask) or
673 (r.addr(55 downto 12) and finalmask))
674 & r.pde(11 downto 0);
675 """
676 finalmask = genmask(shift, 44)
677 zero8 = SelectableInt(0, 8)
678 res = selectconcat(zero8,
679 (pde[8:52] & ~finalmask) | #
680 (addr[8:52] & finalmask), #
681 pde[52:64],
682 )
683 return res
684
685
686 class TestRadixMMU(unittest.TestCase):
687
688 def test_genmask(self):
689 shift = SelectableInt(5, 6)
690 mask = genmask(shift, 43)
691 print (" mask", bin(mask.value))
692
693 self.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
694
695 def test_get_pgtable_addr(self):
696
697 mem = None
698 caller = None
699 dut = RADIX(mem, caller)
700
701 mask_size=4
702 pgbase = SelectableInt(0,64)
703 addrsh = SelectableInt(0,16)
704 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
705 print("ret=",ret)
706 assert(ret==0)
707
708 def test_walk_tree(self):
709 # set up dummy minimal ISACaller
710 spr = {'DSISR': SelectableInt(0, 64),
711 'DAR': SelectableInt(0, 64),
712 'PIDR': SelectableInt(0, 64),
713 'PRTBL': SelectableInt(0, 64)
714 }
715 # set problem state == 0 (other unit tests, set to 1)
716 msr = SelectableInt(0, 64)
717 msr[MSRb.PR] = 0
718 class ISACaller: pass
719 caller = ISACaller()
720 caller.spr = spr
721 caller.msr = msr
722
723 shift = SelectableInt(5, 6)
724 mask = genmask(shift, 43)
725 print (" mask", bin(mask.value))
726
727 mem = Mem(row_bytes=8)
728 mem = RADIX(mem, caller)
729 # -----------------------------------------------
730 # |/|RTS1|/| RPDB | RTS2 | RPDS |
731 # -----------------------------------------------
732 # |0|1 2|3|4 55|56 58|59 63|
733 data = SelectableInt(0, 64)
734 data[1:3] = 0b01
735 data[56:59] = 0b11
736 data[59:64] = 0b01101 # mask
737 data[55] = 1
738 (rts, mbits, pgbase) = mem._decode_prte(data)
739 print (" rts", bin(rts.value), rts.bits)
740 print (" mbits", bin(mbits.value), mbits.bits)
741 print (" pgbase", hex(pgbase.value), pgbase.bits)
742 addr = SelectableInt(0x1000, 64)
743 check = mem._segment_check(addr, mbits, shift)
744 print (" segment check", check)
745
746 print("walking tree")
747 addr = SelectableInt(testaddr,64)
748 # pgbase = None
749 mode = None
750 #mbits = None
751 shift = rts
752 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
753 print(" walking tree result", result)
754
755
756 if __name__ == '__main__':
757 unittest.main()