src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from copy import deepcopy
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def _check_regs(self, sim, expected):
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  22
  23     def test_sv_add(self):
  24         # adds:
  25         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  26         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  27         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  28                        ])
  29         lst = list(isa)
  30         print ("listing", lst)
  31
  32         # initial values in GPR regfile
  33         initial_regs = [0] * 32
  34         initial_regs[9] = 0x1234
  35         initial_regs[10] = 0x1111
  36         initial_regs[5] = 0x4321
  37         initial_regs[6] = 0x2223
  38         # SVSTATE (in this case, VL=2)
  39         svstate = SVP64State()
  40         svstate.vl[0:7] = 2 # VL
  41         svstate.maxvl[0:7] = 2 # MAXVL
  42         print ("SVSTATE", bin(svstate.spr.asint()))
  43         # copy before running
  44         expected_regs = deepcopy(initial_regs)
  45         expected_regs[1] = 0x5555
  46         expected_regs[2] = 0x3334
  47
  48         with Program(lst, bigendian=False) as program:
  49             sim = self.run_tst_program(program, initial_regs, svstate)
  50             self._check_regs(sim, expected_regs)
  51
  52     def test_sv_add_2(self):
  53         # adds:
  54         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  55         #       r1 is scalar so ENDS EARLY
  56         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  57                        ])
  58         lst = list(isa)
  59         print ("listing", lst)
  60
  61         # initial values in GPR regfile
  62         initial_regs = [0] * 32
  63         initial_regs[9] = 0x1234
  64         initial_regs[10] = 0x1111
  65         initial_regs[5] = 0x4321
  66         initial_regs[6] = 0x2223
  67         # SVSTATE (in this case, VL=2)
  68         svstate = SVP64State()
  69         svstate.vl[0:7] = 2 # VL
  70         svstate.maxvl[0:7] = 2 # MAXVL
  71         print ("SVSTATE", bin(svstate.spr.asint()))
  72         # copy before running
  73         expected_regs = deepcopy(initial_regs)
  74         expected_regs[1] = 0x5555
  75
  76         with Program(lst, bigendian=False) as program:
  77             sim = self.run_tst_program(program, initial_regs, svstate)
  78             self._check_regs(sim, expected_regs)
  79
  80     def test_sv_add_3(self):
  81         # adds:
  82         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  83         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
  84         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
  85                        ])
  86         lst = list(isa)
  87         print ("listing", lst)
  88
  89         # initial values in GPR regfile
  90         initial_regs = [0] * 32
  91         initial_regs[9] = 0x1234
  92         initial_regs[10] = 0x1111
  93         initial_regs[5] = 0x4321
  94         initial_regs[6] = 0x2223
  95         # SVSTATE (in this case, VL=2)
  96         svstate = SVP64State()
  97         svstate.vl[0:7] = 2 # VL
  98         svstate.maxvl[0:7] = 2 # MAXVL
  99         print ("SVSTATE", bin(svstate.spr.asint()))
 100         # copy before running
 101         expected_regs = deepcopy(initial_regs)
 102         expected_regs[1] = 0x5555
 103         expected_regs[2] = 0x5432
 104
 105         with Program(lst, bigendian=False) as program:
 106             sim = self.run_tst_program(program, initial_regs, svstate)
 107             self._check_regs(sim, expected_regs)
 108
 109     def test_sv_add_cr(self):
 110         # adds when Rc=1:                               TODO CRs higher up
 111         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 112         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 113         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 114                        ])
 115         lst = list(isa)
 116         print ("listing", lst)
 117
 118         # initial values in GPR regfile
 119         initial_regs = [0] * 32
 120         initial_regs[9] = 0xffffffffffffffff
 121         initial_regs[10] = 0x1111
 122         initial_regs[5] = 0x1
 123         initial_regs[6] = 0x2223
 124         # SVSTATE (in this case, VL=2)
 125         svstate = SVP64State()
 126         svstate.vl[0:7] = 2 # VL
 127         svstate.maxvl[0:7] = 2 # MAXVL
 128         print ("SVSTATE", bin(svstate.spr.asint()))
 129         # copy before running
 130         expected_regs = deepcopy(initial_regs)
 131         expected_regs[1] = 0
 132         expected_regs[2] = 0x3334
 133
 134         with Program(lst, bigendian=False) as program:
 135             sim = self.run_tst_program(program, initial_regs, svstate)
 136             # XXX TODO, these need to move to higher range (offset)
 137             CR0 = sim.crl[0].get_range().value
 138             CR1 = sim.crl[1].get_range().value
 139             print ("CR0", CR0)
 140             print ("CR1", CR1)
 141             self._check_regs(sim, expected_regs)
 142             self.assertEqual(CR0, SelectableInt(2, 4))
 143             self.assertEqual(CR1, SelectableInt(4, 4))
 144
 145     def run_tst_program(self, prog, initial_regs=[0] * 32,
 146                               svstate=None):
 147         simulator = run_tst(prog, initial_regs, svstate=svstate)
 148         simulator.gpr.dump()
 149         return simulator
 150
 151
 152 if __name__ == "__main__":
 153     unittest.main()