d1cad1211c556416321be0967cc6a6333f1eef9a
1 from enum
import Enum
, unique
7 def download_wiki_file(name
, name_on_wiki
=None):
8 if name_on_wiki
is None:
10 file_dir
= os
.path
.dirname(os
.path
.realpath(__file__
))
11 file_path
= os
.path
.join(file_dir
, name
)
12 if not os
.path
.isfile(file_path
):
13 url
= 'https://libre-riscv.org/openpower/isatables/' + name_on_wiki
14 r
= requests
.get(url
, allow_redirects
=True)
15 with
open(file_path
, 'w') as outfile
:
16 outfile
.write(r
.content
.decode("utf-8"))
21 file_path
= download_wiki_file(name
)
22 with
open(file_path
, 'r') as csvfile
:
23 reader
= csv
.DictReader(csvfile
)
27 # names of the fields in the tables that don't correspond to an enum
28 single_bit_flags
= ['CR in', 'CR out', 'inv A', 'inv out',
29 'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
30 'sgn', 'lk', 'sgl pipe']
32 # default values for fields in the table
33 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
34 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
36 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
39 def get_signal_name(name
):
42 return name
.lower().replace(' ', '_')
85 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
87 class InternalOp(Enum
):
88 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
221 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
222 # http://libre-riscv.org/openpower/isatables/sprs.csv
223 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
225 spr_csv
= get_csv("sprs.csv")
226 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
227 SPR
= Enum('SPR', fields
)