src/soc/experiment/cache_ram.py

   1 # entity cache_ram is
   2 #     generic(
   3 #       ROW_BITS : integer := 16;
   4 #       WIDTH    : integer := 64;
   5 #       TRACE    : boolean := false;
   6 #       ADD_BUF  : boolean := false
   7 #       );
   8 #
   9 #     port(
  10 #       clk     : in  std_logic;
  11 #       rd_en   : in  std_logic;
  12 #       rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  13 #       rd_data : out std_logic_vector(WIDTH - 1 downto 0);
  14 #       wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
  15 #       wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  16 #       wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
  17 #       );
  18 #
  19 # end cache_ram;
  20 #
  21 # architecture rtl of cache_ram is
  22 #     constant SIZE : integer := 2**ROW_BITS;
  23 #
  24 #     type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
  25 #     signal ram : ram_type;
  26 #     attribute ram_style : string;
  27 #     attribute ram_style of ram : signal is "block";
  28 #
  29 #     signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
  30 #
  31 # begin
  32 #     process(clk)
  33 #       variable lbit : integer range 0 to WIDTH - 1;
  34 #       variable mbit : integer range 0 to WIDTH - 1;
  35 #       variable widx : integer range 0 to SIZE - 1;
  36 #       constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
  37 #             := (others => '0');
  38 #     begin
  39 #       if rising_edge(clk) then
  40 #             with m.If( TRACE then
  41 #                 with m.If( wr_sel /= sel0 then
  42 #                     report "write a:" & to_hstring(wr_addr) &
  43 #                         " sel:" & to_hstring(wr_sel) &
  44 #                         " dat:" & to_hstring(wr_data);
  45 #                 end with m.If(;
  46 #             end with m.If(;
  47 #             for i in 0 to WIDTH/8-1 loop
  48 #                 lbit := i * 8;
  49 #                 mbit := lbit + 7;
  50 #                 widx := to_integer(unsigned(wr_addr));
  51 #                 with m.If( wr_sel(i) = '1' then
  52 #                     ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
  53 #                 end with m.If(;
  54 #             end loop;
  55 #           with m.If( rd_en = '1' then
  56 #               rd_data0 <= ram(to_integer(unsigned(rd_addr)));
  57 #               if TRACE then
  58 #                   report "read a:" & to_hstring(rd_addr) &
  59 #                       " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
  60 #               end with m.If(;
  61 #           end with m.If(;
  62 #       end with m.If(;
  63 #     end process;
  64 #
  65 #     buf: with m.If( ADD_BUF generate
  66 #     begin
  67 #       process(clk)
  68 #       begin
  69 #           with m.If( rising_edge(clk) then
  70 #               rd_data <= rd_data0;
  71 #           end with m.If(;
  72 #       end process;
  73 #     end generate;
  74 #
  75 #     nobuf: with m.If( not ADD_BUF generate
  76 #     begin
  77 #       rd_data <= rd_data0;
  78 #     end generate;
  79 #
  80 # end;