ad80894d6c7bd3e93aa6f685bd9878eac52b0985
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Repl
, Array
, Record
4 from nmigen
.hdl
.rec
import (DIR_FANIN
, DIR_FANOUT
)
6 from nmutil
.latch
import SRLatch
, latchregister
7 from soc
.decoder
.power_decoder2
import Data
8 from soc
.decoder
.power_enums
import InternalOp
10 from alu_hier
import CompALUOpSubset
12 """ Computation Unit (aka "ALU Manager").
14 This module runs a "revolving door" set of three latches, based on
18 where one of them cannot be set on any given cycle.
19 (Note however that opc_l has been inverted (and qn used), due to SRLatch
20 default reset state being "0" rather than "1")
22 * When issue is first raised, a busy signal is sent out.
23 The src1 and src2 registers and the operand can be latched in
26 * Read request is set, which is acknowledged through the Scoreboard
27 to the priority picker, which generates (one and only one) Go_Read
28 at a time. One of those will (eventually) be this Computation Unit.
30 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
31 src1/src2/operand in place), and the ALU is told to proceed.
33 * As this is currently a "demo" unit, a countdown timer is activated
34 to simulate an ALU "pipeline", which activates "write request release",
35 and the ALU's output is captured into a temporary register.
37 * Write request release will go through a similar process as Read request,
38 resulting (eventually) in Go_Write being asserted.
40 * When Go_Write is asserted, two things happen: (1) the data in the temp
41 register is placed combinatorially onto the output, and (2) the
42 req_l latch is cleared, busy is dropped, and the Comp Unit is back
43 through its revolving door to do another task.
46 def go_record(n
, name
):
47 r
= Record([('go', n
, DIR_FANIN
),
48 ('rel', n
, DIR_FANOUT
)], name
=name
)
49 r
.go
.reset_less
= True
50 r
.rel
.reset_less
= True
54 class MultiCompUnit(Elaboratable
):
55 def __init__(self
, rwid
, alu
, n_src
=2, n_dst
=1):
56 self
.n_src
, self
.n_dst
= n_src
, n_dst
58 self
.alu
= alu
# actual ALU - set as a "submodule" of the CU
60 self
.counter
= Signal(4)
62 for i
in range(n_src
):
63 j
= i
+ 1 # name numbering to match src1/src2
64 src
.append(Signal(rwid
, name
="src%d_i" % j
, reset_less
=True))
67 for i
in range(n_dst
):
68 j
= i
+ 1 # name numbering to match dest1/2...
69 dst
.append(Signal(rwid
, name
="dest%d_i" % j
, reset_less
=True))
71 self
.rd
= go_record(n_src
, name
="rd") # read in, req out
72 self
.wr
= go_record(n_dst
, name
="wr") # write in, req out
73 self
.go_rd_i
= self
.rd
.go
# temporary naming
74 self
.go_wr_i
= self
.wr
.go
# temporary naming
75 self
.rd_rel_o
= self
.rd
.rel
# temporary naming
76 self
.req_rel_o
= self
.wr
.rel
# temporary naming
77 self
.issue_i
= Signal(reset_less
=True) # fn issue in
78 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
79 self
.go_die_i
= Signal() # go die (reset)
81 # operation / data input
82 self
.oper_i
= CompALUOpSubset() # operand
83 self
.src_i
= Array(src
)
84 self
.src1_i
= src
[0] # oper1 in
85 self
.src2_i
= src
[1] # oper2 in
87 self
.busy_o
= Signal(reset_less
=True) # fn busy out
88 self
.dest
= Array(dst
)
89 self
.data_o
= dst
[0] # Dest out
90 self
.done_o
= Signal(reset_less
=True)
92 def elaborate(self
, platform
):
94 m
.submodules
.alu
= self
.alu
95 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
96 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
97 m
.submodules
.req_l
= req_l
= SRLatch(False, self
.n_dst
, name
="req")
98 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
99 m
.submodules
.rok_l
= rok_l
= SRLatch(sync
=False, name
="rdok")
101 # ALU only proceeds when all src are ready. rd_rel_o is delayed
102 # so combine it with go_rd_i. if all bits are set we're good
103 all_rd
= Signal(reset_less
=True)
104 m
.d
.comb
+= all_rd
.eq(self
.busy_o
& rok_l
.q
&
105 (((~self
.rd
.rel
) | self
.rd
.go
).all()))
107 # write_requests all done
108 wr_any
= Signal(reset_less
=True)
109 req_done
= Signal(reset_less
=True)
110 m
.d
.comb
+= self
.done_o
.eq(self
.busy_o
& ~
(self
.wr
.rel
.bool()))
111 m
.d
.comb
+= wr_any
.eq(self
.wr
.go
.bool())
112 m
.d
.comb
+= req_done
.eq(rst_l
.q
& wr_any
)
115 reset
= Signal(reset_less
=True)
116 rst_r
= Signal(reset_less
=True) # reset latch off
117 reset_w
= Signal(self
.n_dst
, reset_less
=True)
118 reset_r
= Signal(self
.n_src
, reset_less
=True)
119 m
.d
.comb
+= reset
.eq(req_done | self
.go_die_i
)
120 m
.d
.comb
+= rst_r
.eq(self
.issue_i | self
.go_die_i
)
121 m
.d
.comb
+= reset_w
.eq(self
.wr
.go |
Repl(self
.go_die_i
, self
.n_dst
))
122 m
.d
.comb
+= reset_r
.eq(self
.rd
.go |
Repl(self
.go_die_i
, self
.n_src
))
124 # read-done,wr-proceed latch
125 m
.d
.comb
+= rok_l
.s
.eq(self
.issue_i
) # set up when issue starts
126 m
.d
.comb
+= rok_l
.r
.eq(self
.alu
.p_ready_o
) # off when ALU acknowledges
128 # wr-done, back-to-start latch
129 m
.d
.comb
+= rst_l
.s
.eq(all_rd
) # set when read-phase is fully done
130 m
.d
.comb
+= rst_l
.r
.eq(rst_r
) # *off* on issue
132 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
133 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # set on issue
134 m
.d
.sync
+= opc_l
.r
.eq(self
.alu
.n_valid_o
& req_done
) # reset on ALU
136 # src operand latch (not using go_wr_i)
137 m
.d
.sync
+= src_l
.s
.eq(Repl(self
.issue_i
, self
.n_src
))
138 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
140 # dest operand latch (not using issue_i)
141 m
.d
.sync
+= req_l
.s
.eq(Repl(all_rd
, self
.n_dst
))
142 m
.d
.sync
+= req_l
.r
.eq(reset_w
)
144 # create a latch/register for the operand
145 oper_r
= CompALUOpSubset()
146 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, "oper_r")
148 # and for each output from the ALU
150 for i
in range(self
.n_dst
):
151 name
= "data_r%d" % i
152 data_r
= Signal(self
.rwid
, name
=name
, reset_less
=True)
153 latchregister(m
, self
.alu
.out
[i
], data_r
, req_l
.q
[i
], name
)
156 # pass the operation to the ALU
157 m
.d
.comb
+= self
.alu
.op
.eq(oper_r
)
159 # create list of src/alu-src/src-latch. override 2nd one below
161 for i
in range(self
.n_src
):
162 sl
.append([self
.src_i
[i
], self
.alu
.i
[i
], src_l
.q
[i
]])
164 # select immediate if opcode says so. however also change the latch
165 # to trigger *from* the opcode latch instead.
166 op_is_imm
= oper_r
.imm_data
.imm_ok
167 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
168 src_sel
= Signal(reset_less
=True)
169 m
.d
.comb
+= src_sel
.eq(Mux(op_is_imm
, opc_l
.q
, src_l
.q
[1]))
170 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
,
172 # overwrite 2nd src-latch with immediate-muxed stuff
173 sl
[1][0] = src2_or_imm
176 # create a latch/register for src1/src2
177 for i
in range(self
.n_src
):
178 src
, alusrc
, latch
= sl
[i
]
179 latchregister(m
, src
, alusrc
, latch
, name
="src_r%d" % i
)
185 # all request signals gated by busy_o. prevents picker problems
186 m
.d
.comb
+= self
.busy_o
.eq(opc_l
.q
) # busy out
187 bro
= Repl(self
.busy_o
, self
.n_src
)
188 m
.d
.comb
+= self
.rd
.rel
.eq(src_l
.q
& bro
) # src1/src2 req rel
190 # on a go_read, tell the ALU we're accepting data.
191 # NOTE: this spells TROUBLE if the ALU isn't ready!
192 # go_read is only valid for one clock!
193 with m
.If(all_rd
): # src operands ready, GO!
194 with m
.If(~self
.alu
.p_ready_o
): # no ACK yet
195 m
.d
.comb
+= self
.alu
.p_valid_i
.eq(1) # so indicate valid
197 brd
= Repl(self
.busy_o
& self
.shadown_i
, self
.n_dst
)
198 # only proceed if ALU says its output is valid
199 with m
.If(self
.alu
.n_valid_o
):
200 # when ALU ready, write req release out. waits for shadow
201 m
.d
.comb
+= self
.wr
.rel
.eq(req_l
.q
& brd
)
202 # when output latch is ready, and ALU says ready, accept ALU output
204 m
.d
.comb
+= self
.alu
.n_ready_i
.eq(1) # tells ALU "thanks got it"
206 # output the data from the latch on go_write
207 for i
in range(self
.n_dst
):
208 with m
.If(self
.wr
.go
[i
]):
209 m
.d
.comb
+= self
.dest
[i
].eq(drl
[i
])
219 yield from self
.oper_i
.ports()
231 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0):
232 yield dut
.issue_i
.eq(0)
234 yield dut
.src_i
[0].eq(a
)
235 yield dut
.src_i
[1].eq(b
)
236 yield dut
.oper_i
.insn_type
.eq(op
)
237 yield dut
.oper_i
.invert_a
.eq(inv_a
)
238 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
239 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
240 yield dut
.issue_i
.eq(1)
242 yield dut
.issue_i
.eq(0)
244 yield dut
.rd
.go
.eq(0b11)
247 rd_rel_o
= yield dut
.rd
.rel
248 print ("rd_rel", rd_rel_o
)
252 yield dut
.rd
.go
.eq(0)
253 req_rel_o
= yield dut
.wr
.rel
254 result
= yield dut
.data_o
255 print ("req_rel", req_rel_o
, result
)
257 req_rel_o
= yield dut
.wr
.rel
258 result
= yield dut
.data_o
259 print ("req_rel", req_rel_o
, result
)
263 yield dut
.wr
.go
[0].eq(1)
265 result
= yield dut
.data_o
266 print ("result", result
)
267 yield dut
.wr
.go
[0].eq(0)
272 def scoreboard_sim(dut
):
273 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=0,
277 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
)
280 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=1)
281 assert result
== 65532
284 def test_scoreboard():
285 from alu_hier
import ALU
286 from soc
.decoder
.power_decoder2
import Decode2ToExecute1Type
290 dut
= MultiCompUnit(16, alu
)
291 m
.submodules
.cu
= dut
293 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
294 with
open("test_compalu.il", "w") as f
:
297 run_simulation(m
, scoreboard_sim(dut
), vcd_name
='test_compalu.vcd')
299 if __name__
== '__main__':