dddb1f7730c1b2f3c467683adb22a6e5299412da
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Repl
, Array
5 from nmutil
.latch
import SRLatch
, latchregister
6 from soc
.decoder
.power_decoder2
import Data
7 from soc
.decoder
.power_enums
import InternalOp
9 from alu_hier
import CompALUOpSubset
11 """ Computation Unit (aka "ALU Manager").
13 This module runs a "revolving door" set of three latches, based on
17 where one of them cannot be set on any given cycle.
18 (Note however that opc_l has been inverted (and qn used), due to SRLatch
19 default reset state being "0" rather than "1")
21 * When issue is first raised, a busy signal is sent out.
22 The src1 and src2 registers and the operand can be latched in
25 * Read request is set, which is acknowledged through the Scoreboard
26 to the priority picker, which generates (one and only one) Go_Read
27 at a time. One of those will (eventually) be this Computation Unit.
29 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
30 src1/src2/operand in place), and the ALU is told to proceed.
32 * As this is currently a "demo" unit, a countdown timer is activated
33 to simulate an ALU "pipeline", which activates "write request release",
34 and the ALU's output is captured into a temporary register.
36 * Write request release will go through a similar process as Read request,
37 resulting (eventually) in Go_Write being asserted.
39 * When Go_Write is asserted, two things happen: (1) the data in the temp
40 register is placed combinatorially onto the output, and (2) the
41 req_l latch is cleared, busy is dropped, and the Comp Unit is back
42 through its revolving door to do another task.
46 class ComputationUnitNoDelay(Elaboratable
):
47 def __init__(self
, rwid
, alu
, n_src
=2, n_dst
=1):
48 self
.n_src
, self
.n_dst
= n_src
, n_dst
50 self
.alu
= alu
# actual ALU - set as a "submodule" of the CU
52 self
.counter
= Signal(4)
54 for i
in range(n_src
):
55 j
= i
+ 1 # name numbering to match src1/src2
56 src
.append(Signal(rwid
, name
="src%d_i" % j
, reset_less
=True))
59 for i
in range(n_dst
):
60 j
= i
+ 1 # name numbering to match dest1/2...
61 dst
.append(Signal(rwid
, name
="dest%d_i" % j
, reset_less
=True))
63 self
.go_rd_i
= Signal(n_src
, reset_less
=True) # read in
64 self
.go_wr_i
= Signal(n_dst
, reset_less
=True) # write in
65 self
.issue_i
= Signal(reset_less
=True) # fn issue in
66 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
67 self
.go_die_i
= Signal() # go die (reset)
69 # operation / data input
70 self
.oper_i
= CompALUOpSubset() # operand
71 self
.src_i
= Array(src
)
72 self
.src1_i
= src
[0] # oper1 in
73 self
.src2_i
= src
[1] # oper2 in
75 self
.busy_o
= Signal(reset_less
=True) # fn busy out
76 self
.dest
= Array(dst
)
77 self
.data_o
= dst
[0] # Dest out
78 self
.rd_rel_o
= Signal(n_src
, reset_less
=True) # release src1/src2
79 self
.req_rel_o
= Signal(n_dst
, reset_less
=True) # release out (valid_o)
80 self
.done_o
= Signal(reset_less
=True)
82 def elaborate(self
, platform
):
84 m
.submodules
.alu
= self
.alu
85 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
86 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
87 m
.submodules
.req_l
= req_l
= SRLatch(False, self
.n_dst
, name
="req")
88 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
89 m
.submodules
.rok_l
= rok_l
= SRLatch(sync
=False, name
="rdok")
91 # ALU only proceeds when all src are ready. rd_rel_o is delayed
92 # so combine it with go_rd_i. if all bits are set we're good
93 all_rd
= Signal(reset_less
=True)
94 m
.d
.comb
+= all_rd
.eq(self
.busy_o
& rok_l
.q
&
95 (((~self
.rd_rel_o
) | self
.go_rd_i
).all()))
97 # write_requests all done
98 wr_any
= Signal(reset_less
=True)
99 req_done
= Signal(reset_less
=True)
100 m
.d
.comb
+= self
.done_o
.eq(self
.busy_o
& ~
(self
.req_rel_o
.bool()))
101 m
.d
.comb
+= wr_any
.eq(self
.go_wr_i
.bool())
102 m
.d
.comb
+= req_done
.eq(self
.done_o
& rst_l
.q
& wr_any
)
105 reset
= Signal(reset_less
=True)
106 rst_r
= Signal(reset_less
=True) # reset latch off
107 reset_w
= Signal(self
.n_dst
, reset_less
=True)
108 reset_r
= Signal(self
.n_src
, reset_less
=True)
109 m
.d
.comb
+= reset
.eq(req_done | self
.go_die_i
)
110 m
.d
.comb
+= rst_r
.eq(self
.issue_i | self
.go_die_i
)
111 m
.d
.comb
+= reset_w
.eq(self
.go_wr_i |
Repl(self
.go_die_i
, self
.n_dst
))
112 m
.d
.comb
+= reset_r
.eq(self
.go_rd_i |
Repl(self
.go_die_i
, self
.n_src
))
114 # read-done,wr-proceed latch
115 m
.d
.comb
+= rok_l
.s
.eq(self
.issue_i
) # set up when issue starts
116 m
.d
.comb
+= rok_l
.r
.eq(self
.alu
.p_ready_o
) # off when ALU acknowledges
118 # wr-done, back-to-start latch
119 m
.d
.comb
+= rst_l
.s
.eq(all_rd
) # set when read-phase is fully done
120 m
.d
.comb
+= rst_l
.r
.eq(rst_r
) # *off* on issue
122 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
123 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # set on issue
124 m
.d
.sync
+= opc_l
.r
.eq(self
.alu
.n_valid_o
) # reset on ALU finishes
126 # src operand latch (not using go_wr_i)
127 m
.d
.sync
+= src_l
.s
.eq(Repl(self
.issue_i
, self
.n_src
))
128 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
130 # dest operand latch (not using issue_i)
131 m
.d
.sync
+= req_l
.s
.eq(Repl(all_rd
, self
.n_dst
))
132 m
.d
.sync
+= req_l
.r
.eq(reset_w
)
134 # create a latch/register for the operand
135 oper_r
= CompALUOpSubset()
136 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, "oper_r")
138 # and for each output from the ALU
140 for i
in range(self
.n_dst
):
141 name
= "data_r%d" % i
142 data_r
= Signal(self
.rwid
, name
=name
, reset_less
=True)
143 latchregister(m
, self
.alu
.out
[i
], data_r
, req_l
.q
[i
], name
)
146 # pass the operation to the ALU
147 m
.d
.comb
+= self
.alu
.op
.eq(oper_r
)
149 # create list of src/alu-src/src-latch. override 2nd one below
151 for i
in range(self
.n_src
):
152 sl
.append([self
.src_i
[i
], self
.alu
.i
[i
], src_l
.q
[i
]])
154 # select immediate if opcode says so. however also change the latch
155 # to trigger *from* the opcode latch instead.
156 op_is_imm
= oper_r
.imm_data
.imm_ok
157 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
158 src_sel
= Signal(reset_less
=True)
159 m
.d
.comb
+= src_sel
.eq(Mux(op_is_imm
, opc_l
.q
, src_l
.q
[1]))
160 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
,
162 # overwrite 2nd src-latch with immediate-muxed stuff
163 sl
[1][0] = src2_or_imm
166 # create a latch/register for src1/src2
167 for i
in range(self
.n_src
):
168 src
, alusrc
, latch
= sl
[i
]
169 latchregister(m
, src
, alusrc
, latch
, name
="src_r%d" % i
)
175 # all request signals gated by busy_o. prevents picker problems
176 m
.d
.comb
+= self
.busy_o
.eq(opc_l
.q
) # busy out
177 bro
= Repl(self
.busy_o
, self
.n_src
)
178 m
.d
.comb
+= self
.rd_rel_o
.eq(src_l
.q
& bro
) # src1/src2 req rel
180 # on a go_read, tell the ALU we're accepting data.
181 # NOTE: this spells TROUBLE if the ALU isn't ready!
182 # go_read is only valid for one clock!
183 with m
.If(all_rd
): # src operands ready, GO!
184 with m
.If(~self
.alu
.p_ready_o
): # no ACK yet
185 m
.d
.comb
+= self
.alu
.p_valid_i
.eq(1) # so indicate valid
187 brd
= Repl(self
.busy_o
& self
.shadown_i
, self
.n_dst
)
188 # only proceed if ALU says its output is valid
189 with m
.If(self
.alu
.n_valid_o
):
190 # when ALU ready, write req release out. waits for shadow
191 m
.d
.comb
+= self
.req_rel_o
.eq(req_l
.q
& brd
)
192 # when output latch is ready, and ALU says ready, accept ALU output
194 m
.d
.comb
+= self
.alu
.n_ready_i
.eq(1) # tells ALU "thanks got it"
196 # output the data from the latch on go_write
197 for i
in range(self
.n_dst
):
198 with m
.If(self
.go_wr_i
[i
]):
199 m
.d
.comb
+= self
.dest
[i
].eq(drl
[i
])
209 yield from self
.oper_i
.ports()
221 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0):
222 yield dut
.issue_i
.eq(0)
224 yield dut
.src_i
[0].eq(a
)
225 yield dut
.src_i
[1].eq(b
)
226 yield dut
.oper_i
.insn_type
.eq(op
)
227 yield dut
.oper_i
.invert_a
.eq(inv_a
)
228 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
229 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
230 yield dut
.issue_i
.eq(1)
232 yield dut
.issue_i
.eq(0)
234 yield dut
.go_rd_i
.eq(0b11)
237 rd_rel_o
= yield dut
.rd_rel_o
238 print ("rd_rel", rd_rel_o
)
242 yield dut
.go_rd_i
.eq(0)
243 req_rel_o
= yield dut
.req_rel_o
244 result
= yield dut
.data_o
245 print ("req_rel", req_rel_o
, result
)
247 req_rel_o
= yield dut
.req_rel_o
248 result
= yield dut
.data_o
249 print ("req_rel", req_rel_o
, result
)
253 yield dut
.go_wr_i
[0].eq(1)
255 result
= yield dut
.data_o
256 print ("result", result
)
257 yield dut
.go_wr_i
[0].eq(0)
262 def scoreboard_sim(dut
):
263 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=0,
267 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
)
270 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=1)
271 assert result
== 65532
274 def test_scoreboard():
275 from alu_hier
import ALU
276 from soc
.decoder
.power_decoder2
import Decode2ToExecute1Type
280 dut
= ComputationUnitNoDelay(16, alu
)
281 m
.submodules
.cu
= dut
283 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
284 with
open("test_compalu.il", "w") as f
:
287 run_simulation(m
, scoreboard_sim(dut
), vcd_name
='test_compalu.vcd')
289 if __name__
== '__main__':