1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
89 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
90 from soc
.experiment
.l0_cache
import PortInterface
91 from soc
.fu
.regspec
import RegSpecAPI
93 from soc
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
94 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
95 from soc
.decoder
.power_decoder2
import Data
98 class LDSTCompUnitRecord(CompUnitRecord
):
99 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
100 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
101 n_src
=3, n_dst
=2, name
=name
)
103 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
104 self
.st
= go_record(1, name
="cu_st") # store go in, req out
106 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
108 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
109 self
.st_o
= Signal(reset_less
=True) # operation is a ST
111 # hmm... are these necessary?
112 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
113 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
116 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
117 """LOAD / STORE Computation Unit
122 * :pi: a PortInterface to the memory subsystem (read-write capable)
123 * :rwid: register width
124 * :awid: address width
128 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
132 * :data_o: Dest out (LD) - managed by wr[0] go/req
133 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
134 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
136 TODO: make addr_exc_o a data-type rather than a single-bit signal
142 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
143 * :issue_i: LD/ST is being "issued".
144 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
145 * :go_rd_i: read is being actioned (latches in src regs)
146 * :go_wr_i: write mode (exactly like ALU CompUnit)
147 * :go_ad_i: address is being actioned (triggers actual mem LD)
148 * :go_st_i: store is being actioned (triggers actual mem STORE)
149 * :go_die_i: resets the unit back to "wait for issue"
151 Control Signals (Out)
152 ---------------------
154 * :busy_o: function unit is busy
155 * :rd_rel_o: request src1/src2
156 * :adr_rel_o: request address (from mem)
157 * :sto_rel_o: request store (to mem)
158 * :req_rel_o: request write (result)
159 * :load_mem_o: activate memory LOAD
160 * :stwd_mem_o: activate memory STORE
162 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
163 in a single cycle and the CompUnit set back to doing another op.
164 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
165 depending on whether the operation is a ST or LD.
167 Note: LDSTCompUnit takes care of LE/BE normalisation:
168 * LD data is normalised after receipt from the PortInterface
169 * ST data is normalised *prior* to sending onto the PortInterface
170 TODO: use one module for the byte-reverse as it's quite expensive in gates
173 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
174 debugtest
=False, name
=None):
175 super().__init
__(rwid
)
178 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
179 self
.debugtest
= debugtest
181 # POWER-compliant LD/ST has index and update: *fixed* number of ports
182 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
183 self
.n_dst
= n_dst
= 2 # RA, RT/RS
185 # set up array of src and dest signals
186 for i
in range(n_src
):
187 j
= i
+ 1 # name numbering to match src1/src2
189 setattr(self
, name
, getattr(cu
, name
))
192 for i
in range(n_dst
):
193 j
= i
+ 1 # name numbering to match dest1/2...
194 name
= "dest%d_o" % j
195 setattr(self
, name
, getattr(cu
, name
))
200 self
.rdmaskn
= cu
.rdmaskn
201 self
.wrmask
= cu
.wrmask
206 # HACK: get data width from dest[0]. this is used across the board
207 # (it really shouldn't be)
208 self
.data_wid
= self
.dest
[0].shape()
210 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
211 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
212 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
213 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
215 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
216 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
217 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
218 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
220 self
.issue_i
= cu
.issue_i
221 self
.shadown_i
= cu
.shadown_i
222 self
.go_die_i
= cu
.go_die_i
224 self
.oper_i
= cu
.oper_i
225 self
.src_i
= cu
._src
_i
227 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
228 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
229 self
.addr_exc_o
= cu
.addr_exc_o
230 self
.done_o
= cu
.done_o
231 self
.busy_o
= cu
.busy_o
236 self
.load_mem_o
= cu
.load_mem_o
237 self
.stwd_mem_o
= cu
.stwd_mem_o
239 def elaborate(self
, platform
):
245 issue_i
= self
.issue_i
247 #####################
248 # latches for the FSM.
249 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
250 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
251 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
252 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
253 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
254 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
255 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
256 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
257 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
258 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
264 op_is_ld
= Signal(reset_less
=True)
265 op_is_st
= Signal(reset_less
=True)
267 # ALU/LD data output control
268 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
269 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
270 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
271 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
272 wr_any
= Signal(reset_less
=True) # any write (incl. store)
273 rda_any
= Signal(reset_less
=True) # any read for address ops
274 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
275 wr_reset
= Signal(reset_less
=True) # final reset condition
278 alu_o
= Signal(self
.data_wid
, reset_less
=True)
279 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
281 ##############################
282 # reset conditions for latches
284 # temporaries (also convenient when debugging)
285 reset_o
= Signal(reset_less
=True) # reset opcode
286 reset_w
= Signal(reset_less
=True) # reset write
287 reset_u
= Signal(reset_less
=True) # reset update
288 reset_a
= Signal(reset_less
=True) # reset adr latch
289 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
290 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
291 reset_s
= Signal(reset_less
=True) # reset store
293 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
294 comb
+= reset_o
.eq(wr_reset | self
.go_die_i
) # opcode reset
295 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | self
.go_die_i
) # write reg 1
296 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | self
.go_die_i
) # update (reg 2)
297 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
298 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(self
.go_die_i
, self
.n_src
))
299 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
301 p_st_go
= Signal(reset_less
=True)
302 sync
+= p_st_go
.eq(self
.st
.go_i
)
304 ##########################
305 # FSM implemented through sequence of latches. approximately this:
307 # - src_l[0] : operands
309 # - alu_l : looks after add of src1/2/imm (EA)
310 # - adr_l : waits for add (EA)
311 # - upd_l : waits for adr and Regfile (port 2)
313 # - lod_l : waits for adr (EA) and for LD Data
314 # - wri_l : waits for LD Data and Regfile (port 1)
315 # - st_l : waits for alu and operand2
316 # - rst_l : waits for all FSM paths to converge.
317 # NOTE: use sync to stop combinatorial loops.
319 # opcode latch - inverted so that busy resets to 0
320 # note this MUST be sync so as to avoid a combinatorial loop
321 # between busy_o and issue_i on the reset latch (rst_l)
322 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
323 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
326 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
327 sync
+= src_l
.r
.eq(reset_r
)
329 # alu latch. use sync-delay between alu_ok and valid to generate pulse
330 comb
+= alu_l
.s
.eq(reset_i
)
331 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
334 comb
+= adr_l
.s
.eq(reset_i
)
335 sync
+= adr_l
.r
.eq(reset_a
)
338 comb
+= lod_l
.s
.eq(reset_i
)
339 comb
+= lod_l
.r
.eq(ld_ok
)
342 comb
+= wri_l
.s
.eq(issue_i
)
343 sync
+= wri_l
.r
.eq(reset_w |
Repl(self
.done_o
, self
.n_dst
))
345 # update-mode operand latch (EA written to reg 2)
346 sync
+= upd_l
.s
.eq(reset_i
)
347 sync
+= upd_l
.r
.eq(reset_u
)
350 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
351 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
353 # ld/st done. needed to stop LD/ST from activating repeatedly
354 comb
+= lsd_l
.s
.eq(issue_i
)
355 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
358 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
359 comb
+= rst_l
.r
.eq(issue_i
)
361 # create a latch/register for the operand
362 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
363 with m
.If(self
.issue_i
):
364 sync
+= oper_r
.eq(self
.oper_i
)
367 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
368 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
370 # and for each input from the incoming src operands
372 for i
in range(self
.n_src
):
374 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
375 latchregister(m
, self
.src_i
[i
], src_r
, src_l
.q
[i
], name
+ '_l')
378 # and one for the output from the ADD (for the EA)
379 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
380 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
382 # select either zero or src1 if opcode says so
383 op_is_z
= oper_r
.zero_a
384 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
385 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
387 # select either immediate or src2 if opcode says so
388 op_is_imm
= oper_r
.imm_data
.imm_ok
389 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
390 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
, srl
[1]))
392 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
393 sync
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
394 sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
396 # decode bits of operand (latched)
397 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
398 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
399 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
400 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
401 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
402 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
403 comb
+= self
.ld_o
.eq(op_is_ld
)
404 comb
+= self
.st_o
.eq(op_is_st
)
406 ############################
407 # Control Signal calculation
411 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
413 # 1st operand read-request only when zero not active
414 # 2nd operand only needed when immediate is not active
415 slg
= Cat(op_is_z
, op_is_imm
)
416 bro
= Repl(self
.busy_o
, self
.n_src
)
417 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
419 # note when the address-related read "go" signals are active
420 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
422 # alu input valid when 1st and 2nd ops done (or imm not active)
423 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
425 # 3rd operand only needed when operation is a store
426 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
428 # all reads done when alu is valid and 3rd operand needed
429 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
431 # address release only if addr ready, but Port must be idle
432 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
434 # store release when st ready *and* all operands read (and no shadow)
435 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
438 # request write of LD result. waits until shadow is dropped.
439 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
440 op_is_ld
& self
.shadown_i
)
442 # request write of EA result only in update mode
443 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
444 alu_valid
& self
.shadown_i
)
446 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
447 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
448 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
449 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
450 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
452 (lod_l
.qn | op_is_st
))
453 comb
+= self
.done_o
.eq(wr_reset
)
455 ######################
456 # Data/Address outputs
458 # put the LD-output register directly onto the output bus on a go_write
459 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
460 with m
.If(self
.wr
.go_i
[0]):
461 comb
+= self
.dest
[0].eq(ldd_r
)
463 # "update" mode, put address out on 2nd go-write
464 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
465 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
466 comb
+= self
.dest
[1].eq(addr_r
)
468 # need to look like MultiCompUnit: put wrmask out.
469 # XXX may need to make this enable only when write active
470 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
472 ###########################
473 # PortInterface connections
476 # connect to LD/ST PortInterface.
477 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
478 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
479 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
480 # address: use sync to avoid long latency
481 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
482 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
483 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
484 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
487 with m
.If(oper_r
.byte_reverse
):
488 # byte-reverse the data based on ld/st width (turn it to LE)
489 data_len
= oper_r
.data_len
490 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
491 comb
+= ldd_o
.eq(lddata_r
) # put reversed- data out
493 comb
+= ldd_o
.eq(pi
.ld
.data
) # put data out, straight (as BE)
494 # ld - ld gets latched in via lod_l
495 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
498 op3
= srl
[2] # 3rd operand latch
499 with m
.If(oper_r
.byte_reverse
):
500 # byte-reverse the data based on width
501 data_len
= oper_r
.data_len
502 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
503 comb
+= pi
.st
.data
.eq(stdata_r
)
505 comb
+= pi
.st
.data
.eq(op3
)
506 # store - data goes in based on go_st
507 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
511 def get_out(self
, i
):
512 """make LDSTCompUnit look like RegSpecALUAPI"""
517 # return self.dest[i]
519 def get_fu_out(self
, i
):
520 return self
.get_out(i
)
530 yield from self
.oper_i
.ports()
531 yield from self
.src_i
537 yield from self
.data_o
.ports()
538 yield from self
.addr_o
.ports()
539 yield self
.load_mem_o
540 yield self
.stwd_mem_o
546 def wait_for(sig
, wait
=True, test1st
=False):
548 print("wait for", sig
, v
, wait
, test1st
)
549 if test1st
and bool(v
) == wait
:
554 #print("...wait for", sig, v)
559 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
561 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
562 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
563 yield dut
.oper_i
.data_len
.eq(2) # half-word
564 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
565 yield dut
.src1_i
.eq(src1
)
566 yield dut
.src2_i
.eq(src2
)
567 yield dut
.src3_i
.eq(src3
)
568 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
569 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
570 yield dut
.oper_i
.update
.eq(update
)
571 yield dut
.issue_i
.eq(1)
573 yield dut
.issue_i
.eq(0)
579 # wait for all active rel signals to come up
581 rel
= yield dut
.rd
.rel_o
582 if rel
== active_rel
:
585 yield dut
.rd
.go
.eq(active_rel
)
587 yield dut
.rd
.go
.eq(0)
589 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
590 # yield from wait_for(dut.adr_rel_o)
591 # yield dut.ad.go.eq(1)
593 # yield dut.ad.go.eq(0)
596 yield from wait_for(dut
.wr
.rel_o
[1])
597 yield dut
.wr
.go
.eq(0b10)
599 addr
= yield dut
.addr_o
601 yield dut
.wr
.go
.eq(0)
605 yield from wait_for(dut
.sto_rel_o
)
606 yield dut
.go_st_i
.eq(1)
608 yield dut
.go_st_i
.eq(0)
609 yield from wait_for(dut
.busy_o
, False)
610 # wait_for(dut.stwd_mem_o)
615 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
617 print("LD", src1
, src2
, imm
, imm_ok
, update
)
618 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
619 yield dut
.oper_i
.data_len
.eq(2) # half-word
620 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
621 yield dut
.src1_i
.eq(src1
)
622 yield dut
.src2_i
.eq(src2
)
623 yield dut
.oper_i
.zero_a
.eq(zero_a
)
624 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
625 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
626 yield dut
.issue_i
.eq(1)
628 yield dut
.issue_i
.eq(0)
631 # set up read-operand flags
633 if not imm_ok
: # no immediate means RB register needs to be read
635 if not zero_a
: # no zero-a means RA needs to be read
638 # wait for the operands (RA, RB, or both)
640 yield dut
.rd
.go
.eq(rd
)
641 yield from wait_for(dut
.rd
.rel_o
)
642 yield dut
.rd
.go
.eq(0)
644 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
645 # yield dut.ad.go.eq(1)
647 # yield dut.ad.go.eq(0)
650 yield from wait_for(dut
.wr
.rel_o
[1])
651 yield dut
.wr
.go
.eq(0b10)
653 addr
= yield dut
.addr_o
655 yield dut
.wr
.go
.eq(0)
659 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
660 yield dut
.wr
.go
.eq(1)
662 data
= yield dut
.data_o
664 yield dut
.wr
.go
.eq(0)
665 yield from wait_for(dut
.busy_o
)
667 # wait_for(dut.stwd_mem_o)
676 # two STs (different addresses)
677 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
678 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
680 # two LDs (deliberately LD from the 1st address then 2nd)
681 data
, addr
= yield from load(dut
, 4, 0, 2)
682 assert data
== 0x0003, "returned %x" % data
683 data
, addr
= yield from load(dut
, 2, 0, 2)
684 assert data
== 0x0009, "returned %x" % data
688 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
689 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
690 assert data
== 0x0003, "returned %x" % data
692 # update-immediate version
693 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
694 assert addr
== 0x000b, "returned %x" % addr
696 # update-indexed version
697 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
698 assert data
== 0x0003, "returned %x" % data
699 assert addr
== 0x000e, "returned %x" % addr
701 # immediate *and* zero version
702 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
703 assert data
== 0x0008, "returned %x" % data
706 class TestLDSTCompUnit(LDSTCompUnit
):
708 def __init__(self
, rwid
):
709 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
710 self
.l0
= l0
= TstL0CacheBuffer()
711 pi
= l0
.l0
.dports
[0].pi
712 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
714 def elaborate(self
, platform
):
715 m
= LDSTCompUnit
.elaborate(self
, platform
)
716 m
.submodules
.l0
= self
.l0
717 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
721 def test_scoreboard():
723 dut
= TestLDSTCompUnit(16)
724 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
725 with
open("test_ldst_comp.il", "w") as f
:
728 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
731 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
734 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
735 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
736 regspec
= LDSTPipeSpec
.regspec
737 self
.l0
= l0
= TstL0CacheBuffer()
738 pi
= l0
.l0
.dports
[0].pi
739 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
741 def elaborate(self
, platform
):
742 m
= LDSTCompUnit
.elaborate(self
, platform
)
743 m
.submodules
.l0
= self
.l0
744 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
748 def test_scoreboard_regspec():
750 dut
= TestLDSTCompUnitRegSpec()
751 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
752 with
open("test_ldst_comp.il", "w") as f
:
755 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
758 if __name__
== '__main__':
759 test_scoreboard_regspec()