630dc9b8984a7829bfa762b8c27d2c23277e6844
1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
88 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
89 from soc
.experiment
.l0_cache
import PortInterface
90 from soc
.fu
.regspec
import RegSpecAPI
92 from soc
.decoder
.power_enums
import InternalOp
, Function
93 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
94 from soc
.decoder
.power_decoder2
import Data
97 class LDSTCompUnitRecord(CompUnitRecord
):
98 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
99 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
100 n_src
=3, n_dst
=2, name
=name
)
102 self
.ad
= go_record(1, name
="ad") # address go in, req out
103 self
.st
= go_record(1, name
="st") # store go in, req out
105 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
107 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
108 self
.st_o
= Signal(reset_less
=True) # operation is a ST
110 # hmm... are these necessary?
111 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
112 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
115 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
116 """LOAD / STORE Computation Unit
121 * :pi: a PortInterface to the memory subsystem (read-write capable)
122 * :rwid: register width
123 * :awid: address width
127 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
131 * :data_o: Dest out (LD) - managed by wr[0] go/req
132 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
133 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
135 TODO: make addr_exc_o a data-type rather than a single-bit signal
141 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
142 * :issue_i: LD/ST is being "issued".
143 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
144 * :go_rd_i: read is being actioned (latches in src regs)
145 * :go_wr_i: write mode (exactly like ALU CompUnit)
146 * :go_ad_i: address is being actioned (triggers actual mem LD)
147 * :go_st_i: store is being actioned (triggers actual mem STORE)
148 * :go_die_i: resets the unit back to "wait for issue"
150 Control Signals (Out)
151 ---------------------
153 * :busy_o: function unit is busy
154 * :rd_rel_o: request src1/src2
155 * :adr_rel_o: request address (from mem)
156 * :sto_rel_o: request store (to mem)
157 * :req_rel_o: request write (result)
158 * :load_mem_o: activate memory LOAD
159 * :stwd_mem_o: activate memory STORE
161 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
162 in a single cycle and the CompUnit set back to doing another op.
163 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
164 depending on whether the operation is a ST or LD.
167 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
169 super().__init
__(rwid
)
172 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
)
173 self
.debugtest
= debugtest
175 # POWER-compliant LD/ST has index and update: *fixed* number of ports
176 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
177 self
.n_dst
= n_dst
= 2 # RA, RT/RS
179 # set up array of src and dest signals
180 for i
in range(n_src
):
181 j
= i
+ 1 # name numbering to match src1/src2
183 setattr(self
, name
, getattr(cu
, name
))
186 for i
in range(n_dst
):
187 j
= i
+ 1 # name numbering to match dest1/2...
188 name
= "dest%d_o" % j
189 setattr(self
, name
, getattr(cu
, name
))
194 self
.rdmaskn
= cu
.rdmaskn
195 self
.wrmask
= cu
.wrmask
200 # HACK: get data width from dest[0]. this is used across the board
201 # (it really shouldn't be)
202 self
.data_wid
= self
.dest
[0].shape()
204 self
.go_rd_i
= self
.rd
.go
# temporary naming
205 self
.go_wr_i
= self
.wr
.go
# temporary naming
206 self
.go_ad_i
= self
.ad
.go
# temp naming: go address in
207 self
.go_st_i
= self
.st
.go
# temp naming: go store in
209 self
.rd_rel_o
= self
.rd
.rel
# temporary naming
210 self
.req_rel_o
= self
.wr
.rel
# temporary naming
211 self
.adr_rel_o
= self
.ad
.rel
# request address (from mem)
212 self
.sto_rel_o
= self
.st
.rel
# request store (to mem)
214 self
.issue_i
= cu
.issue_i
215 self
.shadown_i
= cu
.shadown_i
216 self
.go_die_i
= cu
.go_die_i
218 self
.oper_i
= cu
.oper_i
219 self
.src_i
= cu
._src
_i
221 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
222 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
223 self
.addr_exc_o
= cu
.addr_exc_o
224 self
.done_o
= cu
.done_o
225 self
.busy_o
= cu
.busy_o
230 self
.load_mem_o
= cu
.load_mem_o
231 self
.stwd_mem_o
= cu
.stwd_mem_o
233 def elaborate(self
, platform
):
239 issue_i
= self
.issue_i
241 #####################
242 # latches for the FSM.
243 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
244 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
245 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
246 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
247 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
248 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
249 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
250 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
251 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
257 op_is_ld
= Signal(reset_less
=True)
258 op_is_st
= Signal(reset_less
=True)
260 # ALU/LD data output control
261 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
262 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
263 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
264 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
265 wr_any
= Signal(reset_less
=True) # any write (incl. store)
266 rda_any
= Signal(reset_less
=True) # any read for address ops
267 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
268 wr_reset
= Signal(reset_less
=True) # final reset condition
271 alu_o
= Signal(self
.data_wid
, reset_less
=True)
272 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
274 ##############################
275 # reset conditions for latches
277 # temporaries (also convenient when debugging)
278 reset_o
= Signal(reset_less
=True) # reset opcode
279 reset_w
= Signal(reset_less
=True) # reset write
280 reset_u
= Signal(reset_less
=True) # reset update
281 reset_a
= Signal(reset_less
=True) # reset adr latch
282 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
283 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
284 reset_s
= Signal(reset_less
=True) # reset store
286 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
287 comb
+= reset_o
.eq(wr_reset | self
.go_die_i
) # opcode reset
288 comb
+= reset_w
.eq(self
.wr
.go
[0] | self
.go_die_i
) # write reg 1
289 comb
+= reset_u
.eq(self
.wr
.go
[1] | self
.go_die_i
) # update (reg 2)
290 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
291 comb
+= reset_r
.eq(self
.rd
.go |
Repl(self
.go_die_i
, self
.n_src
))
292 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
294 ##########################
295 # FSM implemented through sequence of latches. approximately this:
297 # - src_l[0] : operands
299 # - alu_l : looks after add of src1/2/imm (EA)
300 # - adr_l : waits for add (EA)
301 # - upd_l : waits for adr and Regfile (port 2)
303 # - lod_l : waits for adr (EA) and for LD Data
304 # - wri_l : waits for LD Data and Regfile (port 1)
305 # - st_l : waits for alu and operand2
306 # - rst_l : waits for all FSM paths to converge.
307 # NOTE: use sync to stop combinatorial loops.
309 # opcode latch - inverted so that busy resets to 0
310 # note this MUST be sync so as to avoid a combinatorial loop
311 # between busy_o and issue_i on the reset latch (rst_l)
312 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
313 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
316 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
317 sync
+= src_l
.r
.eq(reset_r
)
319 # alu latch. use sync-delay between alu_ok and valid to generate pulse
320 comb
+= alu_l
.s
.eq(reset_i
)
321 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
324 comb
+= adr_l
.s
.eq(reset_i
)
325 sync
+= adr_l
.r
.eq(reset_a
)
328 comb
+= lod_l
.s
.eq(reset_i
)
329 comb
+= lod_l
.r
.eq(ld_ok
)
332 comb
+= wri_l
.s
.eq(issue_i
)
333 sync
+= wri_l
.r
.eq(reset_w |
Repl(self
.done_o
, self
.n_dst
))
335 # update-mode operand latch (EA written to reg 2)
336 sync
+= upd_l
.s
.eq(reset_i
)
337 sync
+= upd_l
.r
.eq(reset_u
)
340 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
341 sync
+= sto_l
.r
.eq(reset_s
)
344 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
345 comb
+= rst_l
.r
.eq(issue_i
)
347 # create a latch/register for the operand
348 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
349 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, name
="oper_l")
352 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
353 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
355 # and for each input from the incoming src operands
357 for i
in range(self
.n_src
):
359 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
360 latchregister(m
, self
.src_i
[i
], src_r
, src_l
.q
[i
], name
+ '_l')
363 # and one for the output from the ADD (for the EA)
364 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
365 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
367 # select either zero or src1 if opcode says so
368 op_is_z
= oper_r
.zero_a
369 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
370 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
372 # select either immediate or src2 if opcode says so
373 op_is_imm
= oper_r
.imm_data
.imm_ok
374 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
375 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
, srl
[1]))
377 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
378 sync
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
379 sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
381 # decode bits of operand (latched)
382 comb
+= op_is_st
.eq(oper_r
.insn_type
== InternalOp
.OP_STORE
) # ST
383 comb
+= op_is_ld
.eq(oper_r
.insn_type
== InternalOp
.OP_LOAD
) # LD
384 op_is_update
= oper_r
.update
# UPDATE
385 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
386 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
387 comb
+= self
.ld_o
.eq(op_is_ld
)
388 comb
+= self
.st_o
.eq(op_is_st
)
390 ############################
391 # Control Signal calculation
395 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
397 # 1st operand read-request only when zero not active
398 # 2nd operand only needed when immediate is not active
399 slg
= Cat(op_is_z
, op_is_imm
)
400 bro
= Repl(self
.busy_o
, self
.n_src
)
401 comb
+= self
.rd
.rel
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
403 # note when the address-related read "go" signals are active
404 comb
+= rda_any
.eq(self
.rd
.go
[0] | self
.rd
.go
[1])
406 # alu input valid when 1st and 2nd ops done (or imm not active)
407 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel
[0] | self
.rd
.rel
[1]))
409 # 3rd operand only needed when operation is a store
410 comb
+= self
.rd
.rel
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
412 # all reads done when alu is valid and 3rd operand needed
413 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel
[2])
415 # address release only if addr ready, but Port must be idle
416 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
418 # store release when st ready *and* all operands read (and no shadow)
419 comb
+= self
.st
.rel
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
422 # request write of LD result. waits until shadow is dropped.
423 comb
+= self
.wr
.rel
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
424 op_is_ld
& self
.shadown_i
)
426 # request write of EA result only in update mode
427 comb
+= self
.wr
.rel
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
430 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
431 comb
+= wr_any
.eq(self
.st
.go | self
.wr
.go
[0] | self
.wr
.go
[1])
432 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
433 ~
(self
.st
.rel | self
.wr
.rel
[0] | self
.wr
.rel
[1]) &
434 (lod_l
.qn | op_is_st
))
435 comb
+= self
.done_o
.eq(wr_reset
)
437 ######################
438 # Data/Address outputs
440 # put the LD-output register directly onto the output bus on a go_write
441 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
442 with m
.If(self
.wr
.go
[0]):
443 comb
+= self
.dest
[0].eq(ldd_r
)
445 # "update" mode, put address out on 2nd go-write
446 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
447 with m
.If(op_is_update
& self
.wr
.go
[1]):
448 comb
+= self
.dest
[1].eq(addr_r
)
450 # need to look like MultiCompUnit: put wrmask out.
451 # XXX may need to make this enable only when write active
452 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
454 ###########################
455 # PortInterface connections
458 # connect to LD/ST PortInterface.
459 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
460 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
461 comb
+= pi
.op
.eq(self
.oper_i
) # op details (not all needed)
463 comb
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
464 comb
+= pi
.addr
.ok
.eq(alu_ok
& lod_l
.q
) # "go do address stuff"
465 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
466 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
467 # ld - ld gets latched in via lod_l
468 comb
+= ldd_o
.eq(pi
.ld
.data
) # ld data goes into ld reg (above)
469 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
470 # store - data goes in based on go_st
471 comb
+= pi
.st
.data
.eq(srl
[2]) # 3rd operand latch
472 comb
+= pi
.st
.ok
.eq(self
.st
.go
) # go store signals st data valid
476 def get_out(self
, i
):
477 """make LDSTCompUnit look like RegSpecALUAPI"""
492 yield from self
.oper_i
.ports()
493 yield from self
.src_i
499 yield from self
.data_o
.ports()
500 yield from self
.addr_o
.ports()
501 yield self
.load_mem_o
502 yield self
.stwd_mem_o
508 def wait_for(sig
, wait
=True, test1st
=False):
510 print("wait for", sig
, v
, wait
, test1st
)
511 if test1st
and bool(v
) == wait
:
516 #print("...wait for", sig, v)
521 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False):
522 print ("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
523 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_STORE
)
524 yield dut
.oper_i
.data_len
.eq(2) # half-word
525 yield dut
.src1_i
.eq(src1
)
526 yield dut
.src2_i
.eq(src2
)
527 yield dut
.src3_i
.eq(src3
)
528 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
529 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
530 yield dut
.oper_i
.update
.eq(update
)
531 yield dut
.issue_i
.eq(1)
533 yield dut
.issue_i
.eq(0)
536 yield dut
.rd
.go
.eq(0b101)
538 yield dut
.rd
.go
.eq(0b111)
539 yield from wait_for(dut
.rd
.rel
)
540 yield dut
.rd
.go
.eq(0)
542 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
543 #yield from wait_for(dut.adr_rel_o)
544 #yield dut.ad.go.eq(1)
546 #yield dut.ad.go.eq(0)
549 yield from wait_for(dut
.wr
.rel
[1])
550 yield dut
.wr
.go
.eq(0b10)
552 addr
= yield dut
.addr_o
554 yield dut
.wr
.go
.eq(0)
558 yield from wait_for(dut
.sto_rel_o
)
559 yield dut
.go_st_i
.eq(1)
561 yield dut
.go_st_i
.eq(0)
562 yield from wait_for(dut
.busy_o
, False)
563 #wait_for(dut.stwd_mem_o)
568 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False):
569 print ("LD", src1
, src2
, imm
, imm_ok
, update
)
570 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_LOAD
)
571 yield dut
.oper_i
.data_len
.eq(2) # half-word
572 yield dut
.src1_i
.eq(src1
)
573 yield dut
.src2_i
.eq(src2
)
574 yield dut
.oper_i
.zero_a
.eq(zero_a
)
575 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
576 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
577 yield dut
.issue_i
.eq(1)
579 yield dut
.issue_i
.eq(0)
588 yield dut
.rd
.go
.eq(rd
)
589 yield from wait_for(dut
.rd
.rel
)
590 yield dut
.rd
.go
.eq(0)
592 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
593 #yield dut.ad.go.eq(1)
595 #yield dut.ad.go.eq(0)
598 yield from wait_for(dut
.wr
.rel
[1])
599 yield dut
.wr
.go
.eq(0b10)
601 addr
= yield dut
.addr_o
603 yield dut
.wr
.go
.eq(0)
607 yield from wait_for(dut
.wr
.rel
[0], test1st
=True)
608 yield dut
.wr
.go
.eq(1)
610 data
= yield dut
.data_o
612 yield dut
.wr
.go
.eq(0)
613 yield from wait_for(dut
.busy_o
)
615 # wait_for(dut.stwd_mem_o)
624 # two STs (different addresses)
625 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
626 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
628 # two LDs (deliberately LD from the 1st address then 2nd)
629 data
, addr
= yield from load(dut
, 4, 0, 2)
630 assert data
== 0x0003, "returned %x" % data
631 data
, addr
= yield from load(dut
, 2, 0, 2)
632 assert data
== 0x0009, "returned %x" % data
636 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
637 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
638 assert data
== 0x0003, "returned %x" % data
640 # update-immediate version
641 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
642 assert addr
== 0x000b, "returned %x" % addr
644 # update-indexed version
645 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
646 assert data
== 0x0003, "returned %x" % data
647 assert addr
== 0x000e, "returned %x" % addr
649 # immediate *and* zero version
650 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
651 assert data
== 0x0008, "returned %x" % data
654 class TestLDSTCompUnit(LDSTCompUnit
):
656 def __init__(self
, rwid
):
657 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
658 self
.l0
= l0
= TstL0CacheBuffer()
659 pi
= l0
.l0
.dports
[0].pi
660 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
662 def elaborate(self
, platform
):
663 m
= LDSTCompUnit
.elaborate(self
, platform
)
664 m
.submodules
.l0
= self
.l0
665 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
669 def test_scoreboard():
671 dut
= TestLDSTCompUnit(16)
672 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
673 with
open("test_ldst_comp.il", "w") as f
:
676 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
679 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
682 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
683 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
684 regspec
= LDSTPipeSpec
.regspec
685 self
.l0
= l0
= TstL0CacheBuffer()
686 pi
= l0
.l0
.dports
[0].pi
687 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
689 def elaborate(self
, platform
):
690 m
= LDSTCompUnit
.elaborate(self
, platform
)
691 m
.submodules
.l0
= self
.l0
692 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
696 def test_scoreboard_regspec():
698 dut
= TestLDSTCompUnitRegSpec()
699 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
700 with
open("test_ldst_comp.il", "w") as f
:
703 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
706 if __name__
== '__main__':
707 test_scoreboard_regspec()