1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 TODO: dcbz, yes, that's going to be complicated, has to be done
24 with great care, to detect the case when dcbz is set
25 and *not* expect to read any data, just the address.
26 so, wait for RA but not RB.
28 Both LD and ST may request that the address be computed from summing
29 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
30 the immediate (from the opcode).
32 Both LD and ST may also request "update" mode (op_is_update) which
33 activates the use of Go_Write[1] to control storage of the EA into
34 a *second* operand in the register file.
36 Thus this module has *TWO* write-requests to the register file and
37 *THREE* read-requests to the register file (not all at the same time!)
38 The regfile port usage is:
50 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
51 is not suited to (nmigen.FSM is clock-driven, and some aspects of
52 the nested FSMs below are *combinatorial*).
54 * One FSM covers Operand collection and communication address-side
55 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
57 * A second FSM activates to cover LD. it activates if op_is_ld is true
59 * A third FSM activates to cover ST. it activates if op_is_st is true
61 * TODO document DCBZ (not complete yet)
63 * The "overall" (fourth) FSM coordinates the progression and completion
64 of the three other FSMs, firing "WR_RESET" which switches off "busy"
68 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
70 Links including to walk-through videos:
72 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
73 * http://libre-soc.org/openpower/isa/fixedload
74 * http://libre-soc.org/openpower/isa/fixedstore
78 * https://bugs.libre-soc.org/show_bug.cgi?id=302
79 * https://bugs.libre-soc.org/show_bug.cgi?id=216
83 * EA - Effective Address
88 from nmigen
.compat
.sim
import run_simulation
89 from nmigen
.cli
import verilog
, rtlil
90 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
91 from nmigen
.hdl
.rec
import Record
, Layout
93 from nmutil
.latch
import SRLatch
, latchregister
94 from nmutil
.byterev
import byte_reverse
95 from nmutil
.extend
import exts
97 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
98 from soc
.experiment
.l0_cache
import PortInterface
99 from soc
.experiment
.pimem
import LDSTException
100 from soc
.fu
.regspec
import RegSpecAPI
102 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
103 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
104 from openpower
.decoder
.power_decoder2
import Data
105 from openpower
.consts
import MSR
106 from soc
.config
.test
.test_loadstore
import TestMemPspec
109 from nmutil
.util
import Display
112 # TODO: LDSTInputData and LDSTOutputData really should be used
113 # here, to make things more like the other CompUnits. currently,
114 # also, RegSpecAPI is used explicitly here
117 class LDSTCompUnitRecord(CompUnitRecord
):
118 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
119 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
120 n_src
=3, n_dst
=2, name
=name
)
122 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
123 self
.st
= go_record(1, name
="cu_st") # store go in, req out
125 self
.exc_o
= LDSTException("exc_o")
127 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
128 self
.st_o
= Signal(reset_less
=True) # operation is a ST
130 # hmm... are these necessary?
131 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
132 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
135 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
136 """LOAD / STORE Computation Unit
141 * :pi: a PortInterface to the memory subsystem (read-write capable)
142 * :rwid: register width
143 * :awid: address width
147 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
151 * :o_data: Dest out (LD) - managed by wr[0] go/req
152 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
153 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
155 TODO: make exc_o a data-type rather than a single-bit signal
161 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
162 * :issue_i: LD/ST is being "issued".
163 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
164 * :go_rd_i: read is being actioned (latches in src regs)
165 * :go_wr_i: write mode (exactly like ALU CompUnit)
166 * :go_ad_i: address is being actioned (triggers actual mem LD)
167 * :go_st_i: store is being actioned (triggers actual mem STORE)
168 * :go_die_i: resets the unit back to "wait for issue"
170 Control Signals (Out)
171 ---------------------
173 * :busy_o: function unit is busy
174 * :rd_rel_o: request src1/src2
175 * :adr_rel_o: request address (from mem)
176 * :sto_rel_o: request store (to mem)
177 * :req_rel_o: request write (result)
178 * :load_mem_o: activate memory LOAD
179 * :stwd_mem_o: activate memory STORE
181 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
182 in a single cycle and the CompUnit set back to doing another op.
183 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
184 depending on whether the operation is a ST or LD.
186 Note: LDSTCompUnit takes care of LE/BE normalisation:
187 * LD data is normalised after receipt from the PortInterface
188 * ST data is normalised *prior* to sending onto the PortInterface
189 TODO: use one module for the byte-reverse as it's quite expensive in gates
192 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
193 debugtest
=False, name
=None):
194 super().__init
__(rwid
)
197 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
198 self
.debugtest
= debugtest
200 # POWER-compliant LD/ST has index and update: *fixed* number of ports
201 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
202 self
.n_dst
= n_dst
= 2 # RA, RT/RS
204 # set up array of src and dest signals
205 for i
in range(n_src
):
206 j
= i
+ 1 # name numbering to match src1/src2
208 setattr(self
, name
, getattr(cu
, name
))
211 for i
in range(n_dst
):
212 j
= i
+ 1 # name numbering to match dest1/2...
213 name
= "dest%d_o" % j
214 setattr(self
, name
, getattr(cu
, name
))
219 self
.rdmaskn
= cu
.rdmaskn
220 self
.wrmask
= cu
.wrmask
225 # HACK: get data width from dest[0]. this is used across the board
226 # (it really shouldn't be)
227 self
.data_wid
= self
.dest
[0].shape()
229 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
230 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
231 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
232 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
234 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
235 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
236 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
237 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
239 self
.issue_i
= cu
.issue_i
240 self
.shadown_i
= cu
.shadown_i
241 self
.go_die_i
= cu
.go_die_i
243 self
.oper_i
= cu
.oper_i
244 self
.src_i
= cu
._src
_i
246 self
.o_data
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
247 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
248 self
.exc_o
= cu
.exc_o
249 self
.done_o
= cu
.done_o
250 self
.busy_o
= cu
.busy_o
255 self
.load_mem_o
= cu
.load_mem_o
256 self
.stwd_mem_o
= cu
.stwd_mem_o
258 def elaborate(self
, platform
):
264 issue_i
= self
.issue_i
266 #####################
267 # latches for the FSM.
268 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
269 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
270 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
271 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
272 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
273 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
274 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
275 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
276 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
277 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
283 op_is_ld
= Signal(reset_less
=True)
284 op_is_st
= Signal(reset_less
=True)
285 op_is_dcbz
= Signal(reset_less
=True)
287 # ALU/LD data output control
288 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
289 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
290 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
291 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
292 wr_any
= Signal(reset_less
=True) # any write (incl. store)
293 rda_any
= Signal(reset_less
=True) # any read for address ops
294 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
295 wr_reset
= Signal(reset_less
=True) # final reset condition
298 alu_o
= Signal(self
.data_wid
, reset_less
=True)
299 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
301 ##############################
302 # reset conditions for latches
304 # temporaries (also convenient when debugging)
305 reset_o
= Signal(reset_less
=True) # reset opcode
306 reset_w
= Signal(reset_less
=True) # reset write
307 reset_u
= Signal(reset_less
=True) # reset update
308 reset_a
= Signal(reset_less
=True) # reset adr latch
309 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
310 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
311 reset_s
= Signal(reset_less
=True) # reset store
313 # end execution when a terminating condition is detected:
314 # - go_die_i: a speculative operation was cancelled
315 # - exc_o.happened: an exception has occurred
317 comb
+= terminate
.eq(self
.go_die_i | self
.exc_o
.happened
)
319 comb
+= reset_i
.eq(issue_i | terminate
) # various
320 comb
+= reset_o
.eq(self
.done_o | terminate
) # opcode reset
321 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | terminate
) # write reg 1
322 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | terminate
) # update (reg 2)
323 comb
+= reset_s
.eq(self
.go_st_i | terminate
) # store reset
324 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(terminate
, self
.n_src
))
325 comb
+= reset_a
.eq(self
.go_ad_i | terminate
)
327 p_st_go
= Signal(reset_less
=True)
328 sync
+= p_st_go
.eq(self
.st
.go_i
)
330 # decode bits of operand (latched)
331 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
332 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
333 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
334 comb
+= op_is_dcbz
.eq(oper_r
.insn_type
== MicrOp
.OP_DCBZ
) # DCBZ
336 #comb += Display("compldst_multi: op_is_dcbz = %i",
337 # (oper_r.insn_type == MicrOp.OP_DCBZ))
338 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
339 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
340 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
341 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
342 comb
+= self
.ld_o
.eq(op_is_ld
)
343 comb
+= self
.st_o
.eq(op_is_st
)
345 ##########################
346 # FSM implemented through sequence of latches. approximately this:
348 # - src_l[0] : operands
350 # - alu_l : looks after add of src1/2/imm (EA)
351 # - adr_l : waits for add (EA)
352 # - upd_l : waits for adr and Regfile (port 2)
354 # - lod_l : waits for adr (EA) and for LD Data
355 # - wri_l : waits for LD Data and Regfile (port 1)
356 # - st_l : waits for alu and operand2
357 # - rst_l : waits for all FSM paths to converge.
358 # NOTE: use sync to stop combinatorial loops.
360 # opcode latch - inverted so that busy resets to 0
361 # note this MUST be sync so as to avoid a combinatorial loop
362 # between busy_o and issue_i on the reset latch (rst_l)
363 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
364 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
367 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
368 sync
+= src_l
.r
.eq(reset_r
)
370 # alu latch. use sync-delay between alu_ok and valid to generate pulse
371 comb
+= alu_l
.s
.eq(reset_i
)
372 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
375 comb
+= adr_l
.s
.eq(reset_i
)
376 sync
+= adr_l
.r
.eq(reset_a
)
379 comb
+= lod_l
.s
.eq(reset_i
)
380 comb
+= lod_l
.r
.eq(ld_ok
)
383 comb
+= wri_l
.s
.eq(issue_i
)
384 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
385 (~self
.pi
.busy_o
& op_is_update
),
386 #(self.pi.busy_o & op_is_update),
387 #self.done_o | (self.pi.busy_o & op_is_update),
390 # update-mode operand latch (EA written to reg 2)
391 sync
+= upd_l
.s
.eq(reset_i
)
392 sync
+= upd_l
.r
.eq(reset_u
)
395 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
396 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
398 # ld/st done. needed to stop LD/ST from activating repeatedly
399 comb
+= lsd_l
.s
.eq(issue_i
)
400 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
403 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
404 comb
+= rst_l
.r
.eq(issue_i
)
406 # create a latch/register for the operand
407 with m
.If(self
.issue_i
):
408 sync
+= oper_r
.eq(self
.oper_i
)
409 with m
.If(self
.done_o | terminate
):
413 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
414 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
416 # and for each input from the incoming src operands
418 for i
in range(self
.n_src
):
420 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
421 with m
.If(self
.rd
.go_i
[i
]):
422 sync
+= src_r
.eq(self
.src_i
[i
])
423 with m
.If(self
.issue_i
):
427 # and one for the output from the ADD (for the EA)
428 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
429 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
431 # select either zero or src1 if opcode says so
432 op_is_z
= oper_r
.zero_a
433 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
434 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
436 # select either immediate or src2 if opcode says so
437 op_is_imm
= oper_r
.imm_data
.ok
438 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
439 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
441 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
442 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
443 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
445 ############################
446 # Control Signal calculation
450 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
452 # 1st operand read-request only when zero not active
453 # 2nd operand only needed when immediate is not active
454 slg
= Cat(op_is_z
, op_is_imm
)
455 bro
= Repl(self
.busy_o
, self
.n_src
)
456 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
458 # note when the address-related read "go" signals are active
459 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
461 # alu input valid when 1st and 2nd ops done (or imm not active)
462 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
464 # 3rd operand only needed when operation is a store
465 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
467 # all reads done when alu is valid and 3rd operand needed
468 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
470 # address release only if addr ready, but Port must be idle
471 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
473 # the write/store (etc) all must be cancelled if an exception occurs
474 # note: cancel is active low, like shadown_i,
475 # while exc_o.happpened is active high
476 cancel
= Signal(reset_less
=True)
477 comb
+= cancel
.eq(~self
.exc_o
.happened
& self
.shadown_i
)
479 # store release when st ready *and* all operands read (and no shadow)
480 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
483 # request write of LD result. waits until shadow is dropped.
484 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
487 # request write of EA result only in update mode
488 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
491 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
492 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
493 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
494 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& cancel
&
495 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
497 (lod_l
.qn | op_is_st
)
499 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
501 ######################
502 # Data/Address outputs
504 # put the LD-output register directly onto the output bus on a go_write
505 comb
+= self
.o_data
.data
.eq(self
.dest
[0])
506 with m
.If(self
.wr
.go_i
[0]):
507 comb
+= self
.dest
[0].eq(ldd_r
)
509 # "update" mode, put address out on 2nd go-write
510 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
511 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
512 comb
+= self
.dest
[1].eq(addr_r
)
514 # need to look like MultiCompUnit: put wrmask out.
515 # XXX may need to make this enable only when write active
516 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
518 ###########################
519 # PortInterface connections
522 # connect to LD/ST PortInterface.
523 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
524 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
525 comb
+= pi
.is_dcbz_i
.eq(op_is_dcbz
& busy_o
) # decoded-DCBZ
526 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
527 # address: use sync to avoid long latency
528 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
529 sync
+= Display("EA from adder %i op_is_dcbz %i",addr_r
,op_is_dcbz
)
530 ## do not use ### sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
532 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
533 comb
+= self
.exc_o
.eq(pi
.exc_o
) # exception occurred
534 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
535 # connect MSR.PR for priv/virt operation
536 comb
+= pi
.msr_pr
.eq(oper_r
.msr
[MSR
.PR
])
539 revnorev
= Signal(64, reset_less
=True)
540 with m
.If(oper_r
.byte_reverse
):
541 # byte-reverse the data based on ld/st width (turn it to LE)
542 data_len
= oper_r
.data_len
543 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
544 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
546 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
548 # then check sign-extend
549 with m
.If(oper_r
.sign_extend
):
550 # okok really should "if data_len == 4" and so on here
551 with m
.If(oper_r
.data_len
== 2):
552 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
554 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
556 comb
+= ldd_o
.eq(revnorev
)
558 # ld - ld gets latched in via lod_l
559 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
562 op3
= srl
[2] # 3rd operand latch
563 with m
.If(oper_r
.byte_reverse
):
564 # byte-reverse the data based on width
565 data_len
= oper_r
.data_len
566 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
567 comb
+= pi
.st
.data
.eq(stdata_r
)
569 comb
+= pi
.st
.data
.eq(op3
)
570 # store - data goes in based on go_st
571 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
575 def get_out(self
, i
):
576 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
577 to LDSTOutputData o and o1 respectively.
580 return self
.o_data
# LDSTOutputData.regspec o
582 return self
.addr_o
# LDSTOutputData.regspec o1
583 # return self.dest[i]
585 def get_fu_out(self
, i
):
586 return self
.get_out(i
)
596 yield from self
.oper_i
.ports()
597 yield from self
.src_i
603 yield from self
.o_data
.ports()
604 yield from self
.addr_o
.ports()
605 yield self
.load_mem_o
606 yield self
.stwd_mem_o
612 def wait_for(sig
, wait
=True, test1st
=False):
614 print("wait for", sig
, v
, wait
, test1st
)
615 if test1st
and bool(v
) == wait
:
620 #print("...wait for", sig, v)
625 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
627 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
628 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
629 yield dut
.oper_i
.data_len
.eq(2) # half-word
630 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
631 yield dut
.src1_i
.eq(src1
)
632 yield dut
.src2_i
.eq(src2
)
633 yield dut
.src3_i
.eq(src3
)
634 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
635 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
636 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
637 yield dut
.issue_i
.eq(1)
639 yield dut
.issue_i
.eq(0)
645 # wait for all active rel signals to come up
647 rel
= yield dut
.rd
.rel_o
648 if rel
== active_rel
:
651 yield dut
.rd
.go_i
.eq(active_rel
)
653 yield dut
.rd
.go_i
.eq(0)
655 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
656 # yield from wait_for(dut.adr_rel_o)
657 # yield dut.ad.go.eq(1)
659 # yield dut.ad.go.eq(0)
662 yield from wait_for(dut
.wr
.rel_o
[1])
663 yield dut
.wr
.go
.eq(0b10)
665 addr
= yield dut
.addr_o
667 yield dut
.wr
.go
.eq(0)
671 yield from wait_for(dut
.sto_rel_o
)
672 yield dut
.go_st_i
.eq(1)
674 yield dut
.go_st_i
.eq(0)
675 yield from wait_for(dut
.busy_o
, False)
676 # wait_for(dut.stwd_mem_o)
681 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
683 print("LD", src1
, src2
, imm
, imm_ok
, update
)
684 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
685 yield dut
.oper_i
.data_len
.eq(2) # half-word
686 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
687 yield dut
.src1_i
.eq(src1
)
688 yield dut
.src2_i
.eq(src2
)
689 yield dut
.oper_i
.zero_a
.eq(zero_a
)
690 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
691 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
692 yield dut
.issue_i
.eq(1)
694 yield dut
.issue_i
.eq(0)
697 # set up read-operand flags
699 if not imm_ok
: # no immediate means RB register needs to be read
701 if not zero_a
: # no zero-a means RA needs to be read
704 # wait for the operands (RA, RB, or both)
706 yield dut
.rd
.go_i
.eq(rd
)
707 yield from wait_for(dut
.rd
.rel_o
)
708 yield dut
.rd
.go_i
.eq(0)
710 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
711 # yield dut.ad.go.eq(1)
713 # yield dut.ad.go.eq(0)
716 yield from wait_for(dut
.wr
.rel_o
[1])
717 yield dut
.wr
.go
.eq(0b10)
719 addr
= yield dut
.addr_o
721 yield dut
.wr
.go
.eq(0)
725 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
726 yield dut
.wr
.go
.eq(1)
728 data
= yield dut
.o_data
730 yield dut
.wr
.go
.eq(0)
731 yield from wait_for(dut
.busy_o
)
733 # wait_for(dut.stwd_mem_o)
742 # two STs (different addresses)
743 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
744 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
746 # two LDs (deliberately LD from the 1st address then 2nd)
747 data
, addr
= yield from load(dut
, 4, 0, 2)
748 assert data
== 0x0003, "returned %x" % data
749 data
, addr
= yield from load(dut
, 2, 0, 2)
750 assert data
== 0x0009, "returned %x" % data
754 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
755 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
756 assert data
== 0x0003, "returned %x" % data
758 # update-immediate version
759 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
760 assert addr
== 0x000b, "returned %x" % addr
762 # update-indexed version
763 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
764 assert data
== 0x0003, "returned %x" % data
765 assert addr
== 0x000e, "returned %x" % addr
767 # immediate *and* zero version
768 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
769 assert data
== 0x0008, "returned %x" % data
772 class TestLDSTCompUnit(LDSTCompUnit
):
774 def __init__(self
, rwid
, pspec
):
775 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
776 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
778 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
780 def elaborate(self
, platform
):
781 m
= LDSTCompUnit
.elaborate(self
, platform
)
782 m
.submodules
.l0
= self
.l0
783 # link addr-go direct to rel
784 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
788 def test_scoreboard():
791 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
792 imem_ifacetype
='bare_wb',
798 dut
= TestLDSTCompUnit(16,pspec
)
799 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
800 with
open("test_ldst_comp.il", "w") as f
:
803 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
806 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
808 def __init__(self
, pspec
):
809 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
810 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
811 regspec
= LDSTPipeSpec
.regspec
812 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
814 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
816 def elaborate(self
, platform
):
817 m
= LDSTCompUnit
.elaborate(self
, platform
)
818 m
.submodules
.l0
= self
.l0
819 # link addr-go direct to rel
820 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
824 def test_scoreboard_regspec():
827 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
828 imem_ifacetype
='bare_wb',
834 dut
= TestLDSTCompUnitRegSpec(pspec
)
835 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
836 with
open("test_ldst_comp.il", "w") as f
:
839 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
842 if __name__
== '__main__':
843 test_scoreboard_regspec()