1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 TODO: dcbz, yes, that's going to be complicated, has to be done
24 with great care, to detect the case when dcbz is set
25 and *not* expect to read any data, just the address.
26 so, wait for RA but not RB.
28 Both LD and ST may request that the address be computed from summing
29 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
30 the immediate (from the opcode).
32 Both LD and ST may also request "update" mode (op_is_update) which
33 activates the use of Go_Write[1] to control storage of the EA into
34 a *second* operand in the register file.
36 Thus this module has *TWO* write-requests to the register file and
37 *THREE* read-requests to the register file (not all at the same time!)
38 The regfile port usage is:
50 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
51 is not suited to (nmigen.FSM is clock-driven, and some aspects of
52 the nested FSMs below are *combinatorial*).
54 * One FSM covers Operand collection and communication address-side
55 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
57 * A second FSM activates to cover LD. it activates if op_is_ld is true
59 * A third FSM activates to cover ST. it activates if op_is_st is true
61 * TODO document DCBZ (not complete yet)
63 * The "overall" (fourth) FSM coordinates the progression and completion
64 of the three other FSMs, firing "WR_RESET" which switches off "busy"
68 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
70 Links including to walk-through videos:
72 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
73 * http://libre-soc.org/openpower/isa/fixedload
74 * http://libre-soc.org/openpower/isa/fixedstore
78 * https://bugs.libre-soc.org/show_bug.cgi?id=302
79 * https://bugs.libre-soc.org/show_bug.cgi?id=216
83 * EA - Effective Address
88 from nmigen
.compat
.sim
import run_simulation
89 from nmigen
.cli
import verilog
, rtlil
90 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
91 from nmigen
.hdl
.rec
import Record
, Layout
93 from nmutil
.latch
import SRLatch
, latchregister
94 from nmutil
.byterev
import byte_reverse
95 from nmutil
.extend
import exts
97 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
98 from soc
.experiment
.l0_cache
import PortInterface
99 from soc
.experiment
.pimem
import LDSTException
100 from soc
.fu
.regspec
import RegSpecAPI
102 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
103 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
104 from openpower
.decoder
.power_decoder2
import Data
105 from openpower
.consts
import MSR
106 from soc
.config
.test
.test_loadstore
import TestMemPspec
109 from nmutil
.util
import Display
112 # TODO: LDSTInputData and LDSTOutputData really should be used
113 # here, to make things more like the other CompUnits. currently,
114 # also, RegSpecAPI is used explicitly here
117 class LDSTCompUnitRecord(CompUnitRecord
):
118 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
119 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
120 n_src
=3, n_dst
=2, name
=name
)
122 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
123 self
.st
= go_record(1, name
="cu_st") # store go in, req out
125 self
.exc_o
= LDSTException("exc_o")
127 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
128 self
.st_o
= Signal(reset_less
=True) # operation is a ST
130 # hmm... are these necessary?
131 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
132 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
135 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
136 """LOAD / STORE Computation Unit
141 * :pi: a PortInterface to the memory subsystem (read-write capable)
142 * :rwid: register width
143 * :awid: address width
147 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
151 * :o_data: Dest out (LD) - managed by wr[0] go/req
152 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
153 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
155 TODO: make exc_o a data-type rather than a single-bit signal
161 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
162 * :issue_i: LD/ST is being "issued".
163 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
164 * :go_rd_i: read is being actioned (latches in src regs)
165 * :go_wr_i: write mode (exactly like ALU CompUnit)
166 * :go_ad_i: address is being actioned (triggers actual mem LD)
167 * :go_st_i: store is being actioned (triggers actual mem STORE)
168 * :go_die_i: resets the unit back to "wait for issue"
170 Control Signals (Out)
171 ---------------------
173 * :busy_o: function unit is busy
174 * :rd_rel_o: request src1/src2
175 * :adr_rel_o: request address (from mem)
176 * :sto_rel_o: request store (to mem)
177 * :req_rel_o: request write (result)
178 * :load_mem_o: activate memory LOAD
179 * :stwd_mem_o: activate memory STORE
181 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
182 in a single cycle and the CompUnit set back to doing another op.
183 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
184 depending on whether the operation is a ST or LD.
186 Note: LDSTCompUnit takes care of LE/BE normalisation:
187 * LD data is normalised after receipt from the PortInterface
188 * ST data is normalised *prior* to sending onto the PortInterface
189 TODO: use one module for the byte-reverse as it's quite expensive in gates
192 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
193 debugtest
=False, name
=None):
194 super().__init
__(rwid
)
197 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
198 self
.debugtest
= debugtest
# enable debug output for unit testing
200 # POWER-compliant LD/ST has index and update: *fixed* number of ports
201 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
202 self
.n_dst
= n_dst
= 2 # RA, RT/RS
204 # set up array of src and dest signals
205 for i
in range(n_src
):
206 j
= i
+ 1 # name numbering to match src1/src2
208 setattr(self
, name
, getattr(cu
, name
))
211 for i
in range(n_dst
):
212 j
= i
+ 1 # name numbering to match dest1/2...
213 name
= "dest%d_o" % j
214 setattr(self
, name
, getattr(cu
, name
))
219 self
.rdmaskn
= cu
.rdmaskn
220 self
.wrmask
= cu
.wrmask
225 # HACK: get data width from dest[0]. this is used across the board
226 # (it really shouldn't be)
227 self
.data_wid
= self
.dest
[0].shape()
229 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
230 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
231 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
232 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
234 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
235 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
236 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
237 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
239 self
.issue_i
= cu
.issue_i
240 self
.shadown_i
= cu
.shadown_i
241 self
.go_die_i
= cu
.go_die_i
243 self
.oper_i
= cu
.oper_i
244 self
.src_i
= cu
._src
_i
246 self
.o_data
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
247 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
248 self
.exc_o
= cu
.exc_o
249 self
.done_o
= cu
.done_o
250 self
.busy_o
= cu
.busy_o
255 self
.load_mem_o
= cu
.load_mem_o
256 self
.stwd_mem_o
= cu
.stwd_mem_o
258 def elaborate(self
, platform
):
264 issue_i
= self
.issue_i
266 #####################
267 # latches for the FSM.
268 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
269 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
270 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
271 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
272 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
273 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
274 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
275 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
276 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
277 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
283 op_is_ld
= Signal(reset_less
=True)
284 op_is_st
= Signal(reset_less
=True)
285 op_is_dcbz
= Signal(reset_less
=True)
286 op_is_st_or_dcbz
= Signal(reset_less
=True)
288 # ALU/LD data output control
289 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
290 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
291 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
292 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
293 wr_any
= Signal(reset_less
=True) # any write (incl. store)
294 rda_any
= Signal(reset_less
=True) # any read for address ops
295 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
296 wr_reset
= Signal(reset_less
=True) # final reset condition
299 alu_o
= Signal(self
.data_wid
, reset_less
=True)
300 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
302 ##############################
303 # reset conditions for latches
305 # temporaries (also convenient when debugging)
306 reset_o
= Signal(reset_less
=True) # reset opcode
307 reset_w
= Signal(reset_less
=True) # reset write
308 reset_u
= Signal(reset_less
=True) # reset update
309 reset_a
= Signal(reset_less
=True) # reset adr latch
310 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
311 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
312 reset_s
= Signal(reset_less
=True) # reset store
314 # end execution when a terminating condition is detected:
315 # - go_die_i: a speculative operation was cancelled
316 # - exc_o.happened: an exception has occurred
318 comb
+= terminate
.eq(self
.go_die_i | self
.exc_o
.happened
)
320 comb
+= reset_i
.eq(issue_i | terminate
) # various
321 comb
+= reset_o
.eq(self
.done_o | terminate
) # opcode reset
322 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | terminate
) # write reg 1
323 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | terminate
) # update (reg 2)
324 comb
+= reset_s
.eq(self
.go_st_i | terminate
) # store reset
325 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(terminate
, self
.n_src
))
326 comb
+= reset_a
.eq(self
.go_ad_i | terminate
)
328 p_st_go
= Signal(reset_less
=True)
329 sync
+= p_st_go
.eq(self
.st
.go_i
)
331 # decode bits of operand (latched)
332 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
333 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
334 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
335 comb
+= op_is_dcbz
.eq(oper_r
.insn_type
== MicrOp
.OP_DCBZ
) # DCBZ
336 comb
+= op_is_st_or_dcbz
.eq(op_is_st | op_is_dcbz
)
337 # dcbz is special case of store
339 #comb += Display("compldst_multi: op_is_dcbz = %i",
340 # (oper_r.insn_type == MicrOp.OP_DCBZ))
341 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
342 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
343 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
344 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
345 comb
+= self
.ld_o
.eq(op_is_ld
)
346 comb
+= self
.st_o
.eq(op_is_st
)
348 ##########################
349 # FSM implemented through sequence of latches. approximately this:
351 # - src_l[0] : operands
353 # - alu_l : looks after add of src1/2/imm (EA)
354 # - adr_l : waits for add (EA)
355 # - upd_l : waits for adr and Regfile (port 2)
357 # - lod_l : waits for adr (EA) and for LD Data
358 # - wri_l : waits for LD Data and Regfile (port 1)
359 # - st_l : waits for alu and operand2
360 # - rst_l : waits for all FSM paths to converge.
361 # NOTE: use sync to stop combinatorial loops.
363 # opcode latch - inverted so that busy resets to 0
364 # note this MUST be sync so as to avoid a combinatorial loop
365 # between busy_o and issue_i on the reset latch (rst_l)
366 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
367 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
370 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
371 sync
+= src_l
.r
.eq(reset_r
)
372 #### sync += Display("reset_r = %i",reset_r)
374 # alu latch. use sync-delay between alu_ok and valid to generate pulse
375 comb
+= alu_l
.s
.eq(reset_i
)
376 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
379 comb
+= adr_l
.s
.eq(reset_i
)
380 sync
+= adr_l
.r
.eq(reset_a
)
383 comb
+= lod_l
.s
.eq(reset_i
)
384 comb
+= lod_l
.r
.eq(ld_ok
)
387 comb
+= wri_l
.s
.eq(issue_i
)
388 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
389 (~self
.pi
.busy_o
& op_is_update
),
390 #(self.pi.busy_o & op_is_update),
391 #self.done_o | (self.pi.busy_o & op_is_update),
394 # update-mode operand latch (EA written to reg 2)
395 sync
+= upd_l
.s
.eq(reset_i
)
396 sync
+= upd_l
.r
.eq(reset_u
)
399 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st_or_dcbz
)
400 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
402 # ld/st done. needed to stop LD/ST from activating repeatedly
403 comb
+= lsd_l
.s
.eq(issue_i
)
404 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
407 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
408 comb
+= rst_l
.r
.eq(issue_i
)
410 # create a latch/register for the operand
411 with m
.If(self
.issue_i
):
412 sync
+= oper_r
.eq(self
.oper_i
)
413 with m
.If(self
.done_o | terminate
):
417 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
418 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
420 # and for each input from the incoming src operands
422 for i
in range(self
.n_src
):
424 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
425 with m
.If(self
.rd
.go_i
[i
]):
426 sync
+= src_r
.eq(self
.src_i
[i
])
427 with m
.If(self
.issue_i
):
431 # and one for the output from the ADD (for the EA)
432 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
433 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
435 # select either zero or src1 if opcode says so
436 op_is_z
= oper_r
.zero_a
437 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
438 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
440 # select either immediate or src2 if opcode says so
441 op_is_imm
= oper_r
.imm_data
.ok
442 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
443 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
445 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
446 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
447 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
449 ############################
450 # Control Signal calculation
454 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
456 # 1st operand read-request only when zero not active
457 # 2nd operand only needed when immediate is not active
458 slg
= Cat(op_is_z
, op_is_imm
) #is this correct ?
459 bro
= Repl(self
.busy_o
, self
.n_src
)
460 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
462 # note when the address-related read "go" signals are active
463 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
465 # alu input valid when 1st and 2nd ops done (or imm not active)
466 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
468 # 3rd operand only needed when operation is a store
469 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
471 # all reads done when alu is valid and 3rd operand needed
472 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
474 # address release only if addr ready, but Port must be idle
475 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
477 # the write/store (etc) all must be cancelled if an exception occurs
478 # note: cancel is active low, like shadown_i,
479 # while exc_o.happpened is active high
480 cancel
= Signal(reset_less
=True)
481 comb
+= cancel
.eq(~self
.exc_o
.happened
& self
.shadown_i
)
483 # store release when st ready *and* all operands read (and no shadow)
484 # dcbz is special case of store -- TODO verify shadows
485 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st_or_dcbz
&
488 # request write of LD result. waits until shadow is dropped.
489 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
492 # request write of EA result only in update mode
493 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
496 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
497 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
498 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
499 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& cancel
&
500 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
502 (lod_l
.qn | op_is_st_or_dcbz
)
504 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
506 ######################
507 # Data/Address outputs
509 # put the LD-output register directly onto the output bus on a go_write
510 comb
+= self
.o_data
.data
.eq(self
.dest
[0])
511 with m
.If(self
.wr
.go_i
[0]):
512 comb
+= self
.dest
[0].eq(ldd_r
)
514 # "update" mode, put address out on 2nd go-write
515 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
516 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
517 comb
+= self
.dest
[1].eq(addr_r
)
519 # need to look like MultiCompUnit: put wrmask out.
520 # XXX may need to make this enable only when write active
521 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
523 ###########################
524 # PortInterface connections
527 # connect to LD/ST PortInterface.
528 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
529 comb
+= pi
.is_st_i
.eq(op_is_st_or_dcbz
& busy_o
) # decoded-ST
530 comb
+= pi
.is_dcbz_i
.eq(op_is_dcbz
& busy_o
) # decoded-DCBZ
531 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
532 # address: use sync to avoid long latency
533 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
534 with m
.If(op_is_dcbz
):
535 sync
+= Display("DCBZ: EA from adder %i",addr_r
)
537 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
538 comb
+= self
.exc_o
.eq(pi
.exc_o
) # exception occurred
539 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
540 # connect MSR.PR for priv/virt operation
541 comb
+= pi
.msr_pr
.eq(oper_r
.msr
[MSR
.PR
])
544 revnorev
= Signal(64, reset_less
=True)
545 with m
.If(oper_r
.byte_reverse
):
546 # byte-reverse the data based on ld/st width (turn it to LE)
547 data_len
= oper_r
.data_len
548 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
549 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
551 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
553 # then check sign-extend
554 with m
.If(oper_r
.sign_extend
):
555 # okok really should "if data_len == 4" and so on here
556 with m
.If(oper_r
.data_len
== 2):
557 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
559 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
561 comb
+= ldd_o
.eq(revnorev
)
563 # ld - ld gets latched in via lod_l
564 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
567 op3
= srl
[2] # 3rd operand latch
568 with m
.If(oper_r
.byte_reverse
):
569 # byte-reverse the data based on width
570 data_len
= oper_r
.data_len
571 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
572 comb
+= pi
.st
.data
.eq(stdata_r
)
574 comb
+= pi
.st
.data
.eq(op3
)
575 # store - data goes in based on go_st
576 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
580 def get_out(self
, i
):
581 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
582 to LDSTOutputData o and o1 respectively.
585 return self
.o_data
# LDSTOutputData.regspec o
587 return self
.addr_o
# LDSTOutputData.regspec o1
588 # return self.dest[i]
590 def get_fu_out(self
, i
):
591 return self
.get_out(i
)
601 yield from self
.oper_i
.ports()
602 yield from self
.src_i
608 yield from self
.o_data
.ports()
609 yield from self
.addr_o
.ports()
610 yield self
.load_mem_o
611 yield self
.stwd_mem_o
617 def wait_for(sig
, wait
=True, test1st
=False):
619 print("wait for", sig
, v
, wait
, test1st
)
620 if test1st
and bool(v
) == wait
:
625 #print("...wait for", sig, v)
630 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
632 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
633 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
634 yield dut
.oper_i
.data_len
.eq(2) # half-word
635 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
636 yield dut
.src1_i
.eq(src1
)
637 yield dut
.src2_i
.eq(src2
)
638 yield dut
.src3_i
.eq(src3
)
639 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
640 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
641 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
642 yield dut
.issue_i
.eq(1)
644 yield dut
.issue_i
.eq(0)
650 # wait for all active rel signals to come up
652 rel
= yield dut
.rd
.rel_o
653 if rel
== active_rel
:
656 yield dut
.rd
.go_i
.eq(active_rel
)
658 yield dut
.rd
.go_i
.eq(0)
660 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
661 # yield from wait_for(dut.adr_rel_o)
662 # yield dut.ad.go.eq(1)
664 # yield dut.ad.go.eq(0)
667 yield from wait_for(dut
.wr
.rel_o
[1])
668 yield dut
.wr
.go
.eq(0b10)
670 addr
= yield dut
.addr_o
672 yield dut
.wr
.go
.eq(0)
676 yield from wait_for(dut
.sto_rel_o
)
677 yield dut
.go_st_i
.eq(1)
679 yield dut
.go_st_i
.eq(0)
680 yield from wait_for(dut
.busy_o
, False)
681 # wait_for(dut.stwd_mem_o)
686 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
688 print("LD", src1
, src2
, imm
, imm_ok
, update
)
689 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
690 yield dut
.oper_i
.data_len
.eq(2) # half-word
691 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
692 yield dut
.src1_i
.eq(src1
)
693 yield dut
.src2_i
.eq(src2
)
694 yield dut
.oper_i
.zero_a
.eq(zero_a
)
695 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
696 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
697 yield dut
.issue_i
.eq(1)
699 yield dut
.issue_i
.eq(0)
702 # set up read-operand flags
704 if not imm_ok
: # no immediate means RB register needs to be read
706 if not zero_a
: # no zero-a means RA needs to be read
709 # wait for the operands (RA, RB, or both)
711 yield dut
.rd
.go_i
.eq(rd
)
712 yield from wait_for(dut
.rd
.rel_o
)
713 yield dut
.rd
.go_i
.eq(0)
715 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
716 # yield dut.ad.go.eq(1)
718 # yield dut.ad.go.eq(0)
721 yield from wait_for(dut
.wr
.rel_o
[1])
722 yield dut
.wr
.go_i
.eq(0b10)
724 addr
= yield dut
.addr_o
726 yield dut
.wr
.go_i
.eq(0)
730 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
731 yield dut
.wr
.go_i
.eq(1)
733 data
= yield dut
.o_data
.o
734 data_ok
= yield dut
.o_data
.o_ok
735 yield dut
.wr
.go_i
.eq(0)
736 yield from wait_for(dut
.busy_o
)
738 # wait_for(dut.stwd_mem_o)
739 return data
, data_ok
, addr
747 # two STs (different addresses)
748 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
749 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
751 # two LDs (deliberately LD from the 1st address then 2nd)
752 data
, addr
= yield from load(dut
, 4, 0, 2)
753 assert data
== 0x0003, "returned %x" % data
754 data
, addr
= yield from load(dut
, 2, 0, 2)
755 assert data
== 0x0009, "returned %x" % data
759 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
760 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
761 assert data
== 0x0003, "returned %x" % data
763 # update-immediate version
764 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
765 assert addr
== 0x000b, "returned %x" % addr
767 # update-indexed version
768 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
769 assert data
== 0x0003, "returned %x" % data
770 assert addr
== 0x000e, "returned %x" % addr
772 # immediate *and* zero version
773 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
774 assert data
== 0x0008, "returned %x" % data
777 class TestLDSTCompUnit(LDSTCompUnit
):
779 def __init__(self
, rwid
, pspec
):
780 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
781 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
783 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
785 def elaborate(self
, platform
):
786 m
= LDSTCompUnit
.elaborate(self
, platform
)
787 m
.submodules
.l0
= self
.l0
788 # link addr-go direct to rel
789 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
793 def test_scoreboard():
796 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
797 imem_ifacetype
='bare_wb',
803 dut
= TestLDSTCompUnit(16,pspec
)
804 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
805 with
open("test_ldst_comp.il", "w") as f
:
808 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
811 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
813 def __init__(self
, pspec
):
814 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
815 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
816 regspec
= LDSTPipeSpec
.regspec
817 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
819 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
821 def elaborate(self
, platform
):
822 m
= LDSTCompUnit
.elaborate(self
, platform
)
823 m
.submodules
.l0
= self
.l0
824 # link addr-go direct to rel
825 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
829 def test_scoreboard_regspec():
832 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
833 imem_ifacetype
='bare_wb',
839 dut
= TestLDSTCompUnitRegSpec(pspec
)
840 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
841 with
open("test_ldst_comp.il", "w") as f
:
844 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
847 if __name__
== '__main__':
848 test_scoreboard_regspec()