src/soc/experiment/pi2ls.py

   1 """PortInterface to LoadStoreUnitInterface adapter
   2
   3     PortInterface   LoadStoreUnitInterface
   4     -------------   ----------------------
   5
   6     is_ld_i/1       x_ld_i
   7     is_st_i/1       x_st_i
   8
   9     data_len/4      x_mask/16  (translate using LenExpand)
  10
  11     busy_o/1        most likely to be x_busy_o
  12     go_die_i/1      rst?
  13     addr.data/48    x_addr_i (x_addr_i[:4] goes into LenExpand)
  14     addr.ok/1       probably x_valid_i & ~x_stall_i
  15
  16     addr_ok_o/1     no equivalent.  *might* work using x_stall_i
  17     addr_exc_o/2(?) m_load_err_o and m_store_err_o
  18
  19     ld.data/64      m_ld_data_o
  20     ld.ok/1         probably implicit, when x_busy drops low
  21     st.data/64      x_st_data_i
  22     st.ok/1         probably kinda redundant, set to x_st_i
  23 """
  24
  25 from soc.minerva.units.loadstore import LoadStoreUnitInterface
  26 from soc.experiment.pimem import PortInterface
  27 from soc.scoreboard.addr_match import LenExpand
  28 from nmigen.utils import log2_int
  29
  30 from nmigen import Elaboratable, Module, Signal
  31
  32
  33 class Pi2LSUI(Elaboratable):
  34
  35     def __init__(self, name, pi=None, lsui=None,
  36                              regwid=64, mask_wid=8, addrwid=48):
  37         self.addrbits = mask_wid
  38         if pi is None:
  39             pi = PortInterface(name="%s_pi", regwid=regwid, addrwid=addrwid)
  40         self.pi = pi
  41         if lsui is None:
  42             lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
  43         self.lsui = lsui
  44
  45     def splitaddr(self, addr):
  46         """split the address into top and bottom bits of the memory granularity
  47         """
  48         return addr[:self.addrbits], addr[self.addrbits:]
  49
  50     def elaborate(self, platform):
  51         m = Module()
  52         pi, lsui, addrbits = self.pi, self.lsui, self.addrbits
  53         m.submodules.lenexp = lenexp = LenExpand(log2_int(self.addrbits), 8)
  54
  55         ld_in_progress = Signal(reset=0)
  56
  57         m.d.comb += lsui.x_ld_i.eq(pi.is_ld_i)
  58         m.d.comb += lsui.x_st_i.eq(pi.is_st_i)
  59         m.d.comb += pi.busy_o.eq(lsui.x_busy_o)
  60
  61         with m.If(pi.addr.ok):
  62             # expand the LSBs of address plus LD/ST len into 16-bit mask
  63             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
  64             m.d.comb += lenexp.len_i.eq(pi.data_len)
  65             m.d.comb += lenexp.addr_i.eq(lsbaddr) # LSBs of addr
  66             m.d.comb += lsui.x_mask_i.eq(lenexp.lexp_o)
  67             # pass through the address, indicate "valid"
  68             m.d.comb += lsui.x_addr_i.eq(msbaddr) # XXX hmmm...
  69             m.d.comb += lsui.x_valid_i.eq(1)
  70             # indicate "OK" - XXX should be checking address valid
  71             m.d.comb += pi.addr_ok_o.eq(1)
  72
  73         with m.If(pi.is_ld_i):
  74             # shift/mask out the loaded data
  75             m.d.comb += pi.ld.data.eq((lsui.m_ld_data_o & lenexp.rexp_o) >>
  76                                       (lenexp.addr_i*8))
  77             # remember we're in the process of loading
  78             m.d.sync += ld_in_progress.eq(1)
  79
  80         # If a load happened on the previous cycle and the memory is
  81         # not busy, that means it returned the data from the load. In
  82         # that case ld.ok should be set andwe can clear the
  83         # ld_in_progress flag
  84         with m.If(ld_in_progress & ~lsui.x_busy_o):
  85             m.d.comb += pi.ld.ok.eq(1)
  86             m.d.sync += ld_in_progress.eq(0)
  87         with m.Else():
  88             m.d.comb += pi.ld.ok.eq(0)
  89
  90         with m.If(pi.is_st_i & pi.st.ok):
  91             m.d.comb += lsui.x_st_data_i.eq(pi.st.data << (lenexp.addr_i*8))
  92
  93         return m