22788af24c45222d68690cb8b5121f845ec1d642
3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
19 from nmigen
.compat
.sim
import run_simulation
, Settle
20 from nmigen
.cli
import rtlil
21 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Cat
, Const
22 from nmutil
.iocontrol
import RecordObject
23 from nmigen
.utils
import log2_int
25 from nmutil
.latch
import SRLatch
, latchregister
26 from nmutil
.util
import rising_edge
27 from openpower
.decoder
.power_decoder2
import Data
28 from openpower
.decoder
.power_enums
import MSRSpec
29 from soc
.scoreboard
.addr_match
import LenExpand
30 from soc
.experiment
.mem_types
import LDSTException
32 # for testing purposes
33 from soc
.experiment
.testmem
import TestMemory
34 #from soc.scoreboard.addr_split import LDSTSplitter
35 from nmutil
.util
import Display
40 class PortInterface(RecordObject
):
43 defines the interface - the API - that the LDSTCompUnit connects
44 to. note that this is NOT a "fire-and-forget" interface. the
45 LDSTCompUnit *must* be kept appraised that the request is in
46 progress, and only when it has a 100% successful completion
47 can the notification be given (busy dropped).
49 The interface FSM rules are as follows:
51 * if busy_o is asserted, a LD/ST is in progress. further
52 requests may not be made until busy_o is deasserted.
54 * only one of is_ld_i or is_st_i may be asserted. busy_o
55 will immediately be asserted and remain asserted.
57 * addr.ok is to be asserted when the LD/ST address is known.
58 addr.data is to be valid on the same cycle.
60 addr.ok and addr.data must REMAIN asserted until busy_o
61 is de-asserted. this ensures that there is no need
62 for the L0 Cache/Buffer to have an additional address latch
63 (because the LDSTCompUnit already has it)
65 * addr_ok_o (or exception.happened) must be waited for. these will
66 be asserted *only* for one cycle and one cycle only.
68 * exception.happened will be asserted if there is no chance that the
69 memory request may be fulfilled.
71 busy_o is deasserted on the same cycle as exception.happened is asserted.
73 * conversely: addr_ok_o must *ONLY* be asserted if there is a
74 HUNDRED PERCENT guarantee that the memory request will be
77 * for a LD, ld.ok will be asserted - for only one clock cycle -
78 at any point in the future that is acceptable to the underlying
79 Memory subsystem. the recipient MUST latch ld.data on that cycle.
81 busy_o is deasserted on the same cycle as ld.ok is asserted.
83 * for a ST, st.ok may be asserted only after addr_ok_o had been
84 asserted, alongside valid st.data at the same time. st.ok
85 must only be asserted for one cycle.
87 the underlying Memory is REQUIRED to pick up that data and
88 guarantee its delivery. no back-acknowledgement is required.
90 busy_o is deasserted on the cycle AFTER st.ok is asserted.
93 def __init__(self
, name
=None, regwid
=64, addrwid
=64):
96 self
._addrwid
= addrwid
98 RecordObject
.__init
__(self
, name
=name
)
100 # distinguish op type (ld/st)
101 self
.is_ld_i
= Signal(reset_less
=True)
102 self
.is_st_i
= Signal(reset_less
=True)
104 # LD/ST data length (TODO: other things may be needed)
105 self
.data_len
= Signal(4, reset_less
=True)
108 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
109 self
.go_die_i
= Signal(reset_less
=True) # back to reset
110 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
111 # addr is valid (TLB, L1 etc.)
112 self
.addr_ok_o
= Signal(reset_less
=True)
113 self
.exc_o
= LDSTException("exc")
116 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
117 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
120 self
.is_nc
= Signal() # no cacheing
122 #only priv_mode = not msr_pr is used currently
123 # TODO: connect signals
124 self
.virt_mode
= Signal() # ctrl.msr(MSR_DR);
125 self
.priv_mode
= Signal() # not ctrl.msr(MSR_PR);
126 self
.mode_32bit
= Signal() # not ctrl.msr(MSR_SF);
128 self
.is_dcbz_i
= Signal(reset_less
=True)
131 self
.mmu_done
= Signal() # keep for now
134 self
.ldst_error
= Signal()
135 ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
136 self
.cache_paradox
= Signal()
138 def connect_port(self
, inport
):
139 print("connect_port", self
, inport
)
140 return [self
.is_ld_i
.eq(inport
.is_ld_i
),
141 self
.is_st_i
.eq(inport
.is_st_i
),
142 self
.is_nc
.eq(inport
.is_nc
),
143 self
.is_dcbz_i
.eq(inport
.is_dcbz_i
),
144 self
.data_len
.eq(inport
.data_len
),
145 self
.go_die_i
.eq(inport
.go_die_i
),
146 self
.addr
.data
.eq(inport
.addr
.data
),
147 self
.addr
.ok
.eq(inport
.addr
.ok
),
148 self
.st
.eq(inport
.st
),
149 self
.virt_mode
.eq(inport
.virt_mode
),
150 self
.priv_mode
.eq(inport
.priv_mode
),
151 self
.mode_32bit
.eq(inport
.mode_32bit
),
152 inport
.ld
.eq(self
.ld
),
153 inport
.busy_o
.eq(self
.busy_o
),
154 inport
.addr_ok_o
.eq(self
.addr_ok_o
),
155 inport
.exc_o
.eq(self
.exc_o
),
156 inport
.mmu_done
.eq(self
.mmu_done
),
157 inport
.ldst_error
.eq(self
.ldst_error
),
158 inport
.cache_paradox
.eq(self
.cache_paradox
)
162 class PortInterfaceBase(Elaboratable
):
165 Base class for PortInterface-compliant Memory read/writers
168 def __init__(self
, regwid
=64, addrwid
=4):
170 self
.addrwid
= addrwid
171 self
.pi
= PortInterface("ldst_port0", regwid
, addrwid
)
175 return log2_int(self
.regwid
//8)
177 def splitaddr(self
, addr
):
178 """split the address into top and bottom bits of the memory granularity
180 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
182 def connect_port(self
, inport
):
183 return self
.pi
.connect_port(inport
)
185 def set_wr_addr(self
, m
, addr
, mask
, misalign
, msr
, is_dcbz
): pass
186 def set_rd_addr(self
, m
, addr
, mask
, misalign
, msr
): pass
187 def set_wr_data(self
, m
, data
, wen
): pass
188 def get_rd_data(self
, m
): pass
190 def elaborate(self
, platform
):
192 comb
, sync
= m
.d
.comb
, m
.d
.sync
194 # state-machine latches
195 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
196 m
.submodules
.st_done
= st_done
= SRLatch(False, name
="st_done")
197 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
198 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
199 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
200 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
201 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
205 sync
+= st_done
.s
.eq(0)
206 comb
+= st_done
.r
.eq(0)
207 comb
+= st_active
.r
.eq(0)
208 comb
+= ld_active
.r
.eq(0)
209 comb
+= cyc_l
.s
.eq(0)
210 comb
+= cyc_l
.r
.eq(0)
211 comb
+= busy_l
.s
.eq(0)
212 comb
+= busy_l
.r
.eq(0)
213 sync
+= adrok_l
.s
.eq(0)
214 comb
+= adrok_l
.r
.eq(0)
216 # expand ld/st binary length/addr[:3] into unary bitmap
217 m
.submodules
.lenexp
= lenexp
= LenExpand(4, 8)
219 lds
= Signal(reset_less
=True)
220 sts
= Signal(reset_less
=True)
222 comb
+= lds
.eq(pi
.is_ld_i
) # ld-req signals
223 comb
+= sts
.eq(pi
.is_st_i
) # st-req signals
225 # TODO: construct an MSRspec here and pass it over in
226 # self.set_rd_addr and set_wr_addr below rather than just pr
230 msr
= MSRSpec(pr
=pr
, dr
=dr
, sf
=sf
)
233 busy_delay
= Signal()
235 sync
+= busy_delay
.eq(pi
.busy_o
)
236 comb
+= busy_edge
.eq(pi
.busy_o
& ~busy_delay
)
238 # misalignment detection: bits at end of lenexpand are set.
239 # when using the L0CacheBuffer "data expander" which splits requests
240 # into *two* PortInterfaces, this acts as a "safety check".
242 comb
+= misalign
.eq(lenexp
.lexp_o
[8:].bool())
245 # activate mode: only on "edge"
246 comb
+= ld_active
.s
.eq(rising_edge(m
, lds
)) # activate LD mode
247 comb
+= st_active
.s
.eq(rising_edge(m
, sts
)) # activate ST mode
249 # LD/ST requested activates "busy" (only if not already busy)
250 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
251 comb
+= busy_l
.s
.eq(~busy_delay
)
252 with m
.If(self
.pi
.exc_o
.happened
):
253 sync
+= Display("fast exception")
255 # if now in "LD" mode: wait for addr_ok, then send the address out
256 # to memory, acknowledge address, and send out LD data
257 with m
.If(ld_active
.q
):
258 # set up LenExpander with the LD len and lower bits of addr
259 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
260 comb
+= lenexp
.len_i
.eq(pi
.data_len
)
261 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
262 with m
.If(pi
.addr
.ok
& adrok_l
.qn
):
263 self
.set_rd_addr(m
, pi
.addr
.data
, lenexp
.lexp_o
, misalign
, msr
)
264 comb
+= pi
.addr_ok_o
.eq(1) # acknowledge addr ok
265 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
267 # if now in "ST" mode: likewise do the same but with "ST"
268 # to memory, acknowledge address, and send out LD data
269 with m
.If(st_active
.q
):
270 # set up LenExpander with the ST len and lower bits of addr
271 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
272 comb
+= lenexp
.len_i
.eq(pi
.data_len
)
273 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
274 with m
.If(pi
.addr
.ok
):
275 self
.set_wr_addr(m
, pi
.addr
.data
, lenexp
.lexp_o
, misalign
, msr
,
277 with m
.If(adrok_l
.qn
& self
.pi
.exc_o
.happened
==0):
278 comb
+= pi
.addr_ok_o
.eq(1) # acknowledge addr ok
279 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
281 # for LD mode, when addr has been "ok'd", assume that (because this
282 # is a "Memory" test-class) the memory read data is valid.
283 comb
+= reset_l
.s
.eq(0)
284 comb
+= reset_l
.r
.eq(0)
285 lddata
= Signal(self
.regwid
, reset_less
=True)
286 data
, ldok
= self
.get_rd_data(m
)
287 comb
+= lddata
.eq((data
& lenexp
.rexp_o
) >>
289 with m
.If(ld_active
.q
& adrok_l
.q
):
290 # shift data down before pushing out. requires masking
291 # from the *byte*-expanded version of LenExpand output
292 comb
+= pi
.ld
.data
.eq(lddata
) # put data out
293 comb
+= pi
.ld
.ok
.eq(ldok
) # indicate data valid
294 comb
+= reset_l
.s
.eq(ldok
) # reset mode after 1 cycle
296 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
297 sync
+= st_done
.s
.eq(0) # store done trigger
298 with m
.If(st_active
.q
& pi
.st
.ok
):
299 # shift data up before storing. lenexp *bit* version of mask is
300 # passed straight through as byte-level "write-enable" lines.
301 stdata
= Signal(self
.regwid
, reset_less
=True)
302 comb
+= stdata
.eq(pi
.st
.data
<< (lenexp
.addr_i
*8))
303 # TODO: replace with link to LoadStoreUnitInterface.x_store_data
304 # and also handle the ready/stall/busy protocol
305 stok
= self
.set_wr_data(m
, stdata
, lenexp
.lexp_o
)
306 sync
+= st_done
.s
.eq(~self
.pi
.exc_o
.happened
) # store done trigger
307 with m
.If(st_done
.q
):
308 comb
+= reset_l
.s
.eq(stok
) # reset mode after 1 cycle
310 # ugly hack, due to simultaneous addr req-go acknowledge
311 reset_delay
= Signal(reset_less
=True)
312 sync
+= reset_delay
.eq(reset_l
.q
)
313 with m
.If(reset_delay
):
314 comb
+= adrok_l
.r
.eq(1) # address reset
316 # after waiting one cycle (reset_l is "sync" mode), reset the port
317 with m
.If(reset_l
.q
):
318 comb
+= ld_active
.r
.eq(1) # leave the LD active for 1 cycle
319 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
320 comb
+= reset_l
.r
.eq(1) # clear reset
321 comb
+= adrok_l
.r
.eq(1) # address reset
322 comb
+= st_done
.r
.eq(1) # store done reset
324 # monitor for an exception, clear busy immediately
325 with m
.If(self
.pi
.exc_o
.happened
):
326 comb
+= busy_l
.r
.eq(1)
327 comb
+= reset_l
.s
.eq(1) # also reset whole unit
329 # however ST needs one cycle before busy is reset
330 #with m.If(self.pi.st.ok | self.pi.ld.ok):
331 with m
.If(reset_l
.s
):
332 comb
+= cyc_l
.s
.eq(1)
335 comb
+= cyc_l
.r
.eq(1)
336 comb
+= busy_l
.r
.eq(1)
338 # busy latch outputs to interface
339 if hasattr(self
, "external_busy"):
340 # when there is an extra (external) busy, include that here.
341 # this is used e.g. in LoadStore1 when an instruction fault
342 # is being processed (instr_fault) and stops Load/Store requests
343 # from being made until it's done
344 comb
+= pi
.busy_o
.eq(busy_l
.q | self
.external_busy(m
))
346 comb
+= pi
.busy_o
.eq(busy_l
.q
)
351 yield from self
.pi
.ports()
354 class TestMemoryPortInterface(PortInterfaceBase
):
355 """TestMemoryPortInterface
357 This is a test class for simple verification of the LDSTCompUnit
358 and for the simple core, to be able to run unit tests rapidly and
359 with less other code in the way.
361 Versions of this which are *compatible* (conform with PortInterface)
362 will include augmented-Wishbone Bus versions, including ones that
363 connect to L1, L2, MMU etc. etc. however this is the "base lowest
364 possible version that complies with PortInterface".
367 def __init__(self
, regwid
=64, addrwid
=4):
368 super().__init
__(regwid
, addrwid
)
369 # hard-code memory addressing width to 6 bits
370 self
.mem
= TestMemory(regwid
, 5, granularity
=regwid
//8, init
=False)
372 def set_wr_addr(self
, m
, addr
, mask
, misalign
, msr
, is_dcbz
):
373 lsbaddr
, msbaddr
= self
.splitaddr(addr
)
374 m
.d
.comb
+= self
.mem
.wrport
.addr
.eq(msbaddr
)
376 def set_rd_addr(self
, m
, addr
, mask
, misalign
, msr
):
377 lsbaddr
, msbaddr
= self
.splitaddr(addr
)
378 m
.d
.comb
+= self
.mem
.rdport
.addr
.eq(msbaddr
)
380 def set_wr_data(self
, m
, data
, wen
):
381 m
.d
.comb
+= self
.mem
.wrport
.data
.eq(data
) # write st to mem
382 m
.d
.comb
+= self
.mem
.wrport
.en
.eq(wen
) # enable writes
385 def get_rd_data(self
, m
):
386 return self
.mem
.rdport
.data
, Const(1, 1)
388 def elaborate(self
, platform
):
389 m
= super().elaborate(platform
)
391 # add TestMemory as submodule
392 m
.submodules
.mem
= self
.mem
397 yield from super().ports()