src/soc/experiment/test/test_ldst_pi_misalign.py

   1 """MMU PortInterface Test
   2
   3 quite basic, goes directly to the MMU to assert signals (does not
   4 yet use PortInterface)
   5 """
   6
   7 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   8 from nmigen.cli import main
   9 from nmigen.cli import rtlil
  10 from nmutil.mask import Mask, masked
  11 from nmutil.util import Display
  12
  13 if True:
  14     from nmigen.back.pysim import Simulator, Delay, Settle
  15 else:
  16     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  17 from nmutil.util import wrap
  18
  19 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.config.loadstore import ConfigMemoryPortInterface
  22
  23 from soc.fu.ldst.loadstore import LoadStore1
  24 from soc.experiment.mmu import MMU
  25
  26 from nmigen.compat.sim import run_simulation
  27 from openpower.test.wb_get import wb_get
  28 from openpower.test import wb_get as wbget
  29
  30
  31 wbget.stop = False
  32
  33 def b(x): # byte-reverse function
  34     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  35                           byteorder='big', signed=False)
  36
  37
  38 def setup_mmu():
  39
  40     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  41                          imem_ifacetype='',
  42                          addr_wid=48,
  43                          #disable_cache=True, # hmmm...
  44                          mask_wid=8,
  45                          reg_wid=64)
  46
  47     m = Module()
  48     comb = m.d.comb
  49     cmpi = ConfigMemoryPortInterface(pspec)
  50     m.submodules.ldst = ldst = cmpi.pi
  51     m.submodules.mmu = mmu = MMU()
  52     dcache = ldst.dcache
  53
  54     l_in, l_out = mmu.l_in, mmu.l_out
  55     d_in, d_out = dcache.d_in, dcache.d_out
  56
  57     # link mmu and dcache together
  58     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  59     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
  60
  61     # link ldst and MMU together
  62     comb += l_in.eq(ldst.m_out)
  63     comb += ldst.m_in.eq(l_out)
  64
  65     return m, cmpi
  66
  67
  68
  69 def ldst_sim_misalign(dut):
  70     mmu = dut.submodules.mmu
  71     wbget.stop = False
  72
  73     yield mmu.rin.prtbl.eq(0x1000000) # set process table
  74     yield
  75
  76     # load 8 bytes at aligned address
  77     align_addr = 0x1000
  78     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  79                                           align_addr, 8, msr_pr=1)
  80     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  81     assert data == 0xdeadbeef01234567
  82
  83     # load 4 bytes at aligned address
  84     align_addr = 0x1004
  85     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  86                                           align_addr, 4, msr_pr=1)
  87     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  88     assert data == 0xdeadbeef
  89
  90     # load 8 bytes at *mis*-aligned address
  91     misalign_addr = 0x1004
  92     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  93                                           misalign_addr, 8, msr_pr=1)
  94     print ("ldst_sim_misalign", data, exctype, exc)
  95     yield
  96     dar = yield dut.submodules.ldst.dar
  97     print ("DAR", hex(dar))
  98     assert dar == misalign_addr
  99     # check exception bits
 100     assert exc.happened
 101     assert exc.alignment
 102     assert not exc.segment_fault
 103     assert not exc.instr_fault
 104     assert not exc.invalid
 105     assert not exc.perm_error
 106     assert not exc.rc_error
 107     assert not exc.badtree
 108
 109     wbget.stop = True
 110
 111
 112 def test_misalign_mmu():
 113
 114     m, cmpi = setup_mmu()
 115
 116     # virtual "memory" to use for this test
 117
 118     mem = {0x10000:    # PARTITION_TABLE_2
 119                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
 120            b(0x800000000100000b),
 121
 122            0x30000:     # RADIX_ROOT_PTE
 123                         # V = 1 L = 0 NLB = 0x400 NLS = 9
 124            b(0x8000000000040009),
 125
 126            0x40000:     # RADIX_SECOND_LEVEL
 127                         #          V = 1 L = 1 SW = 0 RPN = 0
 128                            # R = 1 C = 1 ATT = 0 EAA 0x7
 129            b(0xc000000000000183),
 130
 131           0x1000000:   # PROCESS_TABLE_3
 132                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
 133            b(0x40000000000300ad),
 134
 135          # data to return
 136           0x1000: 0xdeadbeef01234567,
 137           0x1008: 0xfeedf00ff001a5a5
 138           }
 139
 140
 141     # nmigen Simulation
 142     sim = Simulator(m)
 143     sim.add_clock(1e-6)
 144
 145     sim.add_sync_process(wrap(ldst_sim_misalign(m)))
 146     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 147     with sim.write_vcd('test_ldst_pi_misalign.vcd'):
 148         sim.run()
 149
 150
 151 if __name__ == '__main__':
 152     test_misalign_mmu()