3b4d968c96df1664bd98666b69d3b7f0def8653c
2 from openpower
.decoder
.power_enums
import (XER_bits
, Function
)
4 from soc
.fu
.div
.test
.helper
import get_cu_inputs
5 from soc
.fu
.div
.test
.test_pipe_caller
import DivTestCases
# creates the tests
7 from openpower
.test
.common
import ALUHelpers
8 from soc
.fu
.compunits
.compunits
import DivFSMFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
10 from openpower
.endian
import bigendian
13 class DivTestRunner(TestRunner
):
14 def __init__(self
, test_data
):
15 super().__init
__(test_data
, DivFSMFunctionUnit
, self
,
16 Function
.DIV
, bigendian
)
18 def get_cu_inputs(self
, dec2
, sim
):
19 """naming (res) must conform to DivFunctionUnit input regspec
21 res
= yield from get_cu_inputs(dec2
, sim
)
24 def check_cu_outputs(self
, res
, dec2
, sim
, alu
, code
):
25 """naming (res) must conform to DivFunctionUnit output regspec
28 rc
= yield dec2
.e
.do
.rc
.data
29 op
= yield dec2
.e
.do
.insn_type
30 cridx_ok
= yield dec2
.e
.write_cr
.ok
31 cridx
= yield dec2
.e
.write_cr
.data
33 print("check extra output", repr(code
), cridx_ok
, cridx
)
36 self
.assertEqual(cridx_ok
, 1, code
)
37 self
.assertEqual(cridx
, 0, code
)
41 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
42 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
43 yield from ALUHelpers
.get_wr_sim_xer_ov(sim_o
, sim
, alu
, dec2
)
44 yield from ALUHelpers
.get_wr_sim_xer_so(sim_o
, sim
, alu
, dec2
)
46 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
47 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
48 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
49 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
52 if __name__
== "__main__":
53 unittest
.main(exit
=False)
54 suite
= unittest
.TestSuite()
55 suite
.addTest(DivTestRunner(DivTestCases().test_data
))
57 runner
= unittest
.TextTestRunner()