src/soc/fu/compunits/test/test_logical_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
   5
   6 from soc.fu.compunits.compunits import LogicalFunctionUnit
   7 from soc.fu.compunits.test.test_compunit import TestRunner
   8
   9
  10 class LogicalTestRunner(TestRunner):
  11     def __init__(self, test_data):
  12         super().__init__(test_data, LogicalFunctionUnit, self,
  13                          Function.LOGICAL)
  14
  15     def get_cu_inputs(self, dec2, sim):
  16         """naming (res) must conform to LogicalFunctionUnit input regspec
  17         """
  18         res = yield from get_cu_inputs(dec2, sim)
  19         return res
  20
  21     def check_cu_outputs(self, res, dec2, sim, code):
  22         """naming (res) must conform to LogicalFunctionUnit output regspec
  23         """
  24
  25         # RT
  26         out_reg_valid = yield dec2.e.write_reg.ok
  27         if out_reg_valid:
  28             write_reg_idx = yield dec2.e.write_reg.data
  29             expected = sim.gpr(write_reg_idx).value
  30             cu_out = res['o']
  31             print(f"expected {expected:x}, actual: {cu_out:x}")
  32             self.assertEqual(expected, cu_out, code)
  33
  34         rc = yield dec2.e.rc.data
  35         op = yield dec2.e.insn_type
  36         cridx_ok = yield dec2.e.write_cr.ok
  37         cridx = yield dec2.e.write_cr.data
  38
  39         print ("check extra output", repr(code), cridx_ok, cridx)
  40
  41         if rc:
  42             self.assertEqual(cridx_ok, 1, code)
  43             self.assertEqual(cridx, 0, code)
  44
  45         # CR (CR0-7)
  46         if cridx_ok:
  47             cr_expected = sim.crl[cridx].get_range().value
  48             cr_actual = res['cr_a']
  49             print ("CR", cridx, cr_expected, cr_actual)
  50             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  51
  52         # XER.ca
  53         cry_out = yield dec2.e.output_carry
  54         if cry_out:
  55             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  56             xer_ca = res['xer_ca']
  57             real_carry = xer_ca & 0b1 # XXX CO not CO32
  58             self.assertEqual(expected_carry, real_carry, code)
  59             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  60             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  61             self.assertEqual(expected_carry32, real_carry32, code)
  62
  63
  64 if __name__ == "__main__":
  65     unittest.main(exit=False)
  66     suite = unittest.TestSuite()
  67     suite.addTest(LogicalTestRunner(LogicalTestCase.test_data))
  68
  69     runner = unittest.TextTestRunner()
  70     runner.run(suite)