src/soc/fu/compunits/test/test_spr_compunit.py

   1 import unittest
   2 from openpower.decoder.power_enums import (XER_bits, Function)
   3
   4 from soc.fu.spr.test.test_pipe_caller import get_cu_inputs
   5 from soc.fu.spr.test.test_pipe_caller import SPRTestCase  # creates the tests
   6
   7 from openpower.test.common import ALUHelpers
   8 from soc.fu.compunits.compunits import SPRFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10 from soc.config.endian import bigendian
  11
  12
  13 class SPRTestRunner(TestRunner):
  14     def __init__(self, test_data):
  15         super().__init__(test_data, SPRFunctionUnit, self,
  16                          Function.SPR, bigendian)
  17
  18     def get_cu_inputs(self, dec2, sim):
  19         """naming (res) must conform to SPRFunctionUnit input regspec
  20         """
  21         res = yield from get_cu_inputs(dec2, sim)
  22         return res
  23
  24     def check_cu_outputs(self, res, dec2, sim, alu, code):
  25         """naming (res) must conform to SPRFunctionUnit output regspec
  26         """
  27
  28         rc = yield dec2.e.do.rc.data
  29         op = yield dec2.e.do.insn_type
  30         cridx_ok = yield dec2.e.write_cr.ok
  31         cridx = yield dec2.e.write_cr.data
  32
  33         print("check extra output", repr(code), cridx_ok, cridx)
  34
  35         if rc:
  36             self.assertEqual(cridx_ok, 1, code)
  37             self.assertEqual(cridx, 0, code)
  38
  39         sim_o = {}
  40
  41         yield from ALUHelpers.get_int_o(res, alu, dec2)
  42         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
  43         yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
  44         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
  45         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
  46         yield from ALUHelpers.get_xer_so(res, alu, dec2)
  47
  48         print("output", res)
  49
  50         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
  51         yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
  52         yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
  53         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
  54         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
  55         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
  56
  57         print("sim output", sim_o)
  58
  59         ALUHelpers.check_xer_ov(self, res, sim_o, code)
  60         ALUHelpers.check_xer_ca(self, res, sim_o, code)
  61         ALUHelpers.check_xer_so(self, res, sim_o, code)
  62         ALUHelpers.check_int_o(self, res, sim_o, code)
  63         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
  64         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
  65
  66
  67 if __name__ == "__main__":
  68     unittest.main(exit=False)
  69     suite = unittest.TestSuite()
  70     suite.addTest(SPRTestRunner(SPRTestCase().test_data))
  71
  72     runner = unittest.TextTestRunner()
  73     runner.run(suite)