src/soc/fu/compunits/test/test_spr_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 from soc.fu.spr.test.test_pipe_caller import get_cu_inputs
   5 from soc.fu.spr.test.test_pipe_caller import SPRTestCase  # creates the tests
   6
   7 from soc.fu.test.common import ALUHelpers
   8 from soc.fu.compunits.compunits import SPRFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class SPRTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, SPRFunctionUnit, self,
  15                          Function.SPR)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to SPRFunctionUnit input regspec
  19         """
  20         res = yield from get_cu_inputs(dec2, sim)
  21         return res
  22
  23     def check_cu_outputs(self, res, dec2, sim, alu, code):
  24         """naming (res) must conform to SPRFunctionUnit output regspec
  25         """
  26
  27         rc = yield dec2.e.do.rc.data
  28         op = yield dec2.e.do.insn_type
  29         cridx_ok = yield dec2.e.write_cr.ok
  30         cridx = yield dec2.e.write_cr.data
  31
  32         print("check extra output", repr(code), cridx_ok, cridx)
  33
  34         if rc:
  35             self.assertEqual(cridx_ok, 1, code)
  36             self.assertEqual(cridx, 0, code)
  37
  38         sim_o = {}
  39
  40         yield from ALUHelpers.get_int_o(res, alu, dec2)
  41         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
  42         yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
  43         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
  44         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
  45         yield from ALUHelpers.get_xer_so(res, alu, dec2)
  46
  47         print("output", res)
  48
  49         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
  50         yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
  51         yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
  52         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
  53         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
  54         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
  55
  56         print("sim output", sim_o)
  57
  58         ALUHelpers.check_xer_ov(self, res, sim_o, code)
  59         ALUHelpers.check_xer_ca(self, res, sim_o, code)
  60         ALUHelpers.check_xer_so(self, res, sim_o, code)
  61         ALUHelpers.check_int_o(self, res, sim_o, code)
  62         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
  63         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
  64
  65
  66 if __name__ == "__main__":
  67     unittest.main(exit=False)
  68     suite = unittest.TestSuite()
  69     suite.addTest(SPRTestRunner(SPRTestCase.test_data))
  70
  71     runner = unittest.TextTestRunner()
  72     runner.run(suite)