313f56f19235f3cdd45b6b3c4cd06d173bc457f3
[soc.git] / src / soc / fu / compunits.py
1 ###################################################################
2 """Function Units Construction
3
4 This module pulls all of the pipelines together (soc.fu.*) and, using
5 the regspec and Computation Unit APIs, constructs Scoreboard-aware
6 Function Units that may systematically and automatically be wired up
7 to appropriate Register Files.
8
9 Two types exist:
10
11 * Single-cycle Function Units. these are FUs that will only block for
12 one cycle. it is expected that multiple of these be instantiated,
13 because they are simple and trivial, and not many gates.
14
15 - ALU, Logical: definitely several
16 - CR: not so many needed (perhaps)
17 - Branch: one or two of these (depending on speculation run-ahead)
18 - Trap: yeah really only one of these
19 - ShiftRot (perhaps not too many of these)
20
21 * Multi-cycle (and FSM) Function Units. these are FUs that can only
22 handle a limited number of values, and take several cycles to complete.
23 Given that under Scoreboard Management, start and completion must be
24 fully managed, a "Reservation Station" style approach is required:
25 *one* multiple-stage (N stage) pipelines need a minimum of N (plural)
26 "CompUnit" front-ends. this includes:
27
28 - MUL (all versions including MAC)
29 - DIV (including modulo)
30
31 In either case, there will be multiple MultiCompUnits: it's just that
32 single-cycle ones are instantiated individually (one single-cycle pipeline
33 per MultiCompUnit, and multi-cycle ones need to be instantiated en-masse,
34 where *only one* actual pipeline (or FSM) has *multiple* Reservation
35 Stations.
36
37 see:
38
39 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
40
41 """
42
43 from nmigen.cli import rtlil
44 from soc.experiment.compalu_multi import MultiCompUnit
45
46 # pipeline / spec imports
47
48 from soc.fu.alu.pipeline import ALUBasePipe
49 from soc.fu.alu.pipe_data import ALUPipeSpec
50
51 from soc.fu.cr.pipeline import CRBasePipe
52 from soc.fu.cr.pipe_data import CRPipeSpec
53
54
55 ###################################################################
56 ###### FunctionUnitBaseSingle - use to make single-stge pipes #####
57
58 class FunctionUnitBaseSingle(MultiCompUnit):
59 """FunctionUnitBaseSingle
60
61 main "glue" class that brings everything together.
62 ONLY use this class for single-stage pipelines.
63
64 * :speckls: - the specification. contains regspec and op subset info,
65 and contains common "stuff" like the pipeline ctx,
66 what type of nmutil pipeline base is to be used (etc)
67 * :pipekls: - the type of pipeline. actually connects things together
68
69 note that it is through MultiCompUnit.get_in/out that we *actually*
70 connect up the association between regspec variable names (defined
71 in the pipe_data).
72 """
73 def __init__(self, speckls, pipekls):
74 pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance)
75 opsubset = pspec.opsubsetkls # get the operand subset class
76 regspec = pspec.regspec # get the regspec
77 alu = pipekls(pspec) # create actual NNNBasePipe
78 super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
79
80
81 ##############################################################
82 # TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
83
84 class FunctionUnitBaseMulti:
85 pass
86
87
88 ######################################################################
89 ###### actual Function Units: these are "single" stage pipelines #####
90
91 class ALUFunctionUnit(FunctionUnitBaseSingle):
92 def __init__(self): super().__init__(ALUPipeSpec, ALUBasePipe)
93
94 class CRFunctionUnit(FunctionUnitBaseSingle):
95 def __init__(self): super().__init__(CRPipeSpec, CRBasePipe)
96
97
98 #####################################################################
99 ###### actual Function Units: these are "multi" stage pipelines #####
100
101 # TODO: ReservationStations-based.
102
103
104 def tst_single_fus_il():
105 for (name, kls) in (('alu', ALUFunctionUnit),
106 ('cr', CRFunctionUnit)):
107 fu = kls()
108 vl = rtlil.convert(fu, ports=fu.ports())
109 with open("fu_%s.il" % name, "w") as f:
110 f.write(vl)
111
112 if __name__ == '__main__':
113 tst_single_fus_il()