src/soc/fu/cr/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   4 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
   5 from soc.decoder.power_decoder2 import Data
   6
   7
   8 class CRInputData(IntegerData):
   9     regspec = [('INT', 'a', '0:63'),      # 64 bit range
  10                ('CR', 'full_cr', '0:31'), # 32 bit range
  11                ('CR', 'cr_a', '0:3'),     # 4 bit range
  12                ('CR', 'cr_b', '0:3'),     # 4 bit range
  13                ('CR', 'cr_c', '0:3')]     # 4 bit range
  14     def __init__(self, pspec):
  15         super().__init__(pspec)
  16         self.a = Signal(64, reset_less=True) # RA
  17         self.full_cr = Signal(32, reset_less=True) # full CR in
  18         self.cr_a = Signal(4, reset_less=True)
  19         self.cr_b = Signal(4, reset_less=True)
  20         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
  21
  22     def __iter__(self):
  23         yield from super().__iter__()
  24         yield self.a
  25         yield self.full_cr
  26         yield self.cr_a
  27         yield self.cr_b
  28         yield self.cr_c
  29
  30     def eq(self, i):
  31         lst = super().eq(i)
  32         return lst + [self.a.eq(i.a),
  33                       self.full_cr.eq(i.full_cr),
  34                       self.cr_a.eq(i.cr_a),
  35                       self.cr_b.eq(i.cr_b),
  36                       self.cr_c.eq(i.cr_c)]
  37
  38
  39 class CROutputData(IntegerData):
  40     regspec = [('INT', 'o', '0:63'),      # 64 bit range
  41                ('CR', 'full_cr', '0:31'), # 32 bit range
  42                ('CR', 'cr_o', '0:3')]     # 4 bit range
  43     def __init__(self, pspec):
  44         super().__init__(pspec)
  45         self.o = Signal(64, reset_less=True) # RA
  46         self.full_cr = Data(32, name="cr_out") # CR in
  47         self.cr_o = Data(4, name="cr_o")
  48
  49     def __iter__(self):
  50         yield from super().__iter__()
  51         yield self.o
  52         yield self.full_cr
  53         yield self.cr_o
  54
  55     def eq(self, i):
  56         lst = super().eq(i)
  57         return lst + [self.o.eq(i.o),
  58                       self.full_cr.eq(i.full_cr),
  59                       self.cr_o.eq(i.cr_o)]
  60
  61 # TODO: replace CompALUOpSubset with CompCROpSubset
  62 class CRPipeSpec(CommonPipeSpec):
  63     regspec = (CRInputData.regspec, CROutputData.regspec)
  64     opsubsetkls = CompALUOpSubset