009f1fbc5e63caa579f3fbf3337f54941760c7df
3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
5 this module is a key strategic module that links pipeline specifications
6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits. MultiCompUnits
7 know absolutely nothing about the data passing through them: all they know
8 is: how many inputs they need to manage, and how many outputs.
10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
15 again, the regspecs will say which Regfile (which type) is connected to
16 which MultiCompUnit port, how wide the connection is, and so on.
21 def get_regspec_bitwidth(regspec
, srcdest
, idx
):
22 bitspec
= regspec
[srcdest
][idx
]
25 for ranges
in bitspec
[2].split(","):
26 ranges
= ranges
.split(":")
28 if len(ranges
) == 1: # only one bit
31 start
, end
= map(int, ranges
)
37 def __init__(self
, rwid
, n_src
=None, n_dst
=None, name
=None):
39 if isinstance(rwid
, int):
40 # rwid: integer (covers all registers)
41 self
._n
_src
, self
._n
_dst
= n_src
, n_dst
44 self
._n
_src
, self
._n
_dst
= len(rwid
[0]), len(rwid
[1])
46 def _get_dstwid(self
, i
):
47 if isinstance(self
._rwid
, int):
49 return get_regspec_bitwidth(self
._rwid
, 1, i
)
51 def _get_srcwid(self
, i
):
52 if isinstance(self
._rwid
, int):
54 return get_regspec_bitwidth(self
._rwid
, 0, i
)
58 def __init__(self
, rwid
, alu
):
62 * :alu: ALU covered by this regspec
65 self
.alu
= alu
# actual ALU - set as a "submodule" of the CU
68 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
69 return self
.alu
.out
[i
]
70 # regspec-based API: look up variable through regspec thru row number
71 return getattr(self
.alu
.n
.data_o
, self
.rwid
[1][i
][1])
74 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
76 # regspec-based API: look up variable through regspec thru row number
77 return getattr(self
.alu
.p
.data_i
, self
.rwid
[0][i
][1])
80 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
82 return self
.alu
.p
.data_i
.ctx
.op