src/soc/fu/shift_rot/rotator.py

   1 # Manual translation and adaptation of rotator.vhdl from microwatt into nmigen
   2 #
   3
   4 from nmigen import (Elaboratable, Signal, Module, Const, Cat, Repl,
   5                     unsigned, signed)
   6 from soc.fu.shift_rot.rotl import ROTL
   7 from nmutil.extend import exts
   8
   9
  10 # note BE bit numbering
  11 def right_mask(m, mask_begin):
  12     ret = Signal(64, name="right_mask", reset_less=True)
  13     with m.If(mask_begin <= 64):
  14         m.d.comb += ret.eq((1<<(64-mask_begin)) - 1)
  15     return ret
  16
  17 def left_mask(m, mask_end):
  18     ret = Signal(64, name="left_mask", reset_less=True)
  19     m.d.comb += ret.eq(~((1<<(63-mask_end)) - 1))
  20     return ret
  21
  22
  23 class Rotator(Elaboratable):
  24     """Rotator: covers multiple POWER9 rotate functions
  25
  26         supported modes:
  27
  28         * sl[wd]
  29         * rlw*, rldic, rldicr, rldimi
  30         * rldicl, sr[wd]
  31         * sra[wd][i]
  32
  33         use as follows:
  34
  35         * shift = RB[0:7]
  36         * arith = 1 when is_signed
  37         * right_shift = 1 when insn_type is OP_SHR
  38         * clear_left = 1 when insn_type is OP_RLC or OP_RLCL
  39         * clear_right = 1 when insn_type is OP_RLC or OP_RLCR
  40     """
  41     def __init__(self):
  42         # input
  43         self.me = Signal(5, reset_less=True)        # ME field
  44         self.mb = Signal(5, reset_less=True)        # MB field
  45         self.mb_extra = Signal(1, reset_less=True)  # extra bit of mb in MD-form
  46         self.ra = Signal(64, reset_less=True)       # RA
  47         self.rs = Signal(64, reset_less=True)       # RS
  48         self.shift = Signal(7, reset_less=True)     # RB[0:7]
  49         self.is_32bit = Signal(reset_less=True)
  50         self.right_shift = Signal(reset_less=True)
  51         self.arith = Signal(reset_less=True)
  52         self.clear_left = Signal(reset_less=True)
  53         self.clear_right = Signal(reset_less=True)
  54         self.sign_ext_rs = Signal(reset_less=True)
  55         # output
  56         self.result_o = Signal(64, reset_less=True)
  57         self.carry_out_o = Signal(reset_less=True)
  58
  59     def elaborate(self, platform):
  60         m = Module()
  61         comb = m.d.comb
  62         ra, rs = self.ra, self.rs
  63
  64         # temporaries
  65         rot_count = Signal(6, reset_less=True)
  66         rot = Signal(64, reset_less=True)
  67         sh = Signal(7, reset_less=True)
  68         mb = Signal(7, reset_less=True)
  69         me = Signal(7, reset_less=True)
  70         mr = Signal(64, reset_less=True)
  71         ml = Signal(64, reset_less=True)
  72         output_mode = Signal(2, reset_less=True)
  73         hi32 = Signal(32, reset_less=True)
  74         repl32 = Signal(64, reset_less=True)
  75
  76         # First replicate bottom 32 bits to both halves if 32-bit
  77         with m.If(self.is_32bit):
  78             comb += hi32.eq(rs[0:32])
  79         with m.Elif(self.sign_ext_rs):
  80             # sign-extend bottom 32 bits
  81             comb += hi32.eq(Repl(rs[31], 32))
  82         with m.Else():
  83             comb += hi32.eq(rs[32:64])
  84         comb += repl32.eq(Cat(rs[0:32], hi32))
  85
  86         shift_signed = Signal(signed(6))
  87         comb += shift_signed.eq(self.shift[0:6])
  88
  89         # Negate shift count for right shifts
  90         with m.If(self.right_shift):
  91             comb += rot_count.eq(-shift_signed)
  92         with m.Else():
  93             comb += rot_count.eq(self.shift[0:6])
  94
  95         # ROTL submodule
  96         m.submodules.rotl = rotl = ROTL(64)
  97         comb += rotl.a.eq(repl32)
  98         comb += rotl.b.eq(rot_count)
  99         comb += rot.eq(rotl.o)
 100
 101         # Trim shift count to 6 bits for 32-bit shifts
 102         comb += sh.eq(Cat(self.shift[0:6], self.shift[6] & ~self.is_32bit))
 103
 104         # XXX errr... we should already have these, in Fields?  oh well
 105         # Work out mask begin/end indexes (caution, big-endian bit numbering)
 106
 107         # mask-begin (mb)
 108         with m.If(self.clear_left):
 109             comb += mb.eq(self.mb)
 110             with m.If(self.is_32bit):
 111                 comb += mb[5:7].eq(Const(0b01, 2))
 112             with m.Else():
 113                 comb += mb[5:7].eq(Cat(self.mb_extra, Const(0b0, 1)))
 114         with m.Elif(self.right_shift):
 115             # this is basically mb = sh + (is_32bit? 32: 0);
 116             comb += mb.eq(sh)
 117             with m.If(self.is_32bit):
 118                 comb += mb[5:7].eq(Cat(~sh[5], sh[5]))
 119         with m.Else():
 120             comb += mb.eq(Cat(Const(0b0, 5), self.is_32bit, Const(0b0, 1)))
 121
 122         # mask-end (me)
 123         with m.If(self.clear_right & self.is_32bit):
 124             # TODO: track down where this is.  have to use fields.
 125             comb += me.eq(Cat(self.me, Const(0b01, 2)))
 126         with m.Elif(self.clear_right & ~self.clear_left):
 127             # this is me, have to use fields
 128             comb += me.eq(Cat(self.mb, self.mb_extra, Const(0b0, 1)))
 129         with m.Else():
 130             # effectively, 63 - sh
 131             comb += me.eq(Cat(~sh[0:6], sh[6]))
 132
 133         # Calculate left and right masks
 134         comb += mr.eq(right_mask(m, mb))
 135         comb += ml.eq(left_mask(m, me))
 136
 137         # Work out output mode
 138         # 00 for sl[wd]
 139         # 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
 140         # 10 for rldicl, sr[wd]
 141         # 1z for sra[wd][i], z = 1 if rs is negative
 142         with m.If((self.clear_left & ~self.clear_right) | self.right_shift):
 143             comb += output_mode.eq(Cat(self.arith & repl32[63], Const(1, 1)))
 144         with m.Else():
 145             mbgt = self.clear_right & (mb[0:6] > me[0:6])
 146             comb += output_mode.eq(Cat(mbgt, Const(0, 1)))
 147
 148         # Generate output from rotated input and masks
 149         with m.Switch(output_mode):
 150             with m.Case(0b00):
 151                 comb += self.result_o.eq((rot & (mr & ml)) | (ra & ~(mr & ml)))
 152             with m.Case(0b01):
 153                 comb += self.result_o.eq((rot & (mr | ml)) | (ra & ~(mr | ml)))
 154             with m.Case(0b10):
 155                 comb += self.result_o.eq(rot & mr)
 156             with m.Case(0b11):
 157                 comb += self.result_o.eq(rot | ~mr)
 158                 # Generate carry output for arithmetic shift right of -ve value
 159                 comb += self.carry_out_o.eq((rs & ~ml).bool() & rs[0])
 160
 161         return m
 162