src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard"]
   9
  10
  11 class LibreSoC(CPU):
  12     name                 = "libre_soc"
  13     human_name           = "Libre-SoC"
  14     variants             = CPU_VARIANTS
  15     data_width           = 64
  16     endianness           = "little"
  17     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  18     linker_output_format = "elf64-powerpcle"
  19     nop                  = "nop"
  20     io_regions           = {0xc0000000: 0x10000000} # origin, length
  21
  22     @property
  23     def mem_map(self):
  24         return {"csr": 0xc0000000}
  25
  26     @property
  27     def gcc_flags(self):
  28         flags  = "-m64 "
  29         flags += "-mabi=elfv2 "
  30         flags += "-msoft-float "
  31         flags += "-mno-string "
  32         flags += "-mno-multiple "
  33         flags += "-mno-vsx "
  34         flags += "-mno-altivec "
  35         flags += "-mlittle-endian "
  36         flags += "-mstrict-align "
  37         flags += "-fno-stack-protector "
  38         flags += "-mcmodel=small "
  39         flags += "-D__microwatt__ "
  40         return flags
  41
  42     def __init__(self, platform, variant="standard"):
  43         self.platform     = platform
  44         self.variant      = variant
  45         self.reset        = Signal()
  46
  47         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
  48         self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
  49
  50         self.periph_buses = [ibus, dbus]
  51         self.memory_buses = []
  52
  53         self.dmi_addr = Signal(3)
  54         self.dmi_din = Signal(64)
  55         self.dmi_dout = Signal(64)
  56         self.dmi_wr = Signal(1)
  57         self.dmi_ack = Signal(1)
  58         self.dmi_req = Signal(1)
  59
  60         # # #
  61
  62         self.cpu_params = dict(
  63             # Clock / Reset
  64             i_clk              = ClockSignal(),
  65             i_rst              = ResetSignal() | self.reset,
  66
  67             # IBus
  68             o_ibus__stb        = ibus.stb,
  69             o_ibus__cyc        = ibus.cyc,
  70             o_ibus__cti        = ibus.cti,
  71             o_ibus__bte        = ibus.bte,
  72             o_ibus__we         = ibus.we,
  73             o_ibus__adr        = Cat(ibus.adr), # bytes to words addressing
  74             o_ibus__dat_w      = ibus.dat_w,
  75             o_ibus__sel        = ibus.sel,
  76             i_ibus__ack        = ibus.ack,
  77             i_ibus__err        = ibus.err,
  78             i_ibus__dat_r      = ibus.dat_r,
  79
  80             # DBus
  81             o_dbus__stb        = dbus.stb,
  82             o_dbus__cyc        = dbus.cyc,
  83             o_dbus__cti        = dbus.cti,
  84             o_dbus__bte        = dbus.bte,
  85             o_dbus__we         = dbus.we,
  86             o_dbus__adr        = Cat(dbus.adr), # bytes to words addressing
  87             o_dbus__dat_w      = dbus.dat_w,
  88             o_dbus__sel        = dbus.sel,
  89             i_dbus__ack        = dbus.ack,
  90             i_dbus__err        = dbus.err,
  91             i_dbus__dat_r      = dbus.dat_r,
  92
  93             # Monitoring / Debugging
  94             i_pc_i             = 0,
  95             i_pc_i_ok          = 0,
  96             i_core_bigendian_i = 0, # Signal(),
  97             o_busy_o           = Signal(),
  98             o_memerr_o         = Signal(),
  99
 100             # Debug bus
 101             i_dmi_addr_i          = self.dmi_addr,
 102             i_dmi_din             = self.dmi_din,
 103             o_dmi_dout            = self.dmi_dout,
 104             i_dmi_req_i           = self.dmi_req,
 105             i_dmi_we_i            = self.dmi_wr,
 106             o_dmi_ack_o           = self.dmi_ack,
 107         )
 108
 109         # add verilog sources
 110         self.add_sources(platform)
 111
 112     def set_reset_address(self, reset_address):
 113         assert not hasattr(self, "reset_address")
 114         self.reset_address = reset_address
 115         assert reset_address == 0x00000000
 116
 117     @staticmethod
 118     def add_sources(platform):
 119         cdir = os.path.dirname(__file__)
 120         platform.add_source(os.path.join(cdir, "libresoc.v"))
 121
 122     def do_finalize(self):
 123         self.specials += Instance("test_issuer", **self.cpu_params)
 124