49f32b3db4fde915071b52f30da24dbbf6cc9a21
2 # This file is part of LiteX.
4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
5 # SPDX-License-Identifier: BSD-2-Clause
9 conceptually similar to the following:
11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
15 Fits in a JEDEC QFP-100
19 from migen
.fhdl
.structure
import _Fragment
20 from litex
.build
.generic_platform
import (GenericPlatform
, Pins
,
21 Subsignal
, IOStandard
, Misc
,
23 from libresoc
.ls180io
import make_uart
, make_gpio
27 # IOs ----------------------------------------------------------------------------------------------
31 ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
32 ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
36 Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
37 Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
38 Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
39 Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
44 Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
45 Subsignal("sda", Pins("M1"), IOStandard("LVCMOS33"))
50 Subsignal("clk", Pins("J1")),
51 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
52 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
53 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
54 Misc("SLEWRATE=FAST"),
55 IOStandard("LVCMOS33"),
60 Subsignal("clk", Pins("J1")),
61 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
62 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
63 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
64 Misc("SLEWRATE=FAST"),
65 IOStandard("LVCMOS33"),
70 Subsignal("clk", Pins("J1")),
71 Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
72 Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
73 Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
74 Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
75 Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
76 Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
77 Misc("SLEWRATE=FAST"),
78 IOStandard("LVCMOS33"),
82 ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
85 "M20 M19 L20 L19 K20 K19 K18 J20",
86 "J19 H20 N19 G20 G19")),
87 Subsignal("dq_i", Pins(
88 "J16 L18 M18 N18 P18 T18 T17 U20",
89 "E19 D20 D19 C20 E18 F18 J18 J17")),
90 Subsignal("dq_o", Pins(
91 "J16 L18 M18 N18 P18 T18 T17 U20",
92 "E19 D20 D19 C20 E18 F18 J18 J17")),
93 Subsignal("dq_oe", Pins("J17")),
94 Subsignal("we_n", Pins("T20")),
95 Subsignal("ras_n", Pins("R20")),
96 Subsignal("cas_n", Pins("T19")),
97 Subsignal("cs_n", Pins("P30")),
98 Subsignal("cke", Pins("F21")),
99 Subsignal("ba", Pins("P19 N20")),
100 Subsignal("dm", Pins("U19 E20")),
101 IOStandard("LVCMOS33"),
102 Misc("SLEWRATE=FAST"),
106 ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
107 ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
113 _io
.append( make_gpio("gpio", 0, n_gpio
) )
116 _io
.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
119 _io
.append(make_uart("uart", 0))
121 _io
.append(make_uart("uart", 1))
123 # not connected - eurgh have to adjust this to match the total pincount.
125 nc
= ' '.join("NC%d" % i
for i
in range(num_nc
))
126 _io
.append(("nc", 0, Pins(nc
), IOStandard("LVCMOS33")))
128 # Platform -----------------------------------------------------------------------------------------
130 class LS180Platform(GenericPlatform
):
131 default_clk_name
= "sys_clk"
132 default_clk_period
= 1e9
/50e6
134 def __init__(self
, device
="LS180", **kwargs
):
135 assert device
in ["LS180"]
136 GenericPlatform
.__init
__(self
, device
, _io
, **kwargs
)
138 def build(self
, fragment
,
147 # Create build directory
148 os
.makedirs(build_dir
, exist_ok
=True)
153 if not isinstance(fragment
, _Fragment
):
154 fragment
= fragment
.get_fragment()
155 platform
.finalize(fragment
)
158 v_output
= platform
.get_verilog(fragment
, name
=build_name
, **kwargs
)
159 named_sc
, named_pc
= platform
.resolve_signals(v_output
.ns
)
160 v_file
= build_name
+ ".v"
161 v_output
.write(v_file
)
162 platform
.add_source(v_file
)
168 def do_finalize(self
, fragment
):
169 super().do_finalize(fragment
)
171 self
.add_period_constraint(self
.lookup_request("clk", loose
=True),